2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
13 #include "am4372.dtsi"
14 #include <dt-bindings/pinctrl/am43xx.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pwm/pwm.h>
19 model = "TI AM43x EPOS EVM";
20 compatible = "ti,am43x-epos-evm","ti,am4372","ti,am43";
22 vmmcsd_fixed: fixedregulator-sd {
23 compatible = "regulator-fixed";
24 regulator-name = "vmmcsd_fixed";
25 regulator-min-microvolt = <3300000>;
26 regulator-max-microvolt = <3300000>;
30 am43xx_pinmux: pinmux@44e10800 {
31 cpsw_default: cpsw_default {
32 pinctrl-single,pins = <
34 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */
35 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */
36 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */
37 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxdv.rmii1_rxdv */
38 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
39 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
40 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
41 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
42 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */
46 cpsw_sleep: cpsw_sleep {
47 pinctrl-single,pins = <
48 /* Slave 1 reset value */
49 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
50 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
51 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
52 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
53 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
54 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
55 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
56 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
57 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
61 davinci_mdio_default: davinci_mdio_default {
62 pinctrl-single,pins = <
64 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
65 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
69 davinci_mdio_sleep: davinci_mdio_sleep {
70 pinctrl-single,pins = <
71 /* MDIO reset value */
72 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
73 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
77 i2c0_pins: pinmux_i2c0_pins {
78 pinctrl-single,pins = <
79 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
80 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
84 nand_flash_x8: nand_flash_x8 {
85 pinctrl-single,pins = <
86 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.SELQSPIorNAND/GPIO */
87 0x0 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
88 0x4 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
89 0x8 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
90 0xc (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
91 0x10 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
92 0x14 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
93 0x18 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
94 0x1c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
95 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
96 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
97 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
98 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
99 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
100 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
101 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
105 ecap0_pins: backlight_pins {
106 pinctrl-single,pins = <
107 0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
111 i2c2_pins: pinmux_i2c2_pins {
112 pinctrl-single,pins = <
113 0x1c0 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_sda.i2c2_sda */
114 0x1c4 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_scl.i2c2_scl */
118 spi0_pins: pinmux_spi0_pins {
119 pinctrl-single,pins = <
120 0x150 (PIN_INPUT | MUX_MODE0) /* spi0_clk.spi0_clk */
121 0x154 (PIN_OUTPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */
122 0x158 (PIN_INPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */
123 0x15c (PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
127 spi1_pins: pinmux_spi1_pins {
128 pinctrl-single,pins = <
129 0x190 (PIN_INPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_clk */
130 0x194 (PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */
131 0x198 (PIN_INPUT | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */
132 0x19c (PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */
136 mmc1_pins: pinmux_mmc1_pins {
137 pinctrl-single,pins = <
138 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
143 matrix_keypad: matrix_keypad@0 {
144 compatible = "gpio-matrix-keypad";
145 debounce-delay-ms = <5>;
146 col-scan-delay-us = <2>;
148 row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */
149 &gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */
150 &gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */
151 &gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */
153 col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */
154 &gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */
155 &gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */
156 &gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */
158 linux,keymap = <0x00000201 /* P1 */
161 0x0300020a /* NUMERIC_STAR */
169 0x0302020b /* NUMERIC_POUND */
171 0x0103006a /* RIGHT */
172 0x0203006c /* DOWN */
173 0x03030069>; /* LEFT */
177 compatible = "pwm-backlight";
178 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
179 brightness-levels = <0 51 53 56 62 75 101 152 255>;
180 default-brightness-level = <8>;
186 vmmc-supply = <&vmmcsd_fixed>;
188 pinctrl-names = "default";
189 pinctrl-0 = <&mmc1_pins>;
190 cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
194 pinctrl-names = "default", "sleep";
195 pinctrl-0 = <&cpsw_default>;
196 pinctrl-1 = <&cpsw_sleep>;
201 pinctrl-names = "default", "sleep";
202 pinctrl-0 = <&davinci_mdio_default>;
203 pinctrl-1 = <&davinci_mdio_sleep>;
208 phy_id = <&davinci_mdio>, <16>;
213 phy_id = <&davinci_mdio>, <1>;
219 pinctrl-names = "default";
220 pinctrl-0 = <&i2c0_pins>;
223 compatible = "at24,24c256";
229 compatible = "pixcir,pixcir_ts";
231 interrupt-parent = <&gpio1>;
234 attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
242 pinctrl-names = "default";
243 pinctrl-0 = <&i2c2_pins>;
269 pinctrl-names = "default";
270 pinctrl-0 = <&nand_flash_x8>;
271 ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
273 reg = <0 0 0>; /* CS0, offset 0 */
274 ti,nand-ecc-opt = "bch8";
276 nand-bus-width = <8>;
277 gpmc,device-width = <1>;
278 gpmc,sync-clk-ps = <0>;
280 gpmc,cs-rd-off-ns = <40>; /* tCEA + tCHZ + 1 */
281 gpmc,cs-wr-off-ns = <40>;
282 gpmc,adv-on-ns = <0>; /* cs-on-ns */
283 gpmc,adv-rd-off-ns = <25>; /* min( tALH + tALS + 1) */
284 gpmc,adv-wr-off-ns = <25>; /* min( tALH + tALS + 1) */
285 gpmc,we-on-ns = <0>; /* cs-on-ns */
286 gpmc,we-off-ns = <20>; /* we-on-time + tWP + 2 */
287 gpmc,oe-on-ns = <3>; /* cs-on-ns + tRR + 2 */
288 gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */
289 gpmc,access-ns = <30>; /* tCEA + 4*/
290 gpmc,rd-cycle-ns = <40>;
291 gpmc,wr-cycle-ns = <40>;
292 gpmc,wait-on-read = "true";
293 gpmc,wait-on-write = "true";
294 gpmc,bus-turnaround-ns = <0>;
295 gpmc,cycle2cycle-delay-ns = <0>;
296 gpmc,clk-activation-ns = <0>;
297 gpmc,wait-monitoring-ns = <0>;
298 gpmc,wr-access-ns = <40>;
299 gpmc,wr-data-mux-bus-ns = <0>;
300 /* MTD partition table */
301 /* All SPL-* partitions are sized to minimal length
302 * which can be independently programmable. For
303 * NAND flash this is equal to size of erase-block */
304 #address-cells = <1>;
308 reg = <0x00000000 0x00040000>;
311 label = "NAND.SPL.backup1";
312 reg = <0x00040000 0x00040000>;
315 label = "NAND.SPL.backup2";
316 reg = <0x00080000 0x00040000>;
319 label = "NAND.SPL.backup3";
320 reg = <0x000C0000 0x00040000>;
323 label = "NAND.u-boot-spl-os";
324 reg = <0x00100000 0x00080000>;
327 label = "NAND.u-boot";
328 reg = <0x00180000 0x00100000>;
331 label = "NAND.u-boot-env";
332 reg = <0x00280000 0x00040000>;
335 label = "NAND.u-boot-env.backup1";
336 reg = <0x002C0000 0x00040000>;
339 label = "NAND.kernel";
340 reg = <0x00300000 0x00700000>;
343 label = "NAND.file-system";
344 reg = <0x00800000 0x1F600000>;
355 pinctrl-names = "default";
356 pinctrl-0 = <&ecap0_pins>;
360 pinctrl-names = "default";
361 pinctrl-0 = <&spi0_pins>;
366 pinctrl-names = "default";
367 pinctrl-0 = <&spi1_pins>;