arch/arm/boot/dts/am437x-idk-evm.dts

   1 /*
   2  * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /dts-v1/;
  10
  11 #include "am4372.dtsi"
  12 #include <dt-bindings/pinctrl/am43xx.h>
  13 #include <dt-bindings/pwm/pwm.h>
  14 #include <dt-bindings/gpio/gpio.h>
  15 #include <dt-bindings/input/input.h>
  16
  17 / {
  18         model = "TI AM437x Industrial Development Kit";
  19         compatible = "ti,am437x-idk-evm","ti,am4372","ti,am43";
  20
  21         v24_0d: fixed-regulator-v24_0d {
  22                 compatible = "regulator-fixed";
  23                 regulator-name = "V24_0D";
  24                 regulator-min-microvolt = <24000000>;
  25                 regulator-max-microvolt = <24000000>;
  26                 regulator-always-on;
  27                 regulator-boot-on;
  28         };
  29
  30         v3_3d: fixed-regulator-v3_3d {
  31                 compatible = "regulator-fixed";
  32                 regulator-name = "V3_3D";
  33                 regulator-min-microvolt = <3300000>;
  34                 regulator-max-microvolt = <3300000>;
  35                 regulator-always-on;
  36                 regulator-boot-on;
  37                 vin-supply = <&v24_0d>;
  38         };
  39
  40         vdd_corereg: fixed-regulator-vdd_corereg {
  41                 compatible = "regulator-fixed";
  42                 regulator-name = "VDD_COREREG";
  43                 regulator-min-microvolt = <1100000>;
  44                 regulator-max-microvolt = <1100000>;
  45                 regulator-always-on;
  46                 regulator-boot-on;
  47                 vin-supply = <&v24_0d>;
  48         };
  49
  50         vdd_core: fixed-regulator-vdd_core {
  51                 compatible = "regulator-fixed";
  52                 regulator-name = "VDD_CORE";
  53                 regulator-min-microvolt = <1100000>;
  54                 regulator-max-microvolt = <1100000>;
  55                 regulator-always-on;
  56                 regulator-boot-on;
  57                 vin-supply = <&vdd_corereg>;
  58         };
  59
  60         v1_8dreg: fixed-regulator-v1_8dreg{
  61                 compatible = "regulator-fixed";
  62                 regulator-name = "V1_8DREG";
  63                 regulator-min-microvolt = <1800000>;
  64                 regulator-max-microvolt = <1800000>;
  65                 regulator-always-on;
  66                 regulator-boot-on;
  67                 vin-supply = <&v24_0d>;
  68         };
  69
  70         v1_8d: fixed-regulator-v1_8d{
  71                 compatible = "regulator-fixed";
  72                 regulator-name = "V1_8D";
  73                 regulator-min-microvolt = <1800000>;
  74                 regulator-max-microvolt = <1800000>;
  75                 regulator-always-on;
  76                 regulator-boot-on;
  77                 vin-supply = <&v1_8dreg>;
  78         };
  79
  80         v1_5dreg: fixed-regulator-v1_5dreg{
  81                 compatible = "regulator-fixed";
  82                 regulator-name = "V1_5DREG";
  83                 regulator-min-microvolt = <1500000>;
  84                 regulator-max-microvolt = <1500000>;
  85                 regulator-always-on;
  86                 regulator-boot-on;
  87                 vin-supply = <&v24_0d>;
  88         };
  89
  90         v1_5d: fixed-regulator-v1_5d{
  91                 compatible = "regulator-fixed";
  92                 regulator-name = "V1_5D";
  93                 regulator-min-microvolt = <1500000>;
  94                 regulator-max-microvolt = <1500000>;
  95                 regulator-always-on;
  96                 regulator-boot-on;
  97                 vin-supply = <&v1_5dreg>;
  98         };
  99 };
 100
 101 &am43xx_pinmux {
 102         i2c0_pins_default: i2c0_pins_default {
 103                 pinctrl-single,pins = <
 104                         0x188 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
 105                         0x18c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
 106                 >;
 107         };
 108
 109         i2c0_pins_sleep: i2c0_pins_sleep {
 110                 pinctrl-single,pins = <
 111                         0x188 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 112                         0x18c (PIN_INPUT_PULLDOWN | MUX_MODE7)
 113                 >;
 114         };
 115
 116         i2c1_pins_default: i2c1_pins_default {
 117                 pinctrl-single,pins = <
 118                         0x15c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
 119                         0x158 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
 120                 >;
 121         };
 122
 123         i2c1_pins_sleep: i2c1_pins_sleep {
 124                 pinctrl-single,pins = <
 125                         0x15c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_cs0.i2c1_scl */
 126                         0x158 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d1.i2c1_sda */
 127                 >;
 128         };
 129
 130         mmc1_pins_default: pinmux_mmc1_pins_default {
 131                 pinctrl-single,pins = <
 132                         0x100 (PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */
 133                         0x104 (PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
 134                         0x1f0 (PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
 135                         0x1f4 (PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
 136                         0x1f8 (PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
 137                         0x1fc (PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
 138                         0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
 139                 >;
 140         };
 141
 142         mmc1_pins_sleep: pinmux_mmc1_pins_sleep {
 143                 pinctrl-single,pins = <
 144                         0x100 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 145                         0x104 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 146                         0x1f0 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 147                         0x1f4 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 148                         0x1f8 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 149                         0x1fc (PIN_INPUT_PULLDOWN | MUX_MODE7)
 150                         0x160 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 151                 >;
 152         };
 153
 154         ecap0_pins_default: backlight_pins_default {
 155                 pinctrl-single,pins = <
 156                         0x164 (PIN_OUTPUT | MUX_MODE0) /* ecap0_in_pwm0_out.ecap0_in_pwm0_out */
 157                 >;
 158         };
 159
 160         cpsw_default: cpsw_default {
 161                 pinctrl-single,pins = <
 162                         0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
 163                         0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
 164                         0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
 165                         0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
 166                         0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */
 167                         0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */
 168                         0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxclk.rmii1_rclk */
 169                         0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxdv.rgmii1_rctl */
 170                         0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd0.rgmii1_rd0 */
 171                         0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd1.rgmii1_rd1 */
 172                         0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd0.rgmii1_rd2 */
 173                         0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd1.rgmii1_rd3 */
 174                 >;
 175         };
 176
 177         cpsw_sleep: cpsw_sleep {
 178                 pinctrl-single,pins = <
 179                         0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
 180                         0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 181                         0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 182                         0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 183                         0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 184                         0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
 185                         0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 186                         0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 187                         0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 188                         0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
 189                         0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 190                         0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 191                 >;
 192         };
 193
 194         davinci_mdio_default: davinci_mdio_default {
 195                 pinctrl-single,pins = <
 196                         /* MDIO */
 197                         0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* mdio_data.mdio_data */
 198                         0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)                   /* mdio_clk.mdio_clk */
 199                 >;
 200         };
 201
 202         davinci_mdio_sleep: davinci_mdio_sleep {
 203                 pinctrl-single,pins = <
 204                         /* MDIO reset value */
 205                         0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 206                         0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
 207                 >;
 208         };
 209
 210         qspi_pins_default: qspi_pins_default {
 211                 pinctrl-single,pins = <
 212                         0x7c (PIN_OUTPUT_PULLUP | MUX_MODE3)    /* gpmc_csn0.qspi_csn */
 213                         0x88 (PIN_OUTPUT | MUX_MODE2)           /* gpmc_csn3.qspi_clk */
 214                         0x90 (PIN_INPUT_PULLUP | MUX_MODE3)     /* gpmc_advn_ale.qspi_d0 */
 215                         0x94 (PIN_INPUT_PULLUP | MUX_MODE3)     /* gpmc_oen_ren.qspi_d1 */
 216                         0x98 (PIN_INPUT_PULLUP | MUX_MODE3)     /* gpmc_wen.qspi_d2 */
 217                         0x9c (PIN_INPUT_PULLUP | MUX_MODE3)     /* gpmc_be0n_cle.qspi_d3 */
 218                 >;
 219         };
 220
 221         qspi_pins_sleep: qspi_pins_sleep{
 222                 pinctrl-single,pins = <
 223                         0x7c (PIN_INPUT_PULLDOWN | MUX_MODE7)
 224                         0x88 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 225                         0x90 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 226                         0x94 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 227                         0x98 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 228                         0x9c (PIN_INPUT_PULLDOWN | MUX_MODE7)
 229                 >;
 230         };
 231 };
 232
 233 &i2c0 {
 234         status = "okay";
 235         pinctrl-names = "default", "sleep";
 236         pinctrl-0 = <&i2c0_pins_default>;
 237         pinctrl-1 = <&i2c0_pins_default>;
 238         clock-frequency = <400000>;
 239
 240         at24@50 {
 241                 compatible = "at24,24c256";
 242                 pagesize = <64>;
 243                 reg = <0x50>;
 244         };
 245 };
 246
 247 &i2c1 {
 248         status = "okay";
 249         pinctrl-names = "default", "sleep";
 250         pinctrl-0 = <&i2c1_pins_default>;
 251         pinctrl-1 = <&i2c1_pins_default>;
 252         clock-frequency = <400000>;
 253
 254         tps: tps62362@60 {
 255                 compatible = "ti,tps62362";
 256                 regulator-name = "VDD_MPU";
 257                 regulator-min-microvolt = <950000>;
 258                 regulator-max-microvolt = <1330000>;
 259                 regulator-boot-on;
 260                 regulator-always-on;
 261                 ti,vsel0-state-high;
 262                 ti,vsel1-state-high;
 263                 vin-supply = <&v3_3d>;
 264         };
 265 };
 266
 267 &epwmss0 {
 268         status = "okay";
 269 };
 270
 271 &ecap0 {
 272         status = "okay";
 273         pinctrl-names = "default";
 274         pinctrl-0 = <&ecap0_pins_default>;
 275 };
 276
 277 &gpio0 {
 278         status = "okay";
 279 };
 280
 281 &gpio1 {
 282         status = "okay";
 283 };
 284
 285 &gpio5 {
 286         status = "okay";
 287 };
 288
 289 &mmc1 {
 290         status = "okay";
 291         pinctrl-names = "default", "sleep";
 292         pinctrl-0 = <&mmc1_pins_default>;
 293         pinctrl-1 = <&mmc1_pins_sleep>;
 294         vmmc-supply = <&v3_3d>;
 295         bus-width = <4>;
 296         cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
 297 };
 298
 299 &qspi {
 300         status = "okay";
 301         pinctrl-names = "default", "sleep";
 302         pinctrl-0 = <&qspi_pins_default>;
 303         pinctrl-1 = <&qspi_pins_sleep>;
 304
 305         spi-max-frequency = <48000000>;
 306         m25p80@0 {
 307                 compatible = "mx66l51235l";
 308                 spi-max-frequency = <48000000>;
 309                 reg = <0>;
 310                 spi-cpol;
 311                 spi-cpha;
 312                 spi-tx-bus-width = <1>;
 313                 spi-rx-bus-width = <4>;
 314                 #address-cells = <1>;
 315                 #size-cells = <1>;
 316
 317                 /*
 318                  * MTD partition table.  The ROM checks the first 512KiB for a
 319                  * valid file to boot(XIP).
 320                  */
 321                 partition@0 {
 322                         label = "QSPI.U_BOOT";
 323                         reg = <0x00000000 0x000080000>;
 324                 };
 325                 partition@1 {
 326                         label = "QSPI.U_BOOT.backup";
 327                         reg = <0x00080000 0x00080000>;
 328                 };
 329                 partition@2 {
 330                         label = "QSPI.U-BOOT-SPL_OS";
 331                         reg = <0x00100000 0x00010000>;
 332                 };
 333                 partition@3 {
 334                         label = "QSPI.U_BOOT_ENV";
 335                         reg = <0x00110000 0x00010000>;
 336                 };
 337                 partition@4 {
 338                         label = "QSPI.U-BOOT-ENV.backup";
 339                         reg = <0x00120000 0x00010000>;
 340                 };
 341                 partition@5 {
 342                         label = "QSPI.KERNEL";
 343                         reg = <0x00130000 0x0800000>;
 344                 };
 345                 partition@6 {
 346                         label = "QSPI.FILESYSTEM";
 347                         reg = <0x00930000 0x36D0000>;
 348                 };
 349         };
 350 };
 351
 352 &mac {
 353         pinctrl-names = "default", "sleep";
 354         pinctrl-0 = <&cpsw_default>;
 355         pinctrl-1 = <&cpsw_sleep>;
 356         status = "okay";
 357 };
 358
 359 &davinci_mdio {
 360         pinctrl-names = "default", "sleep";
 361         pinctrl-0 = <&davinci_mdio_default>;
 362         pinctrl-1 = <&davinci_mdio_sleep>;
 363         status = "okay";
 364 };
 365
 366 &cpsw_emac0 {
 367         phy_id = <&davinci_mdio>, <0>;
 368         phy-mode = "rgmii";
 369 };
 370
 371 &rtc {
 372         status = "okay";
 373 };
 374
 375 &wdt {
 376         status = "okay";
 377 };
 378
 379 &cpu {
 380         cpu0-supply = <&tps>;
 381 };