arch/arm/boot/dts/am33xx.dtsi

   1 /*
   2  * Device Tree Source for AM33XX SoC
   3  *
   4  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 /include/ "skeleton.dtsi"
  12
  13 / {
  14         compatible = "ti,am33xx";
  15
  16         aliases {
  17                 serial0 = &uart1;
  18                 serial1 = &uart2;
  19                 serial2 = &uart3;
  20                 serial3 = &uart4;
  21                 serial4 = &uart5;
  22                 serial5 = &uart6;
  23         };
  24
  25         cpus {
  26                 cpu@0 {
  27                         compatible = "arm,cortex-a8";
  28                 };
  29         };
  30
  31         /*
  32          * The soc node represents the soc top level view. It is uses for IPs
  33          * that are not memory mapped in the MPU view or for the MPU itself.
  34          */
  35         soc {
  36                 compatible = "ti,omap-infra";
  37                 mpu {
  38                         compatible = "ti,omap3-mpu";
  39                         ti,hwmods = "mpu";
  40                 };
  41         };
  42
  43         /*
  44          * XXX: Use a flat representation of the AM33XX interconnect.
  45          * The real AM33XX interconnect network is quite complex.Since
  46          * that will not bring real advantage to represent that in DT
  47          * for the moment, just use a fake OCP bus entry to represent
  48          * the whole bus hierarchy.
  49          */
  50         ocp {
  51                 compatible = "simple-bus";
  52                 #address-cells = <1>;
  53                 #size-cells = <1>;
  54                 ranges;
  55                 ti,hwmods = "l3_main";
  56
  57                 intc: interrupt-controller@48200000 {
  58                         compatible = "ti,omap2-intc";
  59                         interrupt-controller;
  60                         #interrupt-cells = <1>;
  61                         ti,intc-size = <128>;
  62                         reg = <0x48200000 0x1000>;
  63                 };
  64
  65                 gpio1: gpio@44e07000 {
  66                         compatible = "ti,omap4-gpio";
  67                         ti,hwmods = "gpio1";
  68                         gpio-controller;
  69                         #gpio-cells = <2>;
  70                         interrupt-controller;
  71                         #interrupt-cells = <1>;
  72                         reg = <0x44e07000 0x1000>;
  73                         interrupt-parent = <&intc>;
  74                         interrupts = <96>;
  75                 };
  76
  77                 gpio2: gpio@4804c000 {
  78                         compatible = "ti,omap4-gpio";
  79                         ti,hwmods = "gpio2";
  80                         gpio-controller;
  81                         #gpio-cells = <2>;
  82                         interrupt-controller;
  83                         #interrupt-cells = <1>;
  84                         reg = <0x4804c000 0x1000>;
  85                         interrupt-parent = <&intc>;
  86                         interrupts = <98>;
  87                 };
  88
  89                 gpio3: gpio@481ac000 {
  90                         compatible = "ti,omap4-gpio";
  91                         ti,hwmods = "gpio3";
  92                         gpio-controller;
  93                         #gpio-cells = <2>;
  94                         interrupt-controller;
  95                         #interrupt-cells = <1>;
  96                         reg = <0x481ac000 0x1000>;
  97                         interrupt-parent = <&intc>;
  98                         interrupts = <32>;
  99                 };
 100
 101                 gpio4: gpio@481ae000 {
 102                         compatible = "ti,omap4-gpio";
 103                         ti,hwmods = "gpio4";
 104                         gpio-controller;
 105                         #gpio-cells = <2>;
 106                         interrupt-controller;
 107                         #interrupt-cells = <1>;
 108                         reg = <0x481ae000 0x1000>;
 109                         interrupt-parent = <&intc>;
 110                         interrupts = <62>;
 111                 };
 112
 113                 uart1: serial@44e09000 {
 114                         compatible = "ti,omap3-uart";
 115                         ti,hwmods = "uart1";
 116                         clock-frequency = <48000000>;
 117                         reg = <0x44e09000 0x2000>;
 118                         interrupt-parent = <&intc>;
 119                         interrupts = <72>;
 120                         status = "disabled";
 121                 };
 122
 123                 uart2: serial@48022000 {
 124                         compatible = "ti,omap3-uart";
 125                         ti,hwmods = "uart2";
 126                         clock-frequency = <48000000>;
 127                         reg = <0x48022000 0x2000>;
 128                         interrupt-parent = <&intc>;
 129                         interrupts = <73>;
 130                         status = "disabled";
 131                 };
 132
 133                 uart3: serial@48024000 {
 134                         compatible = "ti,omap3-uart";
 135                         ti,hwmods = "uart3";
 136                         clock-frequency = <48000000>;
 137                         reg = <0x48024000 0x2000>;
 138                         interrupt-parent = <&intc>;
 139                         interrupts = <74>;
 140                         status = "disabled";
 141                 };
 142
 143                 uart4: serial@481a6000 {
 144                         compatible = "ti,omap3-uart";
 145                         ti,hwmods = "uart4";
 146                         clock-frequency = <48000000>;
 147                         reg = <0x481a6000 0x2000>;
 148                         interrupt-parent = <&intc>;
 149                         interrupts = <44>;
 150                         status = "disabled";
 151                 };
 152
 153                 uart5: serial@481a8000 {
 154                         compatible = "ti,omap3-uart";
 155                         ti,hwmods = "uart5";
 156                         clock-frequency = <48000000>;
 157                         reg = <0x481a8000 0x2000>;
 158                         interrupt-parent = <&intc>;
 159                         interrupts = <45>;
 160                         status = "disabled";
 161                 };
 162
 163                 uart6: serial@481aa000 {
 164                         compatible = "ti,omap3-uart";
 165                         ti,hwmods = "uart6";
 166                         clock-frequency = <48000000>;
 167                         reg = <0x481aa000 0x2000>;
 168                         interrupt-parent = <&intc>;
 169                         interrupts = <46>;
 170                         status = "disabled";
 171                 };
 172
 173                 i2c1: i2c@44e0b000 {
 174                         compatible = "ti,omap4-i2c";
 175                         #address-cells = <1>;
 176                         #size-cells = <0>;
 177                         ti,hwmods = "i2c1";
 178                         reg = <0x44e0b000 0x1000>;
 179                         interrupt-parent = <&intc>;
 180                         interrupts = <70>;
 181                         status = "disabled";
 182                 };
 183
 184                 i2c2: i2c@4802a000 {
 185                         compatible = "ti,omap4-i2c";
 186                         #address-cells = <1>;
 187                         #size-cells = <0>;
 188                         ti,hwmods = "i2c2";
 189                         reg = <0x4802a000 0x1000>;
 190                         interrupt-parent = <&intc>;
 191                         interrupts = <71>;
 192                         status = "disabled";
 193                 };
 194
 195                 i2c3: i2c@4819c000 {
 196                         compatible = "ti,omap4-i2c";
 197                         #address-cells = <1>;
 198                         #size-cells = <0>;
 199                         ti,hwmods = "i2c3";
 200                         reg = <0x4819c000 0x1000>;
 201                         interrupt-parent = <&intc>;
 202                         interrupts = <30>;
 203                         status = "disabled";
 204                 };
 205
 206                 wdt2: wdt@44e35000 {
 207                         compatible = "ti,omap3-wdt";
 208                         ti,hwmods = "wd_timer2";
 209                         reg = <0x44e35000 0x1000>;
 210                         interrupt-parent = <&intc>;
 211                         interrupts = <91>;
 212                 };
 213         };
 214 };