2 * linux/arch/arm/boot/compressed/head.S
4 * Copyright (C) 1996-2002 Russell King
5 * Copyright (C) 2004 Hyok S. Choi (MPU support)
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/linkage.h>
12 #include <asm/assembler.h>
18 * Note that these macros must not contain any code which is not
19 * 100% relocatable. Any attempt to do so will result in a crash.
20 * Please select one of the following when turning on debugging.
24 #if defined(CONFIG_DEBUG_ICEDCC)
26 #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
27 .macro loadsp, rb, tmp
30 mcr p14, 0, \ch, c0, c5, 0
32 #elif defined(CONFIG_CPU_XSCALE)
33 .macro loadsp, rb, tmp
36 mcr p14, 0, \ch, c8, c0, 0
39 .macro loadsp, rb, tmp
42 mcr p14, 0, \ch, c1, c0, 0
48 #include CONFIG_DEBUG_LL_INCLUDE
54 #if defined(CONFIG_ARCH_SA1100)
55 .macro loadsp, rb, tmp
56 mov \rb, #0x80000000 @ physical base address
57 #ifdef CONFIG_DEBUG_LL_SER3
58 add \rb, \rb, #0x00050000 @ Ser3
60 add \rb, \rb, #0x00010000 @ Ser1
64 .macro loadsp, rb, tmp
82 .macro debug_reloc_start
85 kphex r6, 8 /* processor id */
87 kphex r7, 8 /* architecture id */
88 #ifdef CONFIG_CPU_CP15
90 mrc p15, 0, r0, c1, c0
91 kphex r0, 8 /* control reg */
94 kphex r5, 8 /* decompressed kernel start */
96 kphex r9, 8 /* decompressed kernel end */
98 kphex r4, 8 /* kernel execution address */
103 .macro debug_reloc_end
105 kphex r5, 8 /* end of kernel */
108 bl memdump /* dump 256 bytes at start of kernel */
112 .section ".start", #alloc, #execinstr
114 * sort out different calling conventions
117 .arm @ Always enter in ARM state
119 .type start,#function
125 THUMB( adr r12, BSYM(1f) )
128 .word _magic_sig @ Magic numbers to help the loader
129 .word _magic_start @ absolute load/run zImage address
130 .word _magic_end @ zImage end address
131 .word 0x04030201 @ endianness flag
135 ARM_BE8( setend be ) @ go BE8 if compiled for BE8
137 #ifdef CONFIG_ARM_VIRT_EXT
138 bl __hyp_stub_install @ get into SVC mode, reversibly
140 mov r7, r1 @ save architecture ID
141 mov r8, r2 @ save atags pointer
144 * Booting from Angel - need to enter SVC mode and disable
145 * FIQs/IRQs (numeric definitions from angel arm.h source).
146 * We only do this if we were in user mode on entry.
148 mrs r2, cpsr @ get current mode
149 tst r2, #3 @ not user?
151 mov r0, #0x17 @ angel_SWIreason_EnterSVC
152 ARM( swi 0x123456 ) @ angel_SWI_ARM
153 THUMB( svc 0xab ) @ angel_SWI_THUMB
155 safe_svcmode_maskall r0
156 msr spsr_cxsf, r9 @ Save the CPU boot mode in
159 * Note that some cache flushing and other stuff may
160 * be needed here - is there an Angel SWI call for this?
164 * some architecture specific code can be inserted
165 * by the linker here, but it should preserve r7, r8, and r9.
170 #ifdef CONFIG_AUTO_ZRELADDR
171 @ determine final kernel image address
173 and r4, r4, #0xf8000000
174 add r4, r4, #TEXT_OFFSET
180 * Set up a page table only if it won't overwrite ourself.
181 * That means r4 < pc && r4 - 16k page directory > &_end.
182 * Given that r4 > &_end is most unfrequent, we add a rough
183 * additional 1MB of room for a possible appended DTB.
190 orrcc r4, r4, #1 @ remember we skipped cache_on
194 ldmia r0, {r1, r2, r3, r6, r10, r11, r12}
198 * We might be running at a different address. We need
199 * to fix up various pointers.
201 sub r0, r0, r1 @ calculate the delta offset
202 add r6, r6, r0 @ _edata
203 add r10, r10, r0 @ inflated kernel size location
206 * The kernel build system appends the size of the
207 * decompressed kernel at the end of the compressed data
208 * in little-endian form.
212 orr r9, r9, lr, lsl #8
215 orr r9, r9, lr, lsl #16
216 orr r9, r9, r10, lsl #24
218 #ifndef CONFIG_ZBOOT_ROM
219 /* malloc space is above the relocated stack (64k max) */
221 add r10, sp, #0x10000
224 * With ZBOOT_ROM the bss/stack is non relocatable,
225 * but someone could still run this code from RAM,
226 * in which case our reference is _edata.
231 mov r5, #0 @ init dtb size to 0
232 #ifdef CONFIG_ARM_APPENDED_DTB
237 * r4 = final kernel address (possibly with LSB set)
238 * r5 = appended dtb size (still unknown)
240 * r7 = architecture ID
241 * r8 = atags/device tree pointer
242 * r9 = size of decompressed image
243 * r10 = end of this image, including bss/stack/malloc space if non XIP
248 * if there are device trees (dtb) appended to zImage, advance r10 so that the
249 * dtb data will get relocated along with the kernel if necessary.
254 ldr r1, =0xedfe0dd0 @ sig is 0xd00dfeed big endian
259 bne dtb_check_done @ not found
261 #ifdef CONFIG_ARM_ATAG_DTB_COMPAT
263 * OK... Let's do some funky business here.
264 * If we do have a DTB appended to zImage, and we do have
265 * an ATAG list around, we want the later to be translated
266 * and folded into the former here. To be on the safe side,
267 * let's temporarily move the stack away into the malloc
268 * area. No GOT fixup has occurred yet, but none of the
269 * code we're about to call uses any global variable.
272 stmfd sp!, {r0-r3, ip, lr}
279 * If returned value is 1, there is no ATAG at the location
280 * pointed by r8. Try the typical 0x100 offset from start
281 * of RAM and hope for the best.
284 sub r0, r4, #TEXT_OFFSET
291 ldmfd sp!, {r0-r3, ip, lr}
295 mov r8, r6 @ use the appended device tree
298 * Make sure that the DTB doesn't end up in the final
299 * kernel's .bss area. To do so, we adjust the decompressed
300 * kernel size to compensate if that .bss size is larger
301 * than the relocated code.
303 ldr r5, =_kernel_bss_size
304 adr r1, wont_overwrite
309 /* Get the dtb's size */
312 /* convert r5 (dtb size) to little endian */
313 eor r1, r5, r5, ror #16
314 bic r1, r1, #0x00ff0000
316 eor r5, r5, r1, lsr #8
319 /* preserve 64-bit alignment */
323 /* relocate some pointers past the appended dtb */
331 * Check to see if we will overwrite ourselves.
332 * r4 = final kernel address (possibly with LSB set)
333 * r9 = size of decompressed image
334 * r10 = end of this image, including bss/stack/malloc space if non XIP
336 * r4 - 16k page directory >= r10 -> OK
337 * r4 + image length <= address of wont_overwrite -> OK
338 * Note: the possible LSB in r4 is harmless here.
344 adr r9, wont_overwrite
349 * Relocate ourselves past the end of the decompressed kernel.
351 * r10 = end of the decompressed kernel
352 * Because we always copy ahead, we need to do it from the end and go
353 * backward in case the source and destination overlap.
356 * Bump to the next 256-byte boundary with the size of
357 * the relocation code added. This avoids overwriting
358 * ourself when the offset is small.
360 add r10, r10, #((reloc_code_end - restart + 256) & ~255)
363 /* Get start of code we want to copy and align it down. */
367 /* Relocate the hyp vector base if necessary */
368 #ifdef CONFIG_ARM_VIRT_EXT
370 and r0, r0, #MODE_MASK
381 sub r9, r6, r5 @ size to copy
382 add r9, r9, #31 @ rounded up to a multiple
383 bic r9, r9, #31 @ ... of 32 bytes
387 1: ldmdb r6!, {r0 - r3, r10 - r12, lr}
389 stmdb r9!, {r0 - r3, r10 - r12, lr}
392 /* Preserve offset to relocated code. */
395 #ifndef CONFIG_ZBOOT_ROM
396 /* cache_clean_flush may use the stack, so relocate it */
401 bleq cache_clean_flush
403 adr r0, BSYM(restart)
409 * If delta is zero, we are running at the address we were linked at.
413 * r4 = kernel execution address (possibly with LSB set)
414 * r5 = appended dtb size (0 if not present)
415 * r7 = architecture ID
427 #ifndef CONFIG_ZBOOT_ROM
429 * If we're running fully PIC === CONFIG_ZBOOT_ROM = n,
430 * we need to fix up pointers into the BSS region.
431 * Note that the stack pointer has already been fixed up.
437 * Relocate all entries in the GOT table.
438 * Bump bss entries to _edata + dtb size
440 1: ldr r1, [r11, #0] @ relocate entries in the GOT
441 add r1, r1, r0 @ This fixes up C references
442 cmp r1, r2 @ if entry >= bss_start &&
443 cmphs r3, r1 @ bss_end > entry
444 addhi r1, r1, r5 @ entry += dtb size
445 str r1, [r11], #4 @ next entry
449 /* bump our bss pointers too */
456 * Relocate entries in the GOT table. We only relocate
457 * the entries that are outside the (relocated) BSS region.
459 1: ldr r1, [r11, #0] @ relocate entries in the GOT
460 cmp r1, r2 @ entry < bss_start ||
461 cmphs r3, r1 @ _end < entry
462 addlo r1, r1, r0 @ table. This fixes up the
463 str r1, [r11], #4 @ C references.
468 not_relocated: mov r0, #0
469 1: str r0, [r2], #4 @ clear bss
477 * Did we skip the cache setup earlier?
478 * That is indicated by the LSB in r4.
486 * The C runtime environment should now be setup sufficiently.
487 * Set up some pointers, and start decompressing.
488 * r4 = kernel execution address
489 * r7 = architecture ID
493 mov r1, sp @ malloc space above stack
494 add r2, sp, #0x10000 @ 64k max
499 mov r1, r7 @ restore architecture number
500 mov r2, r8 @ restore atags pointer
502 #ifdef CONFIG_ARM_VIRT_EXT
503 mrs r0, spsr @ Get saved CPU boot mode
504 and r0, r0, #MODE_MASK
505 cmp r0, #HYP_MODE @ if not booted in HYP mode...
506 bne __enter_kernel @ boot kernel directly
508 adr r12, .L__hyp_reentry_vectors_offset
513 __HVC(0) @ otherwise bounce to hyp mode
515 b . @ should never be reached
518 .L__hyp_reentry_vectors_offset: .long __hyp_reentry_vectors - .
526 .word __bss_start @ r2
529 .word input_data_end - 4 @ r10 (inflated size location)
530 .word _got_start @ r11
532 .word .L_user_stack_end @ sp
533 .word _end - restart + 16384 + 1024*1024
536 #ifdef CONFIG_ARCH_RPC
538 params: ldr r0, =0x10000100 @ params_phys for RPC
545 * Turn on the cache. We need to setup some page tables so that we
546 * can have both the I and D caches on.
548 * We place the page tables 16k down from the kernel execution address,
549 * and we hope that nothing else is using it. If we're using it, we
553 * r4 = kernel execution address
554 * r7 = architecture number
557 * r0, r1, r2, r3, r9, r10, r12 corrupted
558 * This routine must preserve:
562 cache_on: mov r3, #8 @ cache_on function
566 * Initialize the highest priority protection region, PR7
567 * to cover all 32bit address and cacheable and bufferable.
569 __armv4_mpu_cache_on:
570 mov r0, #0x3f @ 4G, the whole
571 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
572 mcr p15, 0, r0, c6, c7, 1
575 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
576 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
577 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
580 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
581 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
584 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
585 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
586 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
587 mrc p15, 0, r0, c1, c0, 0 @ read control reg
588 @ ...I .... ..D. WC.M
589 orr r0, r0, #0x002d @ .... .... ..1. 11.1
590 orr r0, r0, #0x1000 @ ...1 .... .... ....
592 mcr p15, 0, r0, c1, c0, 0 @ write control reg
595 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
596 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
599 __armv3_mpu_cache_on:
600 mov r0, #0x3f @ 4G, the whole
601 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
604 mcr p15, 0, r0, c2, c0, 0 @ cache on
605 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
608 mcr p15, 0, r0, c5, c0, 0 @ access permission
611 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
613 * ?? ARMv3 MMU does not allow reading the control register,
614 * does this really work on ARMv3 MPU?
616 mrc p15, 0, r0, c1, c0, 0 @ read control reg
617 @ .... .... .... WC.M
618 orr r0, r0, #0x000d @ .... .... .... 11.1
619 /* ?? this overwrites the value constructed above? */
621 mcr p15, 0, r0, c1, c0, 0 @ write control reg
623 /* ?? invalidate for the second time? */
624 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
627 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
633 __setup_mmu: sub r3, r4, #16384 @ Page directory size
634 bic r3, r3, #0xff @ Align the pointer
637 * Initialise the page tables, turning on the cacheable and bufferable
638 * bits for the RAM area only.
642 mov r9, r9, lsl #18 @ start of RAM
643 add r10, r9, #0x10000000 @ a reasonable RAM size
644 mov r1, #0x12 @ XN|U + section mapping
645 orr r1, r1, #3 << 10 @ AP=11
647 1: cmp r1, r9 @ if virt > start of RAM
648 cmphs r10, r1 @ && end of RAM > virt
649 bic r1, r1, #0x1c @ clear XN|U + C + B
650 orrlo r1, r1, #0x10 @ Set XN|U for non-RAM
651 orrhs r1, r1, r6 @ set RAM section settings
652 str r1, [r0], #4 @ 1:1 mapping
657 * If ever we are running from Flash, then we surely want the cache
658 * to be enabled also for our execution instance... We map 2MB of it
659 * so there is no map overlap problem for up to 1 MB compressed kernel.
660 * If the execution is in RAM then we would only be duplicating the above.
662 orr r1, r6, #0x04 @ ensure B is set for this
666 orr r1, r1, r2, lsl #20
667 add r0, r3, r2, lsl #2
674 @ Enable unaligned access on v6, to allow better code generation
675 @ for the decompressor C code:
676 __armv6_mmu_cache_on:
677 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
678 bic r0, r0, #2 @ A (no unaligned access fault)
679 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
680 mcr p15, 0, r0, c1, c0, 0 @ write SCTLR
681 b __armv4_mmu_cache_on
683 __arm926ejs_mmu_cache_on:
684 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
685 mov r0, #4 @ put dcache in WT mode
686 mcr p15, 7, r0, c15, c0, 0
689 __armv4_mmu_cache_on:
692 mov r6, #CB_BITS | 0x12 @ U
695 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
696 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
697 mrc p15, 0, r0, c1, c0, 0 @ read control reg
698 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
700 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
701 bl __common_mmu_cache_on
703 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
707 __armv7_mmu_cache_on:
710 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
712 movne r6, #CB_BITS | 0x02 @ !XN
715 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
717 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
719 mrc p15, 0, r0, c1, c0, 0 @ read control reg
720 bic r0, r0, #1 << 28 @ clear SCTLR.TRE
721 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
722 orr r0, r0, #0x003c @ write buffer
723 bic r0, r0, #2 @ A (no unaligned access fault)
724 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
725 @ (needed for ARM1176)
727 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
728 mrcne p15, 0, r6, c2, c0, 2 @ read ttb control reg
729 orrne r0, r0, #1 @ MMU enabled
730 movne r1, #0xfffffffd @ domain 0 = client
731 bic r6, r6, #1 << 31 @ 32-bit translation system
732 bic r6, r6, #3 << 0 @ use only ttbr0
733 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
734 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
735 mcrne p15, 0, r6, c2, c0, 2 @ load ttb control
737 mcr p15, 0, r0, c7, c5, 4 @ ISB
738 mcr p15, 0, r0, c1, c0, 0 @ load control register
739 mrc p15, 0, r0, c1, c0, 0 @ and read it back
741 mcr p15, 0, r0, c7, c5, 4 @ ISB
746 mov r6, #CB_BITS | 0x12 @ U
749 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
750 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
751 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
752 mrc p15, 0, r0, c1, c0, 0 @ read control reg
753 orr r0, r0, #0x1000 @ I-cache enable
754 bl __common_mmu_cache_on
756 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
759 __common_mmu_cache_on:
760 #ifndef CONFIG_THUMB2_KERNEL
762 orr r0, r0, #0x000d @ Write buffer, mmu
765 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
766 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
768 .align 5 @ cache line aligned
769 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
770 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
771 sub pc, lr, r0, lsr #32 @ properly flush pipeline
774 #define PROC_ENTRY_SIZE (4*5)
777 * Here follow the relocatable cache support functions for the
778 * various processors. This is a generic hook for locating an
779 * entry and jumping to an instruction at the specified offset
780 * from the start of the block. Please note this is all position
790 call_cache_fn: adr r12, proc_types
791 #ifdef CONFIG_CPU_CP15
792 mrc p15, 0, r9, c0, c0 @ get processor ID
794 ldr r9, =CONFIG_PROCESSOR_ID
796 1: ldr r1, [r12, #0] @ get value
797 ldr r2, [r12, #4] @ get mask
798 eor r1, r1, r9 @ (real ^ match)
800 ARM( addeq pc, r12, r3 ) @ call cache function
801 THUMB( addeq r12, r3 )
802 THUMB( moveq pc, r12 ) @ call cache function
803 add r12, r12, #PROC_ENTRY_SIZE
807 * Table for cache operations. This is basically:
810 * - 'cache on' method instruction
811 * - 'cache off' method instruction
812 * - 'cache flush' method instruction
814 * We match an entry using: ((real_id ^ match) & mask) == 0
816 * Writethrough caches generally only need 'on' and 'off'
817 * methods. Writeback caches _must_ have the flush method
821 .type proc_types,#object
823 .word 0x41000000 @ old ARM ID
832 .word 0x41007000 @ ARM7/710
841 .word 0x41807200 @ ARM720T (writethrough)
843 W(b) __armv4_mmu_cache_on
844 W(b) __armv4_mmu_cache_off
848 .word 0x41007400 @ ARM74x
850 W(b) __armv3_mpu_cache_on
851 W(b) __armv3_mpu_cache_off
852 W(b) __armv3_mpu_cache_flush
854 .word 0x41009400 @ ARM94x
856 W(b) __armv4_mpu_cache_on
857 W(b) __armv4_mpu_cache_off
858 W(b) __armv4_mpu_cache_flush
860 .word 0x41069260 @ ARM926EJ-S (v5TEJ)
862 W(b) __arm926ejs_mmu_cache_on
863 W(b) __armv4_mmu_cache_off
864 W(b) __armv5tej_mmu_cache_flush
866 .word 0x00007000 @ ARM7 IDs
875 @ Everything from here on will be the new ID system.
877 .word 0x4401a100 @ sa110 / sa1100
879 W(b) __armv4_mmu_cache_on
880 W(b) __armv4_mmu_cache_off
881 W(b) __armv4_mmu_cache_flush
883 .word 0x6901b110 @ sa1110
885 W(b) __armv4_mmu_cache_on
886 W(b) __armv4_mmu_cache_off
887 W(b) __armv4_mmu_cache_flush
890 .word 0xffffff00 @ PXA9xx
891 W(b) __armv4_mmu_cache_on
892 W(b) __armv4_mmu_cache_off
893 W(b) __armv4_mmu_cache_flush
895 .word 0x56158000 @ PXA168
897 W(b) __armv4_mmu_cache_on
898 W(b) __armv4_mmu_cache_off
899 W(b) __armv5tej_mmu_cache_flush
901 .word 0x56050000 @ Feroceon
903 W(b) __armv4_mmu_cache_on
904 W(b) __armv4_mmu_cache_off
905 W(b) __armv5tej_mmu_cache_flush
907 #ifdef CONFIG_CPU_FEROCEON_OLD_ID
908 /* this conflicts with the standard ARMv5TE entry */
909 .long 0x41009260 @ Old Feroceon
911 b __armv4_mmu_cache_on
912 b __armv4_mmu_cache_off
913 b __armv5tej_mmu_cache_flush
916 .word 0x66015261 @ FA526
918 W(b) __fa526_cache_on
919 W(b) __armv4_mmu_cache_off
920 W(b) __fa526_cache_flush
922 @ These match on the architecture ID
924 .word 0x00020000 @ ARMv4T
926 W(b) __armv4_mmu_cache_on
927 W(b) __armv4_mmu_cache_off
928 W(b) __armv4_mmu_cache_flush
930 .word 0x00050000 @ ARMv5TE
932 W(b) __armv4_mmu_cache_on
933 W(b) __armv4_mmu_cache_off
934 W(b) __armv4_mmu_cache_flush
936 .word 0x00060000 @ ARMv5TEJ
938 W(b) __armv4_mmu_cache_on
939 W(b) __armv4_mmu_cache_off
940 W(b) __armv5tej_mmu_cache_flush
942 .word 0x0007b000 @ ARMv6
944 W(b) __armv6_mmu_cache_on
945 W(b) __armv4_mmu_cache_off
946 W(b) __armv6_mmu_cache_flush
948 .word 0x000f0000 @ new CPU Id
950 W(b) __armv7_mmu_cache_on
951 W(b) __armv7_mmu_cache_off
952 W(b) __armv7_mmu_cache_flush
954 .word 0 @ unrecognised type
963 .size proc_types, . - proc_types
966 * If you get a "non-constant expression in ".if" statement"
967 * error from the assembler on this line, check that you have
968 * not accidentally written a "b" instruction where you should
971 .if (. - proc_types) % PROC_ENTRY_SIZE != 0
972 .error "The size of one or more proc_types entries is wrong."
976 * Turn off the Cache and MMU. ARMv3 does not support
977 * reading the control register, but ARMv4 does.
980 * r0, r1, r2, r3, r9, r12 corrupted
981 * This routine must preserve:
985 cache_off: mov r3, #12 @ cache_off function
988 __armv4_mpu_cache_off:
989 mrc p15, 0, r0, c1, c0
991 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
993 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
994 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
995 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
998 __armv3_mpu_cache_off:
999 mrc p15, 0, r0, c1, c0
1001 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
1003 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
1006 __armv4_mmu_cache_off:
1008 mrc p15, 0, r0, c1, c0
1010 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1012 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
1013 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
1017 __armv7_mmu_cache_off:
1018 mrc p15, 0, r0, c1, c0
1024 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1026 bl __armv7_mmu_cache_flush
1029 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
1031 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
1032 mcr p15, 0, r0, c7, c10, 4 @ DSB
1033 mcr p15, 0, r0, c7, c5, 4 @ ISB
1037 * Clean and flush the cache to maintain consistency.
1040 * r1, r2, r3, r9, r10, r11, r12 corrupted
1041 * This routine must preserve:
1049 __armv4_mpu_cache_flush:
1052 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
1053 mov r1, #7 << 5 @ 8 segments
1054 1: orr r3, r1, #63 << 26 @ 64 entries
1055 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
1056 subs r3, r3, #1 << 26
1057 bcs 2b @ entries 63 to 0
1058 subs r1, r1, #1 << 5
1059 bcs 1b @ segments 7 to 0
1062 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
1063 mcr p15, 0, ip, c7, c10, 4 @ drain WB
1066 __fa526_cache_flush:
1068 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
1069 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1070 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1073 __armv6_mmu_cache_flush:
1075 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
1076 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
1077 mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
1078 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1081 __armv7_mmu_cache_flush:
1082 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
1083 tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
1086 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
1089 mcr p15, 0, r10, c7, c10, 5 @ DMB
1090 stmfd sp!, {r0-r7, r9-r11}
1091 mrc p15, 1, r0, c0, c0, 1 @ read clidr
1092 ands r3, r0, #0x7000000 @ extract loc from clidr
1093 mov r3, r3, lsr #23 @ left align loc bit field
1094 beq finished @ if loc is 0, then no need to clean
1095 mov r10, #0 @ start clean at cache level 0
1097 add r2, r10, r10, lsr #1 @ work out 3x current cache level
1098 mov r1, r0, lsr r2 @ extract cache type bits from clidr
1099 and r1, r1, #7 @ mask of the bits for current cache only
1100 cmp r1, #2 @ see what cache we have at this level
1101 blt skip @ skip if no cache, or just i-cache
1102 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
1103 mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr
1104 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
1105 and r2, r1, #7 @ extract the length of the cache lines
1106 add r2, r2, #4 @ add 4 (line length offset)
1108 ands r4, r4, r1, lsr #3 @ find maximum number on the way size
1109 clz r5, r4 @ find bit position of way size increment
1111 ands r7, r7, r1, lsr #13 @ extract max number of the index size
1113 mov r9, r4 @ create working copy of max way size
1115 ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11
1116 ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11
1117 THUMB( lsl r6, r9, r5 )
1118 THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
1119 THUMB( lsl r6, r7, r2 )
1120 THUMB( orr r11, r11, r6 ) @ factor index number into r11
1121 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
1122 subs r9, r9, #1 @ decrement the way
1124 subs r7, r7, #1 @ decrement the index
1127 add r10, r10, #2 @ increment cache number
1131 ldmfd sp!, {r0-r7, r9-r11}
1132 mov r10, #0 @ swith back to cache level 0
1133 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
1135 mcr p15, 0, r10, c7, c10, 4 @ DSB
1136 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
1137 mcr p15, 0, r10, c7, c10, 4 @ DSB
1138 mcr p15, 0, r10, c7, c5, 4 @ ISB
1141 __armv5tej_mmu_cache_flush:
1142 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
1144 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
1145 mcr p15, 0, r0, c7, c10, 4 @ drain WB
1148 __armv4_mmu_cache_flush:
1149 mov r2, #64*1024 @ default: 32K dcache size (*2)
1150 mov r11, #32 @ default: 32 byte line size
1151 mrc p15, 0, r3, c0, c0, 1 @ read cache type
1152 teq r3, r9 @ cache ID register present?
1157 mov r2, r2, lsl r1 @ base dcache size *2
1158 tst r3, #1 << 14 @ test M bit
1159 addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1
1163 mov r11, r11, lsl r3 @ cache line size in bytes
1166 bic r1, r1, #63 @ align to longest cache line
1169 ARM( ldr r3, [r1], r11 ) @ s/w flush D cache
1170 THUMB( ldr r3, [r1] ) @ s/w flush D cache
1171 THUMB( add r1, r1, r11 )
1175 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1176 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
1177 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1180 __armv3_mmu_cache_flush:
1181 __armv3_mpu_cache_flush:
1183 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
1187 * Various debugging routines for printing hex characters and
1188 * memory, which again must be relocatable.
1192 .type phexbuf,#object
1194 .size phexbuf, . - phexbuf
1196 @ phex corrupts {r0, r1, r2, r3}
1197 phex: adr r3, phexbuf
1211 @ puts corrupts {r0, r1, r2, r3}
1213 1: ldrb r2, [r0], #1
1226 @ putc corrupts {r0, r1, r2, r3}
1233 @ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr}
1234 memdump: mov r12, r0
1237 2: mov r0, r11, lsl #2
1245 ldr r0, [r12, r11, lsl #2]
1265 #ifdef CONFIG_ARM_VIRT_EXT
1267 __hyp_reentry_vectors:
1273 W(b) __enter_kernel @ hyp
1276 #endif /* CONFIG_ARM_VIRT_EXT */
1279 mov r0, #0 @ must be 0
1280 ARM( mov pc, r4 ) @ call kernel
1281 THUMB( bx r4 ) @ entry point is always ARM
1286 .section ".stack", "aw", %nobits
1287 .L_user_stack: .space 4096