2 * linux/arch/arm/boot/compressed/head.S
4 * Copyright (C) 1996-2002 Russell King
5 * Copyright (C) 2004 Hyok S. Choi (MPU support)
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/linkage.h>
12 #include <asm/assembler.h>
18 * Note that these macros must not contain any code which is not
19 * 100% relocatable. Any attempt to do so will result in a crash.
20 * Please select one of the following when turning on debugging.
24 #if defined(CONFIG_DEBUG_ICEDCC)
26 #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
27 .macro loadsp, rb, tmp
30 mcr p14, 0, \ch, c0, c5, 0
32 #elif defined(CONFIG_CPU_XSCALE)
33 .macro loadsp, rb, tmp
36 mcr p14, 0, \ch, c8, c0, 0
39 .macro loadsp, rb, tmp
42 mcr p14, 0, \ch, c1, c0, 0
48 #include CONFIG_DEBUG_LL_INCLUDE
54 #if defined(CONFIG_ARCH_SA1100)
55 .macro loadsp, rb, tmp
56 mov \rb, #0x80000000 @ physical base address
57 #ifdef CONFIG_DEBUG_LL_SER3
58 add \rb, \rb, #0x00050000 @ Ser3
60 add \rb, \rb, #0x00010000 @ Ser1
64 .macro loadsp, rb, tmp
82 .macro debug_reloc_start
85 kphex r6, 8 /* processor id */
87 kphex r7, 8 /* architecture id */
88 #ifdef CONFIG_CPU_CP15
90 mrc p15, 0, r0, c1, c0
91 kphex r0, 8 /* control reg */
94 kphex r5, 8 /* decompressed kernel start */
96 kphex r9, 8 /* decompressed kernel end */
98 kphex r4, 8 /* kernel execution address */
103 .macro debug_reloc_end
105 kphex r5, 8 /* end of kernel */
108 bl memdump /* dump 256 bytes at start of kernel */
112 .section ".start", #alloc, #execinstr
114 * sort out different calling conventions
117 .arm @ Always enter in ARM state
119 .type start,#function
125 THUMB( adr r12, BSYM(1f) )
128 .word _magic_sig @ Magic numbers to help the loader
129 .word _magic_start @ absolute load/run zImage address
130 .word _magic_end @ zImage end address
131 .word 0x04030201 @ endianness flag
135 ARM_BE8( setend be ) @ go BE8 if compiled for BE8
137 #ifdef CONFIG_ARM_VIRT_EXT
138 bl __hyp_stub_install @ get into SVC mode, reversibly
140 mov r7, r1 @ save architecture ID
141 mov r8, r2 @ save atags pointer
144 * Booting from Angel - need to enter SVC mode and disable
145 * FIQs/IRQs (numeric definitions from angel arm.h source).
146 * We only do this if we were in user mode on entry.
148 mrs r2, cpsr @ get current mode
149 tst r2, #3 @ not user?
151 mov r0, #0x17 @ angel_SWIreason_EnterSVC
152 ARM( swi 0x123456 ) @ angel_SWI_ARM
153 THUMB( svc 0xab ) @ angel_SWI_THUMB
155 safe_svcmode_maskall r0
156 msr spsr_cxsf, r9 @ Save the CPU boot mode in
159 * Note that some cache flushing and other stuff may
160 * be needed here - is there an Angel SWI call for this?
164 * some architecture specific code can be inserted
165 * by the linker here, but it should preserve r7, r8, and r9.
170 #ifdef CONFIG_AUTO_ZRELADDR
171 @ determine final kernel image address
173 and r4, r4, #0xf8000000
174 add r4, r4, #TEXT_OFFSET
180 * Set up a page table only if it won't overwrite ourself.
181 * That means r4 < pc && r4 - 16k page directory > &_end.
182 * Given that r4 > &_end is most unfrequent, we add a rough
183 * additional 1MB of room for a possible appended DTB.
190 orrcc r4, r4, #1 @ remember we skipped cache_on
194 ldmia r0, {r1, r2, r3, r6, r10, r11, r12}
198 * We might be running at a different address. We need
199 * to fix up various pointers.
201 sub r0, r0, r1 @ calculate the delta offset
202 add r6, r6, r0 @ _edata
203 add r10, r10, r0 @ inflated kernel size location
206 * The kernel build system appends the size of the
207 * decompressed kernel at the end of the compressed data
208 * in little-endian form.
212 orr r9, r9, lr, lsl #8
215 orr r9, r9, lr, lsl #16
216 orr r9, r9, r10, lsl #24
218 #ifndef CONFIG_ZBOOT_ROM
219 /* malloc space is above the relocated stack (64k max) */
221 add r10, sp, #0x10000
224 * With ZBOOT_ROM the bss/stack is non relocatable,
225 * but someone could still run this code from RAM,
226 * in which case our reference is _edata.
231 mov r5, #0 @ init dtb size to 0
232 #ifdef CONFIG_ARM_APPENDED_DTB
237 * r4 = final kernel address (possibly with LSB set)
238 * r5 = appended dtb size (still unknown)
240 * r7 = architecture ID
241 * r8 = atags/device tree pointer
242 * r9 = size of decompressed image
243 * r10 = end of this image, including bss/stack/malloc space if non XIP
248 * if there are device trees (dtb) appended to zImage, advance r10 so that the
249 * dtb data will get relocated along with the kernel if necessary.
254 ldr r1, =0xedfe0dd0 @ sig is 0xd00dfeed big endian
259 bne dtb_check_done @ not found
261 #ifdef CONFIG_ARM_ATAG_DTB_COMPAT
263 * OK... Let's do some funky business here.
264 * If we do have a DTB appended to zImage, and we do have
265 * an ATAG list around, we want the later to be translated
266 * and folded into the former here. To be on the safe side,
267 * let's temporarily move the stack away into the malloc
268 * area. No GOT fixup has occurred yet, but none of the
269 * code we're about to call uses any global variable.
272 stmfd sp!, {r0-r3, ip, lr}
279 * If returned value is 1, there is no ATAG at the location
280 * pointed by r8. Try the typical 0x100 offset from start
281 * of RAM and hope for the best.
284 sub r0, r4, #TEXT_OFFSET
291 ldmfd sp!, {r0-r3, ip, lr}
295 mov r8, r6 @ use the appended device tree
298 * Make sure that the DTB doesn't end up in the final
299 * kernel's .bss area. To do so, we adjust the decompressed
300 * kernel size to compensate if that .bss size is larger
301 * than the relocated code.
303 ldr r5, =_kernel_bss_size
304 adr r1, wont_overwrite
309 /* Get the dtb's size */
312 /* convert r5 (dtb size) to little endian */
313 eor r1, r5, r5, ror #16
314 bic r1, r1, #0x00ff0000
316 eor r5, r5, r1, lsr #8
319 /* preserve 64-bit alignment */
323 /* relocate some pointers past the appended dtb */
331 * Check to see if we will overwrite ourselves.
332 * r4 = final kernel address (possibly with LSB set)
333 * r9 = size of decompressed image
334 * r10 = end of this image, including bss/stack/malloc space if non XIP
336 * r4 - 16k page directory >= r10 -> OK
337 * r4 + image length <= address of wont_overwrite -> OK
338 * Note: the possible LSB in r4 is harmless here.
344 adr r9, wont_overwrite
349 * Relocate ourselves past the end of the decompressed kernel.
351 * r10 = end of the decompressed kernel
352 * Because we always copy ahead, we need to do it from the end and go
353 * backward in case the source and destination overlap.
356 * Bump to the next 256-byte boundary with the size of
357 * the relocation code added. This avoids overwriting
358 * ourself when the offset is small.
360 add r10, r10, #((reloc_code_end - restart + 256) & ~255)
363 /* Get start of code we want to copy and align it down. */
367 /* Relocate the hyp vector base if necessary */
368 #ifdef CONFIG_ARM_VIRT_EXT
370 and r0, r0, #MODE_MASK
381 sub r9, r6, r5 @ size to copy
382 add r9, r9, #31 @ rounded up to a multiple
383 bic r9, r9, #31 @ ... of 32 bytes
387 1: ldmdb r6!, {r0 - r3, r10 - r12, lr}
389 stmdb r9!, {r0 - r3, r10 - r12, lr}
392 /* Preserve offset to relocated code. */
395 #ifndef CONFIG_ZBOOT_ROM
396 /* cache_clean_flush may use the stack, so relocate it */
402 adr r0, BSYM(restart)
408 * If delta is zero, we are running at the address we were linked at.
412 * r4 = kernel execution address (possibly with LSB set)
413 * r5 = appended dtb size (0 if not present)
414 * r7 = architecture ID
426 #ifndef CONFIG_ZBOOT_ROM
428 * If we're running fully PIC === CONFIG_ZBOOT_ROM = n,
429 * we need to fix up pointers into the BSS region.
430 * Note that the stack pointer has already been fixed up.
436 * Relocate all entries in the GOT table.
437 * Bump bss entries to _edata + dtb size
439 1: ldr r1, [r11, #0] @ relocate entries in the GOT
440 add r1, r1, r0 @ This fixes up C references
441 cmp r1, r2 @ if entry >= bss_start &&
442 cmphs r3, r1 @ bss_end > entry
443 addhi r1, r1, r5 @ entry += dtb size
444 str r1, [r11], #4 @ next entry
448 /* bump our bss pointers too */
455 * Relocate entries in the GOT table. We only relocate
456 * the entries that are outside the (relocated) BSS region.
458 1: ldr r1, [r11, #0] @ relocate entries in the GOT
459 cmp r1, r2 @ entry < bss_start ||
460 cmphs r3, r1 @ _end < entry
461 addlo r1, r1, r0 @ table. This fixes up the
462 str r1, [r11], #4 @ C references.
467 not_relocated: mov r0, #0
468 1: str r0, [r2], #4 @ clear bss
476 * Did we skip the cache setup earlier?
477 * That is indicated by the LSB in r4.
485 * The C runtime environment should now be setup sufficiently.
486 * Set up some pointers, and start decompressing.
487 * r4 = kernel execution address
488 * r7 = architecture ID
492 mov r1, sp @ malloc space above stack
493 add r2, sp, #0x10000 @ 64k max
498 mov r1, r7 @ restore architecture number
499 mov r2, r8 @ restore atags pointer
501 #ifdef CONFIG_ARM_VIRT_EXT
502 mrs r0, spsr @ Get saved CPU boot mode
503 and r0, r0, #MODE_MASK
504 cmp r0, #HYP_MODE @ if not booted in HYP mode...
505 bne __enter_kernel @ boot kernel directly
507 adr r12, .L__hyp_reentry_vectors_offset
512 __HVC(0) @ otherwise bounce to hyp mode
514 b . @ should never be reached
517 .L__hyp_reentry_vectors_offset: .long __hyp_reentry_vectors - .
525 .word __bss_start @ r2
528 .word input_data_end - 4 @ r10 (inflated size location)
529 .word _got_start @ r11
531 .word .L_user_stack_end @ sp
532 .word _end - restart + 16384 + 1024*1024
535 #ifdef CONFIG_ARCH_RPC
537 params: ldr r0, =0x10000100 @ params_phys for RPC
544 * Turn on the cache. We need to setup some page tables so that we
545 * can have both the I and D caches on.
547 * We place the page tables 16k down from the kernel execution address,
548 * and we hope that nothing else is using it. If we're using it, we
552 * r4 = kernel execution address
553 * r7 = architecture number
556 * r0, r1, r2, r3, r9, r10, r12 corrupted
557 * This routine must preserve:
561 cache_on: mov r3, #8 @ cache_on function
565 * Initialize the highest priority protection region, PR7
566 * to cover all 32bit address and cacheable and bufferable.
568 __armv4_mpu_cache_on:
569 mov r0, #0x3f @ 4G, the whole
570 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
571 mcr p15, 0, r0, c6, c7, 1
574 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
575 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
576 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
579 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
580 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
583 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
584 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
585 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
586 mrc p15, 0, r0, c1, c0, 0 @ read control reg
587 @ ...I .... ..D. WC.M
588 orr r0, r0, #0x002d @ .... .... ..1. 11.1
589 orr r0, r0, #0x1000 @ ...1 .... .... ....
591 mcr p15, 0, r0, c1, c0, 0 @ write control reg
594 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
595 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
598 __armv3_mpu_cache_on:
599 mov r0, #0x3f @ 4G, the whole
600 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
603 mcr p15, 0, r0, c2, c0, 0 @ cache on
604 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
607 mcr p15, 0, r0, c5, c0, 0 @ access permission
610 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
612 * ?? ARMv3 MMU does not allow reading the control register,
613 * does this really work on ARMv3 MPU?
615 mrc p15, 0, r0, c1, c0, 0 @ read control reg
616 @ .... .... .... WC.M
617 orr r0, r0, #0x000d @ .... .... .... 11.1
618 /* ?? this overwrites the value constructed above? */
620 mcr p15, 0, r0, c1, c0, 0 @ write control reg
622 /* ?? invalidate for the second time? */
623 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
626 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
632 __setup_mmu: sub r3, r4, #16384 @ Page directory size
633 bic r3, r3, #0xff @ Align the pointer
636 * Initialise the page tables, turning on the cacheable and bufferable
637 * bits for the RAM area only.
641 mov r9, r9, lsl #18 @ start of RAM
642 add r10, r9, #0x10000000 @ a reasonable RAM size
643 mov r1, #0x12 @ XN|U + section mapping
644 orr r1, r1, #3 << 10 @ AP=11
646 1: cmp r1, r9 @ if virt > start of RAM
647 cmphs r10, r1 @ && end of RAM > virt
648 bic r1, r1, #0x1c @ clear XN|U + C + B
649 orrlo r1, r1, #0x10 @ Set XN|U for non-RAM
650 orrhs r1, r1, r6 @ set RAM section settings
651 str r1, [r0], #4 @ 1:1 mapping
656 * If ever we are running from Flash, then we surely want the cache
657 * to be enabled also for our execution instance... We map 2MB of it
658 * so there is no map overlap problem for up to 1 MB compressed kernel.
659 * If the execution is in RAM then we would only be duplicating the above.
661 orr r1, r6, #0x04 @ ensure B is set for this
665 orr r1, r1, r2, lsl #20
666 add r0, r3, r2, lsl #2
673 @ Enable unaligned access on v6, to allow better code generation
674 @ for the decompressor C code:
675 __armv6_mmu_cache_on:
676 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
677 bic r0, r0, #2 @ A (no unaligned access fault)
678 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
679 mcr p15, 0, r0, c1, c0, 0 @ write SCTLR
680 b __armv4_mmu_cache_on
682 __arm926ejs_mmu_cache_on:
683 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
684 mov r0, #4 @ put dcache in WT mode
685 mcr p15, 7, r0, c15, c0, 0
688 __armv4_mmu_cache_on:
691 mov r6, #CB_BITS | 0x12 @ U
694 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
695 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
696 mrc p15, 0, r0, c1, c0, 0 @ read control reg
697 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
699 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
700 bl __common_mmu_cache_on
702 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
706 __armv7_mmu_cache_on:
709 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
711 movne r6, #CB_BITS | 0x02 @ !XN
714 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
716 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
718 mrc p15, 0, r0, c1, c0, 0 @ read control reg
719 bic r0, r0, #1 << 28 @ clear SCTLR.TRE
720 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
721 orr r0, r0, #0x003c @ write buffer
722 bic r0, r0, #2 @ A (no unaligned access fault)
723 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
724 @ (needed for ARM1176)
726 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
727 mrcne p15, 0, r6, c2, c0, 2 @ read ttb control reg
728 orrne r0, r0, #1 @ MMU enabled
729 movne r1, #0xfffffffd @ domain 0 = client
730 bic r6, r6, #1 << 31 @ 32-bit translation system
731 bic r6, r6, #3 << 0 @ use only ttbr0
732 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
733 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
734 mcrne p15, 0, r6, c2, c0, 2 @ load ttb control
736 mcr p15, 0, r0, c7, c5, 4 @ ISB
737 mcr p15, 0, r0, c1, c0, 0 @ load control register
738 mrc p15, 0, r0, c1, c0, 0 @ and read it back
740 mcr p15, 0, r0, c7, c5, 4 @ ISB
745 mov r6, #CB_BITS | 0x12 @ U
748 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
749 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
750 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
751 mrc p15, 0, r0, c1, c0, 0 @ read control reg
752 orr r0, r0, #0x1000 @ I-cache enable
753 bl __common_mmu_cache_on
755 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
758 __common_mmu_cache_on:
759 #ifndef CONFIG_THUMB2_KERNEL
761 orr r0, r0, #0x000d @ Write buffer, mmu
764 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
765 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
767 .align 5 @ cache line aligned
768 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
769 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
770 sub pc, lr, r0, lsr #32 @ properly flush pipeline
773 #define PROC_ENTRY_SIZE (4*5)
776 * Here follow the relocatable cache support functions for the
777 * various processors. This is a generic hook for locating an
778 * entry and jumping to an instruction at the specified offset
779 * from the start of the block. Please note this is all position
789 call_cache_fn: adr r12, proc_types
790 #ifdef CONFIG_CPU_CP15
791 mrc p15, 0, r9, c0, c0 @ get processor ID
793 ldr r9, =CONFIG_PROCESSOR_ID
795 1: ldr r1, [r12, #0] @ get value
796 ldr r2, [r12, #4] @ get mask
797 eor r1, r1, r9 @ (real ^ match)
799 ARM( addeq pc, r12, r3 ) @ call cache function
800 THUMB( addeq r12, r3 )
801 THUMB( moveq pc, r12 ) @ call cache function
802 add r12, r12, #PROC_ENTRY_SIZE
806 * Table for cache operations. This is basically:
809 * - 'cache on' method instruction
810 * - 'cache off' method instruction
811 * - 'cache flush' method instruction
813 * We match an entry using: ((real_id ^ match) & mask) == 0
815 * Writethrough caches generally only need 'on' and 'off'
816 * methods. Writeback caches _must_ have the flush method
820 .type proc_types,#object
822 .word 0x41000000 @ old ARM ID
831 .word 0x41007000 @ ARM7/710
840 .word 0x41807200 @ ARM720T (writethrough)
842 W(b) __armv4_mmu_cache_on
843 W(b) __armv4_mmu_cache_off
847 .word 0x41007400 @ ARM74x
849 W(b) __armv3_mpu_cache_on
850 W(b) __armv3_mpu_cache_off
851 W(b) __armv3_mpu_cache_flush
853 .word 0x41009400 @ ARM94x
855 W(b) __armv4_mpu_cache_on
856 W(b) __armv4_mpu_cache_off
857 W(b) __armv4_mpu_cache_flush
859 .word 0x41069260 @ ARM926EJ-S (v5TEJ)
861 W(b) __arm926ejs_mmu_cache_on
862 W(b) __armv4_mmu_cache_off
863 W(b) __armv5tej_mmu_cache_flush
865 .word 0x00007000 @ ARM7 IDs
874 @ Everything from here on will be the new ID system.
876 .word 0x4401a100 @ sa110 / sa1100
878 W(b) __armv4_mmu_cache_on
879 W(b) __armv4_mmu_cache_off
880 W(b) __armv4_mmu_cache_flush
882 .word 0x6901b110 @ sa1110
884 W(b) __armv4_mmu_cache_on
885 W(b) __armv4_mmu_cache_off
886 W(b) __armv4_mmu_cache_flush
889 .word 0xffffff00 @ PXA9xx
890 W(b) __armv4_mmu_cache_on
891 W(b) __armv4_mmu_cache_off
892 W(b) __armv4_mmu_cache_flush
894 .word 0x56158000 @ PXA168
896 W(b) __armv4_mmu_cache_on
897 W(b) __armv4_mmu_cache_off
898 W(b) __armv5tej_mmu_cache_flush
900 .word 0x56050000 @ Feroceon
902 W(b) __armv4_mmu_cache_on
903 W(b) __armv4_mmu_cache_off
904 W(b) __armv5tej_mmu_cache_flush
906 #ifdef CONFIG_CPU_FEROCEON_OLD_ID
907 /* this conflicts with the standard ARMv5TE entry */
908 .long 0x41009260 @ Old Feroceon
910 b __armv4_mmu_cache_on
911 b __armv4_mmu_cache_off
912 b __armv5tej_mmu_cache_flush
915 .word 0x66015261 @ FA526
917 W(b) __fa526_cache_on
918 W(b) __armv4_mmu_cache_off
919 W(b) __fa526_cache_flush
921 @ These match on the architecture ID
923 .word 0x00020000 @ ARMv4T
925 W(b) __armv4_mmu_cache_on
926 W(b) __armv4_mmu_cache_off
927 W(b) __armv4_mmu_cache_flush
929 .word 0x00050000 @ ARMv5TE
931 W(b) __armv4_mmu_cache_on
932 W(b) __armv4_mmu_cache_off
933 W(b) __armv4_mmu_cache_flush
935 .word 0x00060000 @ ARMv5TEJ
937 W(b) __armv4_mmu_cache_on
938 W(b) __armv4_mmu_cache_off
939 W(b) __armv5tej_mmu_cache_flush
941 .word 0x0007b000 @ ARMv6
943 W(b) __armv6_mmu_cache_on
944 W(b) __armv4_mmu_cache_off
945 W(b) __armv6_mmu_cache_flush
947 .word 0x000f0000 @ new CPU Id
949 W(b) __armv7_mmu_cache_on
950 W(b) __armv7_mmu_cache_off
951 W(b) __armv7_mmu_cache_flush
953 .word 0 @ unrecognised type
962 .size proc_types, . - proc_types
965 * If you get a "non-constant expression in ".if" statement"
966 * error from the assembler on this line, check that you have
967 * not accidentally written a "b" instruction where you should
970 .if (. - proc_types) % PROC_ENTRY_SIZE != 0
971 .error "The size of one or more proc_types entries is wrong."
975 * Turn off the Cache and MMU. ARMv3 does not support
976 * reading the control register, but ARMv4 does.
979 * r0, r1, r2, r3, r9, r12 corrupted
980 * This routine must preserve:
984 cache_off: mov r3, #12 @ cache_off function
987 __armv4_mpu_cache_off:
988 mrc p15, 0, r0, c1, c0
990 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
992 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
993 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
994 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
997 __armv3_mpu_cache_off:
998 mrc p15, 0, r0, c1, c0
1000 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
1002 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
1005 __armv4_mmu_cache_off:
1007 mrc p15, 0, r0, c1, c0
1009 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1011 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
1012 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
1016 __armv7_mmu_cache_off:
1017 mrc p15, 0, r0, c1, c0
1023 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1025 bl __armv7_mmu_cache_flush
1028 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
1030 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
1031 mcr p15, 0, r0, c7, c10, 4 @ DSB
1032 mcr p15, 0, r0, c7, c5, 4 @ ISB
1036 * Clean and flush the cache to maintain consistency.
1039 * r1, r2, r3, r9, r10, r11, r12 corrupted
1040 * This routine must preserve:
1048 __armv4_mpu_cache_flush:
1053 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
1054 mov r1, #7 << 5 @ 8 segments
1055 1: orr r3, r1, #63 << 26 @ 64 entries
1056 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
1057 subs r3, r3, #1 << 26
1058 bcs 2b @ entries 63 to 0
1059 subs r1, r1, #1 << 5
1060 bcs 1b @ segments 7 to 0
1063 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
1064 mcr p15, 0, ip, c7, c10, 4 @ drain WB
1067 __fa526_cache_flush:
1071 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
1072 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1073 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1076 __armv6_mmu_cache_flush:
1079 mcreq p15, 0, r1, c7, c14, 0 @ clean+invalidate D
1080 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
1081 mcreq p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
1082 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1085 __armv7_mmu_cache_flush:
1088 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
1089 tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
1092 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
1095 mcr p15, 0, r10, c7, c10, 5 @ DMB
1096 stmfd sp!, {r0-r7, r9-r11}
1097 mrc p15, 1, r0, c0, c0, 1 @ read clidr
1098 ands r3, r0, #0x7000000 @ extract loc from clidr
1099 mov r3, r3, lsr #23 @ left align loc bit field
1100 beq finished @ if loc is 0, then no need to clean
1101 mov r10, #0 @ start clean at cache level 0
1103 add r2, r10, r10, lsr #1 @ work out 3x current cache level
1104 mov r1, r0, lsr r2 @ extract cache type bits from clidr
1105 and r1, r1, #7 @ mask of the bits for current cache only
1106 cmp r1, #2 @ see what cache we have at this level
1107 blt skip @ skip if no cache, or just i-cache
1108 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
1109 mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr
1110 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
1111 and r2, r1, #7 @ extract the length of the cache lines
1112 add r2, r2, #4 @ add 4 (line length offset)
1114 ands r4, r4, r1, lsr #3 @ find maximum number on the way size
1115 clz r5, r4 @ find bit position of way size increment
1117 ands r7, r7, r1, lsr #13 @ extract max number of the index size
1119 mov r9, r4 @ create working copy of max way size
1121 ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11
1122 ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11
1123 THUMB( lsl r6, r9, r5 )
1124 THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
1125 THUMB( lsl r6, r7, r2 )
1126 THUMB( orr r11, r11, r6 ) @ factor index number into r11
1127 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
1128 subs r9, r9, #1 @ decrement the way
1130 subs r7, r7, #1 @ decrement the index
1133 add r10, r10, #2 @ increment cache number
1137 ldmfd sp!, {r0-r7, r9-r11}
1138 mov r10, #0 @ swith back to cache level 0
1139 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
1141 mcr p15, 0, r10, c7, c10, 4 @ DSB
1142 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
1143 mcr p15, 0, r10, c7, c10, 4 @ DSB
1144 mcr p15, 0, r10, c7, c5, 4 @ ISB
1147 __armv5tej_mmu_cache_flush:
1150 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
1152 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
1153 mcr p15, 0, r0, c7, c10, 4 @ drain WB
1156 __armv4_mmu_cache_flush:
1159 mov r2, #64*1024 @ default: 32K dcache size (*2)
1160 mov r11, #32 @ default: 32 byte line size
1161 mrc p15, 0, r3, c0, c0, 1 @ read cache type
1162 teq r3, r9 @ cache ID register present?
1167 mov r2, r2, lsl r1 @ base dcache size *2
1168 tst r3, #1 << 14 @ test M bit
1169 addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1
1173 mov r11, r11, lsl r3 @ cache line size in bytes
1176 bic r1, r1, #63 @ align to longest cache line
1179 ARM( ldr r3, [r1], r11 ) @ s/w flush D cache
1180 THUMB( ldr r3, [r1] ) @ s/w flush D cache
1181 THUMB( add r1, r1, r11 )
1185 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1186 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
1187 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1190 __armv3_mmu_cache_flush:
1191 __armv3_mpu_cache_flush:
1195 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
1199 * Various debugging routines for printing hex characters and
1200 * memory, which again must be relocatable.
1204 .type phexbuf,#object
1206 .size phexbuf, . - phexbuf
1208 @ phex corrupts {r0, r1, r2, r3}
1209 phex: adr r3, phexbuf
1223 @ puts corrupts {r0, r1, r2, r3}
1225 1: ldrb r2, [r0], #1
1238 @ putc corrupts {r0, r1, r2, r3}
1245 @ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr}
1246 memdump: mov r12, r0
1249 2: mov r0, r11, lsl #2
1257 ldr r0, [r12, r11, lsl #2]
1277 #ifdef CONFIG_ARM_VIRT_EXT
1279 __hyp_reentry_vectors:
1285 W(b) __enter_kernel @ hyp
1288 #endif /* CONFIG_ARM_VIRT_EXT */
1291 mov r0, #0 @ must be 0
1292 ARM( mov pc, r4 ) @ call kernel
1293 THUMB( bx r4 ) @ entry point is always ARM
1298 .section ".stack", "aw", %nobits
1299 .L_user_stack: .space 4096