5 select HAVE_DMA_API_DEBUG
6 select HAVE_IDE if PCI || ISA || PCMCIA
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if !XIP_KERNEL
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
32 select CPU_PM if (SUSPEND || CPU_IDLE)
34 The ARM series is a line of low-power-consumption RISC chip designs
35 licensed by ARM Ltd and targeted at embedded applications and
36 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
37 manufactured, but legacy ARM-based PC hardware remains popular in
38 Europe. There is an ARM Linux project with a web page at
39 <http://www.arm.linux.org.uk/>.
41 config ARM_HAS_SG_CHAIN
50 config SYS_SUPPORTS_APM_EMULATION
53 config HAVE_SCHED_CLOCK
59 config ARCH_USES_GETTIMEOFFSET
63 config GENERIC_CLOCKEVENTS
66 config GENERIC_CLOCKEVENTS_BROADCAST
68 depends on GENERIC_CLOCKEVENTS
77 select GENERIC_ALLOCATOR
88 The Extended Industry Standard Architecture (EISA) bus was
89 developed as an open alternative to the IBM MicroChannel bus.
91 The EISA bus provided some of the features of the IBM MicroChannel
92 bus while maintaining backward compatibility with cards made for
93 the older ISA bus. The EISA bus saw limited use between 1988 and
94 1995 when it was made obsolete by the PCI bus.
96 Say Y here if you are building a kernel for an EISA-based machine.
106 MicroChannel Architecture is found in some IBM PS/2 machines and
107 laptops. It is a bus system similar to PCI or ISA. See
108 <file:Documentation/mca.txt> (and especially the web page given
109 there) before attempting to build an MCA bus kernel.
111 config STACKTRACE_SUPPORT
115 config HAVE_LATENCYTOP_SUPPORT
120 config LOCKDEP_SUPPORT
124 config TRACE_IRQFLAGS_SUPPORT
128 config HARDIRQS_SW_RESEND
132 config GENERIC_IRQ_PROBE
136 config GENERIC_LOCKBREAK
139 depends on SMP && PREEMPT
141 config RWSEM_GENERIC_SPINLOCK
145 config RWSEM_XCHGADD_ALGORITHM
148 config ARCH_HAS_ILOG2_U32
151 config ARCH_HAS_ILOG2_U64
154 config ARCH_HAS_CPUFREQ
157 Internal node to signify that the ARCH has CPUFREQ support
158 and that the relevant menu configurations are displayed for
161 config ARCH_HAS_CPU_IDLE_WAIT
164 config GENERIC_HWEIGHT
168 config GENERIC_CALIBRATE_DELAY
172 config ARCH_MAY_HAVE_PC_FDC
178 config NEED_DMA_MAP_STATE
181 config GENERIC_ISA_DMA
192 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
193 default DRAM_BASE if REMAP_VECTORS_TO_RAM
196 The base address of exception vectors.
198 config ARM_PATCH_PHYS_VIRT
199 bool "Patch physical to virtual translations at runtime" if EMBEDDED
201 depends on !XIP_KERNEL && MMU
202 depends on !ARCH_REALVIEW || !SPARSEMEM
204 Patch phys-to-virt and virt-to-phys translation functions at
205 boot and module load time according to the position of the
206 kernel in system memory.
208 This can only be used with non-XIP MMU kernels where the base
209 of physical memory is at a 16MB boundary.
211 Only disable this option if you know that you do not require
212 this feature (eg, building a kernel for a single machine) and
213 you need to shrink the kernel to the minimal size.
215 config NEED_MACH_MEMORY_H
218 Select this when mach/memory.h is required to provide special
219 definitions for this platform. The need for mach/memory.h should
220 be avoided when possible.
223 hex "Physical address of main memory"
224 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
226 Please provide the physical address corresponding to the
227 location of main memory in your system.
233 source "init/Kconfig"
235 source "kernel/Kconfig.freezer"
240 bool "MMU-based Paged Memory Management Support"
243 Select if you want MMU-based virtualised addressing space
244 support by paged memory management. If unsure, say 'Y'.
247 # The "ARM system type" choice list is ordered alphabetically by option
248 # text. Please add new entries in the option alphabetic order.
251 prompt "ARM system type"
252 default ARCH_VERSATILE
254 config ARCH_INTEGRATOR
255 bool "ARM Ltd. Integrator family"
257 select ARCH_HAS_CPUFREQ
259 select HAVE_MACH_CLKDEV
261 select GENERIC_CLOCKEVENTS
262 select PLAT_VERSATILE
263 select PLAT_VERSATILE_FPGA_IRQ
264 select NEED_MACH_MEMORY_H
266 Support for ARM's Integrator platform.
269 bool "ARM Ltd. RealView family"
272 select HAVE_MACH_CLKDEV
274 select GENERIC_CLOCKEVENTS
275 select ARCH_WANT_OPTIONAL_GPIOLIB
276 select PLAT_VERSATILE
277 select PLAT_VERSATILE_CLCD
278 select ARM_TIMER_SP804
279 select GPIO_PL061 if GPIOLIB
280 select NEED_MACH_MEMORY_H
282 This enables support for ARM Ltd RealView boards.
284 config ARCH_VERSATILE
285 bool "ARM Ltd. Versatile family"
289 select HAVE_MACH_CLKDEV
291 select GENERIC_CLOCKEVENTS
292 select ARCH_WANT_OPTIONAL_GPIOLIB
293 select PLAT_VERSATILE
294 select PLAT_VERSATILE_CLCD
295 select PLAT_VERSATILE_FPGA_IRQ
296 select ARM_TIMER_SP804
298 This enables support for ARM Ltd Versatile board.
301 bool "ARM Ltd. Versatile Express family"
302 select ARCH_WANT_OPTIONAL_GPIOLIB
304 select ARM_TIMER_SP804
306 select HAVE_MACH_CLKDEV
307 select GENERIC_CLOCKEVENTS
309 select HAVE_PATA_PLATFORM
311 select PLAT_VERSATILE
312 select PLAT_VERSATILE_CLCD
314 This enables support for the ARM Ltd Versatile Express boards.
318 select ARCH_REQUIRE_GPIOLIB
322 This enables support for systems based on the Atmel AT91RM9200,
323 AT91SAM9 and AT91CAP9 processors.
326 bool "Broadcom BCMRING"
330 select ARM_TIMER_SP804
332 select GENERIC_CLOCKEVENTS
333 select ARCH_WANT_OPTIONAL_GPIOLIB
335 Support for Broadcom's BCMRing platform.
338 bool "Cirrus Logic CLPS711x/EP721x-based"
340 select ARCH_USES_GETTIMEOFFSET
341 select NEED_MACH_MEMORY_H
343 Support for Cirrus Logic 711x/721x based boards.
346 bool "Cavium Networks CNS3XXX family"
348 select GENERIC_CLOCKEVENTS
350 select MIGHT_HAVE_PCI
351 select PCI_DOMAINS if PCI
353 Support for Cavium Networks CNS3XXX platform.
356 bool "Cortina Systems Gemini"
358 select ARCH_REQUIRE_GPIOLIB
359 select ARCH_USES_GETTIMEOFFSET
361 Support for the Cortina Systems Gemini family SoCs
364 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
367 select GENERIC_CLOCKEVENTS
369 select GENERIC_IRQ_CHIP
373 Support for CSR SiRFSoC ARM Cortex A9 Platform
380 select ARCH_USES_GETTIMEOFFSET
381 select NEED_MACH_MEMORY_H
383 This is an evaluation board for the StrongARM processor available
384 from Digital. It has limited hardware on-board, including an
385 Ethernet interface, two PCMCIA sockets, two serial ports and a
394 select ARCH_REQUIRE_GPIOLIB
395 select ARCH_HAS_HOLES_MEMORYMODEL
396 select ARCH_USES_GETTIMEOFFSET
397 select NEED_MACH_MEMORY_H
399 This enables support for the Cirrus EP93xx series of CPUs.
401 config ARCH_FOOTBRIDGE
405 select GENERIC_CLOCKEVENTS
407 select NEED_MACH_MEMORY_H
409 Support for systems based on the DC21285 companion chip
410 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
413 bool "Freescale MXC/iMX-based"
414 select GENERIC_CLOCKEVENTS
415 select ARCH_REQUIRE_GPIOLIB
418 select GENERIC_IRQ_CHIP
419 select HAVE_SCHED_CLOCK
421 Support for Freescale MXC/iMX-based family of processors
424 bool "Freescale MXS-based"
425 select GENERIC_CLOCKEVENTS
426 select ARCH_REQUIRE_GPIOLIB
430 Support for Freescale MXS-based family of processors
433 bool "Hilscher NetX based"
437 select GENERIC_CLOCKEVENTS
439 This enables support for systems based on the Hilscher NetX Soc
442 bool "Hynix HMS720x-based"
445 select ARCH_USES_GETTIMEOFFSET
447 This enables support for systems based on the Hynix HMS720x
455 select ARCH_SUPPORTS_MSI
457 select NEED_MACH_MEMORY_H
459 Support for Intel's IOP13XX (XScale) family of processors.
467 select ARCH_REQUIRE_GPIOLIB
469 Support for Intel's 80219 and IOP32X (XScale) family of
478 select ARCH_REQUIRE_GPIOLIB
480 Support for Intel's IOP33X (XScale) family of processors.
487 select ARCH_USES_GETTIMEOFFSET
488 select NEED_MACH_MEMORY_H
490 Support for Intel's IXP23xx (XScale) family of processors.
493 bool "IXP2400/2800-based"
497 select ARCH_USES_GETTIMEOFFSET
498 select NEED_MACH_MEMORY_H
500 Support for Intel's IXP2400/2800 (XScale) family of processors.
508 select GENERIC_CLOCKEVENTS
509 select HAVE_SCHED_CLOCK
510 select MIGHT_HAVE_PCI
511 select DMABOUNCE if PCI
513 Support for Intel's IXP4XX (XScale) family of processors.
519 select ARCH_REQUIRE_GPIOLIB
520 select GENERIC_CLOCKEVENTS
523 Support for the Marvell Dove SoC 88AP510
526 bool "Marvell Kirkwood"
529 select ARCH_REQUIRE_GPIOLIB
530 select GENERIC_CLOCKEVENTS
533 Support for the following Marvell Kirkwood series SoCs:
534 88F6180, 88F6192 and 88F6281.
540 select ARCH_REQUIRE_GPIOLIB
543 select USB_ARCH_HAS_OHCI
545 select GENERIC_CLOCKEVENTS
547 Support for the NXP LPC32XX family of processors
550 bool "Marvell MV78xx0"
553 select ARCH_REQUIRE_GPIOLIB
554 select GENERIC_CLOCKEVENTS
557 Support for the following Marvell MV78xx0 series SoCs:
565 select ARCH_REQUIRE_GPIOLIB
566 select GENERIC_CLOCKEVENTS
569 Support for the following Marvell Orion 5x series SoCs:
570 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
571 Orion-2 (5281), Orion-1-90 (6183).
574 bool "Marvell PXA168/910/MMP2"
576 select ARCH_REQUIRE_GPIOLIB
578 select GENERIC_CLOCKEVENTS
579 select HAVE_SCHED_CLOCK
584 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
587 bool "Micrel/Kendin KS8695"
589 select ARCH_REQUIRE_GPIOLIB
590 select ARCH_USES_GETTIMEOFFSET
591 select NEED_MACH_MEMORY_H
593 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
594 System-on-Chip devices.
597 bool "Nuvoton W90X900 CPU"
599 select ARCH_REQUIRE_GPIOLIB
602 select GENERIC_CLOCKEVENTS
604 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
605 At present, the w90x900 has been renamed nuc900, regarding
606 the ARM series product line, you can login the following
607 link address to know more.
609 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
610 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
613 bool "Nuvoton NUC93X CPU"
617 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
618 low-power and high performance MPEG-4/JPEG multimedia controller chip.
624 select GENERIC_CLOCKEVENTS
627 select HAVE_SCHED_CLOCK
628 select ARCH_HAS_CPUFREQ
630 This enables support for NVIDIA Tegra based systems (Tegra APX,
631 Tegra 6xx and Tegra 2 series).
634 bool "Philips Nexperia PNX4008 Mobile"
637 select ARCH_USES_GETTIMEOFFSET
639 This enables support for Philips PNX4008 mobile platform.
642 bool "PXA2xx/PXA3xx-based"
645 select ARCH_HAS_CPUFREQ
648 select ARCH_REQUIRE_GPIOLIB
649 select GENERIC_CLOCKEVENTS
650 select HAVE_SCHED_CLOCK
655 select MULTI_IRQ_HANDLER
656 select ARM_CPU_SUSPEND if PM
659 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
664 select GENERIC_CLOCKEVENTS
665 select ARCH_REQUIRE_GPIOLIB
668 Support for Qualcomm MSM/QSD based systems. This runs on the
669 apps processor of the MSM/QSD and depends on a shared memory
670 interface to the modem processor which runs the baseband
671 stack and controls some vital subsystems
672 (clock and power control, etc).
675 bool "Renesas SH-Mobile / R-Mobile"
678 select HAVE_MACH_CLKDEV
679 select GENERIC_CLOCKEVENTS
682 select MULTI_IRQ_HANDLER
683 select PM_GENERIC_DOMAINS if PM
684 select NEED_MACH_MEMORY_H
686 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
693 select ARCH_MAY_HAVE_PC_FDC
694 select HAVE_PATA_PLATFORM
697 select ARCH_SPARSEMEM_ENABLE
698 select ARCH_USES_GETTIMEOFFSET
700 select NEED_MACH_MEMORY_H
702 On the Acorn Risc-PC, Linux can support the internal IDE disk and
703 CD-ROM interface, serial and parallel port, and the floppy drive.
710 select ARCH_SPARSEMEM_ENABLE
712 select ARCH_HAS_CPUFREQ
714 select GENERIC_CLOCKEVENTS
716 select HAVE_SCHED_CLOCK
718 select ARCH_REQUIRE_GPIOLIB
720 select NEED_MACH_MEMORY_H
722 Support for StrongARM 11x0 based boards.
725 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
727 select ARCH_HAS_CPUFREQ
730 select ARCH_USES_GETTIMEOFFSET
731 select HAVE_S3C2410_I2C if I2C
733 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
734 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
735 the Samsung SMDK2410 development board (and derivatives).
737 Note, the S3C2416 and the S3C2450 are so close that they even share
738 the same SoC ID code. This means that there is no separate machine
739 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
742 bool "Samsung S3C64XX"
749 select ARCH_USES_GETTIMEOFFSET
750 select ARCH_HAS_CPUFREQ
751 select ARCH_REQUIRE_GPIOLIB
752 select SAMSUNG_CLKSRC
753 select SAMSUNG_IRQ_VIC_TIMER
754 select S3C_GPIO_TRACK
755 select S3C_GPIO_PULL_UPDOWN
756 select S3C_GPIO_CFG_S3C24XX
757 select S3C_GPIO_CFG_S3C64XX
759 select USB_ARCH_HAS_OHCI
760 select SAMSUNG_GPIOLIB_4BIT
761 select HAVE_S3C2410_I2C if I2C
762 select HAVE_S3C2410_WATCHDOG if WATCHDOG
764 Samsung S3C64XX series based systems
767 bool "Samsung S5P6440 S5P6450"
773 select HAVE_S3C2410_WATCHDOG if WATCHDOG
774 select GENERIC_CLOCKEVENTS
775 select HAVE_SCHED_CLOCK
776 select HAVE_S3C2410_I2C if I2C
777 select HAVE_S3C_RTC if RTC_CLASS
779 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
783 bool "Samsung S5PC100"
788 select ARM_L1_CACHE_SHIFT_6
789 select ARCH_USES_GETTIMEOFFSET
790 select HAVE_S3C2410_I2C if I2C
791 select HAVE_S3C_RTC if RTC_CLASS
792 select HAVE_S3C2410_WATCHDOG if WATCHDOG
794 Samsung S5PC100 series based systems
797 bool "Samsung S5PV210/S5PC110"
799 select ARCH_SPARSEMEM_ENABLE
800 select ARCH_HAS_HOLES_MEMORYMODEL
805 select ARM_L1_CACHE_SHIFT_6
806 select ARCH_HAS_CPUFREQ
807 select GENERIC_CLOCKEVENTS
808 select HAVE_SCHED_CLOCK
809 select HAVE_S3C2410_I2C if I2C
810 select HAVE_S3C_RTC if RTC_CLASS
811 select HAVE_S3C2410_WATCHDOG if WATCHDOG
812 select NEED_MACH_MEMORY_H
814 Samsung S5PV210/S5PC110 series based systems
817 bool "Samsung EXYNOS4"
819 select ARCH_SPARSEMEM_ENABLE
820 select ARCH_HAS_HOLES_MEMORYMODEL
824 select ARCH_HAS_CPUFREQ
825 select GENERIC_CLOCKEVENTS
826 select HAVE_S3C_RTC if RTC_CLASS
827 select HAVE_S3C2410_I2C if I2C
828 select HAVE_S3C2410_WATCHDOG if WATCHDOG
829 select NEED_MACH_MEMORY_H
831 Samsung EXYNOS4 series based systems
840 select ARCH_USES_GETTIMEOFFSET
841 select NEED_MACH_MEMORY_H
843 Support for the StrongARM based Digital DNARD machine, also known
844 as "Shark" (<http://www.shark-linux.de/shark.html>).
847 bool "Telechips TCC ARM926-based systems"
852 select GENERIC_CLOCKEVENTS
854 Support for Telechips TCC ARM926-based systems.
857 bool "ST-Ericsson U300 Series"
861 select HAVE_SCHED_CLOCK
864 select ARM_PATCH_PHYS_VIRT
866 select GENERIC_CLOCKEVENTS
868 select HAVE_MACH_CLKDEV
870 select ARCH_REQUIRE_GPIOLIB
871 select NEED_MACH_MEMORY_H
873 Support for ST-Ericsson U300 series mobile platforms.
876 bool "ST-Ericsson U8500 Series"
879 select GENERIC_CLOCKEVENTS
881 select ARCH_REQUIRE_GPIOLIB
882 select ARCH_HAS_CPUFREQ
884 Support for ST-Ericsson's Ux500 architecture
887 bool "STMicroelectronics Nomadik"
892 select GENERIC_CLOCKEVENTS
893 select ARCH_REQUIRE_GPIOLIB
895 Support for the Nomadik platform by ST-Ericsson
899 select GENERIC_CLOCKEVENTS
900 select ARCH_REQUIRE_GPIOLIB
904 select GENERIC_ALLOCATOR
905 select GENERIC_IRQ_CHIP
906 select ARCH_HAS_HOLES_MEMORYMODEL
908 Support for TI's DaVinci platform.
913 select ARCH_REQUIRE_GPIOLIB
914 select ARCH_HAS_CPUFREQ
916 select GENERIC_CLOCKEVENTS
917 select HAVE_SCHED_CLOCK
918 select ARCH_HAS_HOLES_MEMORYMODEL
920 Support for TI's OMAP platform (OMAP1/2/3/4).
925 select ARCH_REQUIRE_GPIOLIB
928 select GENERIC_CLOCKEVENTS
931 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
934 bool "VIA/WonderMedia 85xx"
937 select ARCH_HAS_CPUFREQ
938 select GENERIC_CLOCKEVENTS
939 select ARCH_REQUIRE_GPIOLIB
942 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
945 bool "Xilinx Zynq ARM Cortex A9 Platform"
947 select GENERIC_CLOCKEVENTS
954 Support for Xilinx Zynq ARM Cortex A9 Platform
958 # This is sorted alphabetically by mach-* pathname. However, plat-*
959 # Kconfigs may be included either alphabetically (according to the
960 # plat- suffix) or along side the corresponding mach-* source.
962 source "arch/arm/mach-at91/Kconfig"
964 source "arch/arm/mach-bcmring/Kconfig"
966 source "arch/arm/mach-clps711x/Kconfig"
968 source "arch/arm/mach-cns3xxx/Kconfig"
970 source "arch/arm/mach-davinci/Kconfig"
972 source "arch/arm/mach-dove/Kconfig"
974 source "arch/arm/mach-ep93xx/Kconfig"
976 source "arch/arm/mach-footbridge/Kconfig"
978 source "arch/arm/mach-gemini/Kconfig"
980 source "arch/arm/mach-h720x/Kconfig"
982 source "arch/arm/mach-integrator/Kconfig"
984 source "arch/arm/mach-iop32x/Kconfig"
986 source "arch/arm/mach-iop33x/Kconfig"
988 source "arch/arm/mach-iop13xx/Kconfig"
990 source "arch/arm/mach-ixp4xx/Kconfig"
992 source "arch/arm/mach-ixp2000/Kconfig"
994 source "arch/arm/mach-ixp23xx/Kconfig"
996 source "arch/arm/mach-kirkwood/Kconfig"
998 source "arch/arm/mach-ks8695/Kconfig"
1000 source "arch/arm/mach-lpc32xx/Kconfig"
1002 source "arch/arm/mach-msm/Kconfig"
1004 source "arch/arm/mach-mv78xx0/Kconfig"
1006 source "arch/arm/plat-mxc/Kconfig"
1008 source "arch/arm/mach-mxs/Kconfig"
1010 source "arch/arm/mach-netx/Kconfig"
1012 source "arch/arm/mach-nomadik/Kconfig"
1013 source "arch/arm/plat-nomadik/Kconfig"
1015 source "arch/arm/mach-nuc93x/Kconfig"
1017 source "arch/arm/plat-omap/Kconfig"
1019 source "arch/arm/mach-omap1/Kconfig"
1021 source "arch/arm/mach-omap2/Kconfig"
1023 source "arch/arm/mach-orion5x/Kconfig"
1025 source "arch/arm/mach-pxa/Kconfig"
1026 source "arch/arm/plat-pxa/Kconfig"
1028 source "arch/arm/mach-mmp/Kconfig"
1030 source "arch/arm/mach-realview/Kconfig"
1032 source "arch/arm/mach-sa1100/Kconfig"
1034 source "arch/arm/plat-samsung/Kconfig"
1035 source "arch/arm/plat-s3c24xx/Kconfig"
1036 source "arch/arm/plat-s5p/Kconfig"
1038 source "arch/arm/plat-spear/Kconfig"
1040 source "arch/arm/plat-tcc/Kconfig"
1043 source "arch/arm/mach-s3c2410/Kconfig"
1044 source "arch/arm/mach-s3c2412/Kconfig"
1045 source "arch/arm/mach-s3c2416/Kconfig"
1046 source "arch/arm/mach-s3c2440/Kconfig"
1047 source "arch/arm/mach-s3c2443/Kconfig"
1051 source "arch/arm/mach-s3c64xx/Kconfig"
1054 source "arch/arm/mach-s5p64x0/Kconfig"
1056 source "arch/arm/mach-s5pc100/Kconfig"
1058 source "arch/arm/mach-s5pv210/Kconfig"
1060 source "arch/arm/mach-exynos4/Kconfig"
1062 source "arch/arm/mach-shmobile/Kconfig"
1064 source "arch/arm/mach-tegra/Kconfig"
1066 source "arch/arm/mach-u300/Kconfig"
1068 source "arch/arm/mach-ux500/Kconfig"
1070 source "arch/arm/mach-versatile/Kconfig"
1072 source "arch/arm/mach-vexpress/Kconfig"
1073 source "arch/arm/plat-versatile/Kconfig"
1075 source "arch/arm/mach-vt8500/Kconfig"
1077 source "arch/arm/mach-w90x900/Kconfig"
1079 # Definitions to make life easier
1085 select GENERIC_CLOCKEVENTS
1086 select HAVE_SCHED_CLOCK
1091 select GENERIC_IRQ_CHIP
1092 select HAVE_SCHED_CLOCK
1097 config PLAT_VERSATILE
1100 config ARM_TIMER_SP804
1104 source arch/arm/mm/Kconfig
1107 bool "Enable iWMMXt support"
1108 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1109 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1111 Enable support for iWMMXt context switching at run time if
1112 running on a CPU that supports it.
1114 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1117 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1121 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1122 (!ARCH_OMAP3 || OMAP3_EMU)
1126 config MULTI_IRQ_HANDLER
1129 Allow each machine to specify it's own IRQ handler at run time.
1132 source "arch/arm/Kconfig-nommu"
1135 config ARM_ERRATA_411920
1136 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1137 depends on CPU_V6 || CPU_V6K
1139 Invalidation of the Instruction Cache operation can
1140 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1141 It does not affect the MPCore. This option enables the ARM Ltd.
1142 recommended workaround.
1144 config ARM_ERRATA_430973
1145 bool "ARM errata: Stale prediction on replaced interworking branch"
1148 This option enables the workaround for the 430973 Cortex-A8
1149 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1150 interworking branch is replaced with another code sequence at the
1151 same virtual address, whether due to self-modifying code or virtual
1152 to physical address re-mapping, Cortex-A8 does not recover from the
1153 stale interworking branch prediction. This results in Cortex-A8
1154 executing the new code sequence in the incorrect ARM or Thumb state.
1155 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1156 and also flushes the branch target cache at every context switch.
1157 Note that setting specific bits in the ACTLR register may not be
1158 available in non-secure mode.
1160 config ARM_ERRATA_458693
1161 bool "ARM errata: Processor deadlock when a false hazard is created"
1164 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1165 erratum. For very specific sequences of memory operations, it is
1166 possible for a hazard condition intended for a cache line to instead
1167 be incorrectly associated with a different cache line. This false
1168 hazard might then cause a processor deadlock. The workaround enables
1169 the L1 caching of the NEON accesses and disables the PLD instruction
1170 in the ACTLR register. Note that setting specific bits in the ACTLR
1171 register may not be available in non-secure mode.
1173 config ARM_ERRATA_460075
1174 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1177 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1178 erratum. Any asynchronous access to the L2 cache may encounter a
1179 situation in which recent store transactions to the L2 cache are lost
1180 and overwritten with stale memory contents from external memory. The
1181 workaround disables the write-allocate mode for the L2 cache via the
1182 ACTLR register. Note that setting specific bits in the ACTLR register
1183 may not be available in non-secure mode.
1185 config ARM_ERRATA_742230
1186 bool "ARM errata: DMB operation may be faulty"
1187 depends on CPU_V7 && SMP
1189 This option enables the workaround for the 742230 Cortex-A9
1190 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1191 between two write operations may not ensure the correct visibility
1192 ordering of the two writes. This workaround sets a specific bit in
1193 the diagnostic register of the Cortex-A9 which causes the DMB
1194 instruction to behave as a DSB, ensuring the correct behaviour of
1197 config ARM_ERRATA_742231
1198 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1199 depends on CPU_V7 && SMP
1201 This option enables the workaround for the 742231 Cortex-A9
1202 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1203 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1204 accessing some data located in the same cache line, may get corrupted
1205 data due to bad handling of the address hazard when the line gets
1206 replaced from one of the CPUs at the same time as another CPU is
1207 accessing it. This workaround sets specific bits in the diagnostic
1208 register of the Cortex-A9 which reduces the linefill issuing
1209 capabilities of the processor.
1211 config PL310_ERRATA_588369
1212 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1213 depends on CACHE_L2X0
1215 The PL310 L2 cache controller implements three types of Clean &
1216 Invalidate maintenance operations: by Physical Address
1217 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1218 They are architecturally defined to behave as the execution of a
1219 clean operation followed immediately by an invalidate operation,
1220 both performing to the same memory location. This functionality
1221 is not correctly implemented in PL310 as clean lines are not
1222 invalidated as a result of these operations.
1224 config ARM_ERRATA_720789
1225 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1226 depends on CPU_V7 && SMP
1228 This option enables the workaround for the 720789 Cortex-A9 (prior to
1229 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1230 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1231 As a consequence of this erratum, some TLB entries which should be
1232 invalidated are not, resulting in an incoherency in the system page
1233 tables. The workaround changes the TLB flushing routines to invalidate
1234 entries regardless of the ASID.
1236 config PL310_ERRATA_727915
1237 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1238 depends on CACHE_L2X0
1240 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1241 operation (offset 0x7FC). This operation runs in background so that
1242 PL310 can handle normal accesses while it is in progress. Under very
1243 rare circumstances, due to this erratum, write data can be lost when
1244 PL310 treats a cacheable write transaction during a Clean &
1245 Invalidate by Way operation.
1247 config ARM_ERRATA_743622
1248 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1251 This option enables the workaround for the 743622 Cortex-A9
1252 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1253 optimisation in the Cortex-A9 Store Buffer may lead to data
1254 corruption. This workaround sets a specific bit in the diagnostic
1255 register of the Cortex-A9 which disables the Store Buffer
1256 optimisation, preventing the defect from occurring. This has no
1257 visible impact on the overall performance or power consumption of the
1260 config ARM_ERRATA_751472
1261 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1262 depends on CPU_V7 && SMP
1264 This option enables the workaround for the 751472 Cortex-A9 (prior
1265 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1266 completion of a following broadcasted operation if the second
1267 operation is received by a CPU before the ICIALLUIS has completed,
1268 potentially leading to corrupted entries in the cache or TLB.
1270 config ARM_ERRATA_753970
1271 bool "ARM errata: cache sync operation may be faulty"
1272 depends on CACHE_PL310
1274 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1276 Under some condition the effect of cache sync operation on
1277 the store buffer still remains when the operation completes.
1278 This means that the store buffer is always asked to drain and
1279 this prevents it from merging any further writes. The workaround
1280 is to replace the normal offset of cache sync operation (0x730)
1281 by another offset targeting an unmapped PL310 register 0x740.
1282 This has the same effect as the cache sync operation: store buffer
1283 drain and waiting for all buffers empty.
1285 config ARM_ERRATA_754322
1286 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1289 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1290 r3p*) erratum. A speculative memory access may cause a page table walk
1291 which starts prior to an ASID switch but completes afterwards. This
1292 can populate the micro-TLB with a stale entry which may be hit with
1293 the new ASID. This workaround places two dsb instructions in the mm
1294 switching code so that no page table walks can cross the ASID switch.
1296 config ARM_ERRATA_754327
1297 bool "ARM errata: no automatic Store Buffer drain"
1298 depends on CPU_V7 && SMP
1300 This option enables the workaround for the 754327 Cortex-A9 (prior to
1301 r2p0) erratum. The Store Buffer does not have any automatic draining
1302 mechanism and therefore a livelock may occur if an external agent
1303 continuously polls a memory location waiting to observe an update.
1304 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1305 written polling loops from denying visibility of updates to memory.
1307 config ARM_ERRATA_364296
1308 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1309 depends on CPU_V6 && !SMP
1311 This options enables the workaround for the 364296 ARM1136
1312 r0p2 erratum (possible cache data corruption with
1313 hit-under-miss enabled). It sets the undocumented bit 31 in
1314 the auxiliary control register and the FI bit in the control
1315 register, thus disabling hit-under-miss without putting the
1316 processor into full low interrupt latency mode. ARM11MPCore
1319 config ARM_ERRATA_764369
1320 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1321 depends on CPU_V7 && SMP
1323 This option enables the workaround for erratum 764369
1324 affecting Cortex-A9 MPCore with two or more processors (all
1325 current revisions). Under certain timing circumstances, a data
1326 cache line maintenance operation by MVA targeting an Inner
1327 Shareable memory region may fail to proceed up to either the
1328 Point of Coherency or to the Point of Unification of the
1329 system. This workaround adds a DSB instruction before the
1330 relevant cache maintenance functions and sets a specific bit
1331 in the diagnostic control register of the SCU.
1335 source "arch/arm/common/Kconfig"
1345 Find out whether you have ISA slots on your motherboard. ISA is the
1346 name of a bus system, i.e. the way the CPU talks to the other stuff
1347 inside your box. Other bus systems are PCI, EISA, MicroChannel
1348 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1349 newer boards don't support it. If you have ISA, say Y, otherwise N.
1351 # Select ISA DMA controller support
1356 # Select ISA DMA interface
1361 bool "PCI support" if MIGHT_HAVE_PCI
1363 Find out whether you have a PCI motherboard. PCI is the name of a
1364 bus system, i.e. the way the CPU talks to the other stuff inside
1365 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1366 VESA. If you have PCI, say Y, otherwise N.
1372 config PCI_NANOENGINE
1373 bool "BSE nanoEngine PCI support"
1374 depends on SA1100_NANOENGINE
1376 Enable PCI on the BSE nanoEngine board.
1381 # Select the host bridge type
1382 config PCI_HOST_VIA82C505
1384 depends on PCI && ARCH_SHARK
1387 config PCI_HOST_ITE8152
1389 depends on PCI && MACH_ARMCORE
1393 source "drivers/pci/Kconfig"
1395 source "drivers/pcmcia/Kconfig"
1399 menu "Kernel Features"
1401 source "kernel/time/Kconfig"
1404 bool "Symmetric Multi-Processing"
1405 depends on CPU_V6K || CPU_V7
1406 depends on GENERIC_CLOCKEVENTS
1407 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1408 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1409 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1410 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1412 select USE_GENERIC_SMP_HELPERS
1413 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1415 This enables support for systems with more than one CPU. If you have
1416 a system with only one CPU, like most personal computers, say N. If
1417 you have a system with more than one CPU, say Y.
1419 If you say N here, the kernel will run on single and multiprocessor
1420 machines, but will use only one CPU of a multiprocessor machine. If
1421 you say Y here, the kernel will run on many, but not all, single
1422 processor machines. On a single processor machine, the kernel will
1423 run faster if you say N here.
1425 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1426 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1427 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1429 If you don't know what to do here, say N.
1432 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1433 depends on EXPERIMENTAL
1434 depends on SMP && !XIP_KERNEL
1437 SMP kernels contain instructions which fail on non-SMP processors.
1438 Enabling this option allows the kernel to modify itself to make
1439 these instructions safe. Disabling it allows about 1K of space
1442 If you don't know what to do here, say Y.
1444 config ARM_CPU_TOPOLOGY
1445 bool "Support cpu topology definition"
1446 depends on SMP && CPU_V7
1449 Support ARM cpu topology definition. The MPIDR register defines
1450 affinity between processors which is then used to describe the cpu
1451 topology of an ARM System.
1454 bool "Multi-core scheduler support"
1455 depends on ARM_CPU_TOPOLOGY
1457 Multi-core scheduler support improves the CPU scheduler's decision
1458 making when dealing with multi-core CPU chips at a cost of slightly
1459 increased overhead in some places. If unsure say N here.
1462 bool "SMT scheduler support"
1463 depends on ARM_CPU_TOPOLOGY
1465 Improves the CPU scheduler's decision making when dealing with
1466 MultiThreading at a cost of slightly increased overhead in some
1467 places. If unsure say N here.
1472 This option enables support for the ARM system coherency unit
1479 This options enables support for the ARM timer and watchdog unit
1482 prompt "Memory split"
1485 Select the desired split between kernel and user memory.
1487 If you are not absolutely sure what you are doing, leave this
1491 bool "3G/1G user/kernel split"
1493 bool "2G/2G user/kernel split"
1495 bool "1G/3G user/kernel split"
1500 default 0x40000000 if VMSPLIT_1G
1501 default 0x80000000 if VMSPLIT_2G
1505 int "Maximum number of CPUs (2-32)"
1511 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1512 depends on SMP && HOTPLUG && EXPERIMENTAL
1514 Say Y here to experiment with turning CPUs off and on. CPUs
1515 can be controlled through /sys/devices/system/cpu.
1518 bool "Use local timer interrupts"
1521 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1523 Enable support for local timers on SMP platforms, rather then the
1524 legacy IPI broadcast method. Local timers allows the system
1525 accounting to be spread across the timer interval, preventing a
1526 "thundering herd" at every timer tick.
1528 source kernel/Kconfig.preempt
1532 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1533 ARCH_S5PV210 || ARCH_EXYNOS4
1534 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1535 default AT91_TIMER_HZ if ARCH_AT91
1536 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1539 config THUMB2_KERNEL
1540 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1541 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1543 select ARM_ASM_UNIFIED
1546 By enabling this option, the kernel will be compiled in
1547 Thumb-2 mode. A compiler/assembler that understand the unified
1548 ARM-Thumb syntax is needed.
1552 config THUMB2_AVOID_R_ARM_THM_JUMP11
1553 bool "Work around buggy Thumb-2 short branch relocations in gas"
1554 depends on THUMB2_KERNEL && MODULES
1557 Various binutils versions can resolve Thumb-2 branches to
1558 locally-defined, preemptible global symbols as short-range "b.n"
1559 branch instructions.
1561 This is a problem, because there's no guarantee the final
1562 destination of the symbol, or any candidate locations for a
1563 trampoline, are within range of the branch. For this reason, the
1564 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1565 relocation in modules at all, and it makes little sense to add
1568 The symptom is that the kernel fails with an "unsupported
1569 relocation" error when loading some modules.
1571 Until fixed tools are available, passing
1572 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1573 code which hits this problem, at the cost of a bit of extra runtime
1574 stack usage in some cases.
1576 The problem is described in more detail at:
1577 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1579 Only Thumb-2 kernels are affected.
1581 Unless you are sure your tools don't have this problem, say Y.
1583 config ARM_ASM_UNIFIED
1587 bool "Use the ARM EABI to compile the kernel"
1589 This option allows for the kernel to be compiled using the latest
1590 ARM ABI (aka EABI). This is only useful if you are using a user
1591 space environment that is also compiled with EABI.
1593 Since there are major incompatibilities between the legacy ABI and
1594 EABI, especially with regard to structure member alignment, this
1595 option also changes the kernel syscall calling convention to
1596 disambiguate both ABIs and allow for backward compatibility support
1597 (selected with CONFIG_OABI_COMPAT).
1599 To use this you need GCC version 4.0.0 or later.
1602 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1603 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1606 This option preserves the old syscall interface along with the
1607 new (ARM EABI) one. It also provides a compatibility layer to
1608 intercept syscalls that have structure arguments which layout
1609 in memory differs between the legacy ABI and the new ARM EABI
1610 (only for non "thumb" binaries). This option adds a tiny
1611 overhead to all syscalls and produces a slightly larger kernel.
1612 If you know you'll be using only pure EABI user space then you
1613 can say N here. If this option is not selected and you attempt
1614 to execute a legacy ABI binary then the result will be
1615 UNPREDICTABLE (in fact it can be predicted that it won't work
1616 at all). If in doubt say Y.
1618 config ARCH_HAS_HOLES_MEMORYMODEL
1621 config ARCH_SPARSEMEM_ENABLE
1624 config ARCH_SPARSEMEM_DEFAULT
1625 def_bool ARCH_SPARSEMEM_ENABLE
1627 config ARCH_SELECT_MEMORY_MODEL
1628 def_bool ARCH_SPARSEMEM_ENABLE
1630 config HAVE_ARCH_PFN_VALID
1631 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1634 bool "High Memory Support"
1637 The address space of ARM processors is only 4 Gigabytes large
1638 and it has to accommodate user address space, kernel address
1639 space as well as some memory mapped IO. That means that, if you
1640 have a large amount of physical memory and/or IO, not all of the
1641 memory can be "permanently mapped" by the kernel. The physical
1642 memory that is not permanently mapped is called "high memory".
1644 Depending on the selected kernel/user memory split, minimum
1645 vmalloc space and actual amount of RAM, you may not need this
1646 option which should result in a slightly faster kernel.
1651 bool "Allocate 2nd-level pagetables from highmem"
1654 config HW_PERF_EVENTS
1655 bool "Enable hardware performance counter support for perf events"
1656 depends on PERF_EVENTS && CPU_HAS_PMU
1659 Enable hardware performance counter support for perf events. If
1660 disabled, perf events will use software events only.
1664 config FORCE_MAX_ZONEORDER
1665 int "Maximum zone order" if ARCH_SHMOBILE
1666 range 11 64 if ARCH_SHMOBILE
1667 default "9" if SA1111
1670 The kernel memory allocator divides physically contiguous memory
1671 blocks into "zones", where each zone is a power of two number of
1672 pages. This option selects the largest power of two that the kernel
1673 keeps in the memory allocator. If you need to allocate very large
1674 blocks of physically contiguous memory, then you may need to
1675 increase this value.
1677 This config option is actually maximum order plus one. For example,
1678 a value of 11 means that the largest free memory block is 2^10 pages.
1681 bool "Timer and CPU usage LEDs"
1682 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1683 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1684 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1685 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1686 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1687 ARCH_AT91 || ARCH_DAVINCI || \
1688 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1690 If you say Y here, the LEDs on your machine will be used
1691 to provide useful information about your current system status.
1693 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1694 be able to select which LEDs are active using the options below. If
1695 you are compiling a kernel for the EBSA-110 or the LART however, the
1696 red LED will simply flash regularly to indicate that the system is
1697 still functional. It is safe to say Y here if you have a CATS
1698 system, but the driver will do nothing.
1701 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1702 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1703 || MACH_OMAP_PERSEUS2
1705 depends on !GENERIC_CLOCKEVENTS
1706 default y if ARCH_EBSA110
1708 If you say Y here, one of the system LEDs (the green one on the
1709 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1710 will flash regularly to indicate that the system is still
1711 operational. This is mainly useful to kernel hackers who are
1712 debugging unstable kernels.
1714 The LART uses the same LED for both Timer LED and CPU usage LED
1715 functions. You may choose to use both, but the Timer LED function
1716 will overrule the CPU usage LED.
1719 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1721 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1722 || MACH_OMAP_PERSEUS2
1725 If you say Y here, the red LED will be used to give a good real
1726 time indication of CPU usage, by lighting whenever the idle task
1727 is not currently executing.
1729 The LART uses the same LED for both Timer LED and CPU usage LED
1730 functions. You may choose to use both, but the Timer LED function
1731 will overrule the CPU usage LED.
1733 config ALIGNMENT_TRAP
1735 depends on CPU_CP15_MMU
1736 default y if !ARCH_EBSA110
1737 select HAVE_PROC_CPU if PROC_FS
1739 ARM processors cannot fetch/store information which is not
1740 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1741 address divisible by 4. On 32-bit ARM processors, these non-aligned
1742 fetch/store instructions will be emulated in software if you say
1743 here, which has a severe performance impact. This is necessary for
1744 correct operation of some network protocols. With an IP-only
1745 configuration it is safe to say N, otherwise say Y.
1747 config UACCESS_WITH_MEMCPY
1748 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1749 depends on MMU && EXPERIMENTAL
1750 default y if CPU_FEROCEON
1752 Implement faster copy_to_user and clear_user methods for CPU
1753 cores where a 8-word STM instruction give significantly higher
1754 memory write throughput than a sequence of individual 32bit stores.
1756 A possible side effect is a slight increase in scheduling latency
1757 between threads sharing the same address space if they invoke
1758 such copy operations with large buffers.
1760 However, if the CPU data cache is using a write-allocate mode,
1761 this option is unlikely to provide any performance gain.
1765 prompt "Enable seccomp to safely compute untrusted bytecode"
1767 This kernel feature is useful for number crunching applications
1768 that may need to compute untrusted bytecode during their
1769 execution. By using pipes or other transports made available to
1770 the process as file descriptors supporting the read/write
1771 syscalls, it's possible to isolate those applications in
1772 their own address space using seccomp. Once seccomp is
1773 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1774 and the task is only allowed to execute a few safe syscalls
1775 defined by each seccomp mode.
1777 config CC_STACKPROTECTOR
1778 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1779 depends on EXPERIMENTAL
1781 This option turns on the -fstack-protector GCC feature. This
1782 feature puts, at the beginning of functions, a canary value on
1783 the stack just before the return address, and validates
1784 the value just before actually returning. Stack based buffer
1785 overflows (that need to overwrite this return address) now also
1786 overwrite the canary, which gets detected and the attack is then
1787 neutralized via a kernel panic.
1788 This feature requires gcc version 4.2 or above.
1790 config DEPRECATED_PARAM_STRUCT
1791 bool "Provide old way to pass kernel parameters"
1793 This was deprecated in 2001 and announced to live on for 5 years.
1794 Some old boot loaders still use this way.
1801 bool "Flattened Device Tree support"
1803 select OF_EARLY_FLATTREE
1806 Include support for flattened device tree machine descriptions.
1808 # Compressed boot loader in ROM. Yes, we really want to ask about
1809 # TEXT and BSS so we preserve their values in the config files.
1810 config ZBOOT_ROM_TEXT
1811 hex "Compressed ROM boot loader base address"
1814 The physical address at which the ROM-able zImage is to be
1815 placed in the target. Platforms which normally make use of
1816 ROM-able zImage formats normally set this to a suitable
1817 value in their defconfig file.
1819 If ZBOOT_ROM is not enabled, this has no effect.
1821 config ZBOOT_ROM_BSS
1822 hex "Compressed ROM boot loader BSS address"
1825 The base address of an area of read/write memory in the target
1826 for the ROM-able zImage which must be available while the
1827 decompressor is running. It must be large enough to hold the
1828 entire decompressed kernel plus an additional 128 KiB.
1829 Platforms which normally make use of ROM-able zImage formats
1830 normally set this to a suitable value in their defconfig file.
1832 If ZBOOT_ROM is not enabled, this has no effect.
1835 bool "Compressed boot loader in ROM/flash"
1836 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1838 Say Y here if you intend to execute your compressed kernel image
1839 (zImage) directly from ROM or flash. If unsure, say N.
1842 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1843 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1844 default ZBOOT_ROM_NONE
1846 Include experimental SD/MMC loading code in the ROM-able zImage.
1847 With this enabled it is possible to write the the ROM-able zImage
1848 kernel image to an MMC or SD card and boot the kernel straight
1849 from the reset vector. At reset the processor Mask ROM will load
1850 the first part of the the ROM-able zImage which in turn loads the
1851 rest the kernel image to RAM.
1853 config ZBOOT_ROM_NONE
1854 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1856 Do not load image from SD or MMC
1858 config ZBOOT_ROM_MMCIF
1859 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1861 Load image from MMCIF hardware block.
1863 config ZBOOT_ROM_SH_MOBILE_SDHI
1864 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1866 Load image from SDHI hardware block
1870 config ARM_APPENDED_DTB
1871 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1872 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1874 With this option, the boot code will look for a device tree binary
1875 (DTB) appended to zImage
1876 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1878 This is meant as a backward compatibility convenience for those
1879 systems with a bootloader that can't be upgraded to accommodate
1880 the documented boot protocol using a device tree.
1882 Beware that there is very little in terms of protection against
1883 this option being confused by leftover garbage in memory that might
1884 look like a DTB header after a reboot if no actual DTB is appended
1885 to zImage. Do not leave this option active in a production kernel
1886 if you don't intend to always append a DTB. Proper passing of the
1887 location into r2 of a bootloader provided DTB is always preferable
1890 config ARM_ATAG_DTB_COMPAT
1891 bool "Supplement the appended DTB with traditional ATAG information"
1892 depends on ARM_APPENDED_DTB
1894 Some old bootloaders can't be updated to a DTB capable one, yet
1895 they provide ATAGs with memory configuration, the ramdisk address,
1896 the kernel cmdline string, etc. Such information is dynamically
1897 provided by the bootloader and can't always be stored in a static
1898 DTB. To allow a device tree enabled kernel to be used with such
1899 bootloaders, this option allows zImage to extract the information
1900 from the ATAG list and store it at run time into the appended DTB.
1903 string "Default kernel command string"
1906 On some architectures (EBSA110 and CATS), there is currently no way
1907 for the boot loader to pass arguments to the kernel. For these
1908 architectures, you should supply some command-line options at build
1909 time by entering them here. As a minimum, you should specify the
1910 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1913 prompt "Kernel command line type" if CMDLINE != ""
1914 default CMDLINE_FROM_BOOTLOADER
1916 config CMDLINE_FROM_BOOTLOADER
1917 bool "Use bootloader kernel arguments if available"
1919 Uses the command-line options passed by the boot loader. If
1920 the boot loader doesn't provide any, the default kernel command
1921 string provided in CMDLINE will be used.
1923 config CMDLINE_EXTEND
1924 bool "Extend bootloader kernel arguments"
1926 The command-line arguments provided by the boot loader will be
1927 appended to the default kernel command string.
1929 config CMDLINE_FORCE
1930 bool "Always use the default kernel command string"
1932 Always use the default kernel command string, even if the boot
1933 loader passes other arguments to the kernel.
1934 This is useful if you cannot or don't want to change the
1935 command-line options your boot loader passes to the kernel.
1939 bool "Kernel Execute-In-Place from ROM"
1940 depends on !ZBOOT_ROM
1942 Execute-In-Place allows the kernel to run from non-volatile storage
1943 directly addressable by the CPU, such as NOR flash. This saves RAM
1944 space since the text section of the kernel is not loaded from flash
1945 to RAM. Read-write sections, such as the data section and stack,
1946 are still copied to RAM. The XIP kernel is not compressed since
1947 it has to run directly from flash, so it will take more space to
1948 store it. The flash address used to link the kernel object files,
1949 and for storing it, is configuration dependent. Therefore, if you
1950 say Y here, you must know the proper physical address where to
1951 store the kernel image depending on your own flash memory usage.
1953 Also note that the make target becomes "make xipImage" rather than
1954 "make zImage" or "make Image". The final kernel binary to put in
1955 ROM memory will be arch/arm/boot/xipImage.
1959 config XIP_PHYS_ADDR
1960 hex "XIP Kernel Physical Location"
1961 depends on XIP_KERNEL
1962 default "0x00080000"
1964 This is the physical address in your flash memory the kernel will
1965 be linked for and stored to. This address is dependent on your
1969 bool "Kexec system call (EXPERIMENTAL)"
1970 depends on EXPERIMENTAL
1972 kexec is a system call that implements the ability to shutdown your
1973 current kernel, and to start another kernel. It is like a reboot
1974 but it is independent of the system firmware. And like a reboot
1975 you can start any kernel with it, not just Linux.
1977 It is an ongoing process to be certain the hardware in a machine
1978 is properly shutdown, so do not be surprised if this code does not
1979 initially work for you. It may help to enable device hotplugging
1983 bool "Export atags in procfs"
1987 Should the atags used to boot the kernel be exported in an "atags"
1988 file in procfs. Useful with kexec.
1991 bool "Build kdump crash kernel (EXPERIMENTAL)"
1992 depends on EXPERIMENTAL
1994 Generate crash dump after being started by kexec. This should
1995 be normally only set in special crash dump kernels which are
1996 loaded in the main kernel with kexec-tools into a specially
1997 reserved region and then later executed after a crash by
1998 kdump/kexec. The crash dump kernel must be compiled to a
1999 memory address not used by the main kernel
2001 For more details see Documentation/kdump/kdump.txt
2003 config AUTO_ZRELADDR
2004 bool "Auto calculation of the decompressed kernel image address"
2005 depends on !ZBOOT_ROM && !ARCH_U300
2007 ZRELADDR is the physical address where the decompressed kernel
2008 image will be placed. If AUTO_ZRELADDR is selected, the address
2009 will be determined at run-time by masking the current IP with
2010 0xf8000000. This assumes the zImage being placed in the first 128MB
2011 from start of memory.
2015 menu "CPU Power Management"
2019 source "drivers/cpufreq/Kconfig"
2022 tristate "CPUfreq driver for i.MX CPUs"
2023 depends on ARCH_MXC && CPU_FREQ
2025 This enables the CPUfreq driver for i.MX CPUs.
2027 config CPU_FREQ_SA1100
2030 config CPU_FREQ_SA1110
2033 config CPU_FREQ_INTEGRATOR
2034 tristate "CPUfreq driver for ARM Integrator CPUs"
2035 depends on ARCH_INTEGRATOR && CPU_FREQ
2038 This enables the CPUfreq driver for ARM Integrator CPUs.
2040 For details, take a look at <file:Documentation/cpu-freq>.
2046 depends on CPU_FREQ && ARCH_PXA && PXA25x
2048 select CPU_FREQ_TABLE
2049 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2054 Internal configuration node for common cpufreq on Samsung SoC
2056 config CPU_FREQ_S3C24XX
2057 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2058 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
2061 This enables the CPUfreq driver for the Samsung S3C24XX family
2064 For details, take a look at <file:Documentation/cpu-freq>.
2068 config CPU_FREQ_S3C24XX_PLL
2069 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2070 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2072 Compile in support for changing the PLL frequency from the
2073 S3C24XX series CPUfreq driver. The PLL takes time to settle
2074 after a frequency change, so by default it is not enabled.
2076 This also means that the PLL tables for the selected CPU(s) will
2077 be built which may increase the size of the kernel image.
2079 config CPU_FREQ_S3C24XX_DEBUG
2080 bool "Debug CPUfreq Samsung driver core"
2081 depends on CPU_FREQ_S3C24XX
2083 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2085 config CPU_FREQ_S3C24XX_IODEBUG
2086 bool "Debug CPUfreq Samsung driver IO timing"
2087 depends on CPU_FREQ_S3C24XX
2089 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2091 config CPU_FREQ_S3C24XX_DEBUGFS
2092 bool "Export debugfs for CPUFreq"
2093 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2095 Export status information via debugfs.
2099 source "drivers/cpuidle/Kconfig"
2103 menu "Floating point emulation"
2105 comment "At least one emulation must be selected"
2108 bool "NWFPE math emulation"
2109 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2111 Say Y to include the NWFPE floating point emulator in the kernel.
2112 This is necessary to run most binaries. Linux does not currently
2113 support floating point hardware so you need to say Y here even if
2114 your machine has an FPA or floating point co-processor podule.
2116 You may say N here if you are going to load the Acorn FPEmulator
2117 early in the bootup.
2120 bool "Support extended precision"
2121 depends on FPE_NWFPE
2123 Say Y to include 80-bit support in the kernel floating-point
2124 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2125 Note that gcc does not generate 80-bit operations by default,
2126 so in most cases this option only enlarges the size of the
2127 floating point emulator without any good reason.
2129 You almost surely want to say N here.
2132 bool "FastFPE math emulation (EXPERIMENTAL)"
2133 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2135 Say Y here to include the FAST floating point emulator in the kernel.
2136 This is an experimental much faster emulator which now also has full
2137 precision for the mantissa. It does not support any exceptions.
2138 It is very simple, and approximately 3-6 times faster than NWFPE.
2140 It should be sufficient for most programs. It may be not suitable
2141 for scientific calculations, but you have to check this for yourself.
2142 If you do not feel you need a faster FP emulation you should better
2146 bool "VFP-format floating point maths"
2147 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2149 Say Y to include VFP support code in the kernel. This is needed
2150 if your hardware includes a VFP unit.
2152 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2153 release notes and additional status information.
2155 Say N if your target does not have VFP hardware.
2163 bool "Advanced SIMD (NEON) Extension support"
2164 depends on VFPv3 && CPU_V7
2166 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2171 menu "Userspace binary formats"
2173 source "fs/Kconfig.binfmt"
2176 tristate "RISC OS personality"
2179 Say Y here to include the kernel code necessary if you want to run
2180 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2181 experimental; if this sounds frightening, say N and sleep in peace.
2182 You can also say M here to compile this support as a module (which
2183 will be called arthur).
2187 menu "Power management options"
2189 source "kernel/power/Kconfig"
2191 config ARCH_SUSPEND_POSSIBLE
2192 depends on !ARCH_S5P64X0 && !ARCH_S5PC100
2193 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2194 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2197 config ARM_CPU_SUSPEND
2202 source "net/Kconfig"
2204 source "drivers/Kconfig"
2208 source "arch/arm/Kconfig.debug"
2210 source "security/Kconfig"
2212 source "crypto/Kconfig"
2214 source "lib/Kconfig"