5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if !XIP_KERNEL
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
32 select CPU_PM if (SUSPEND || CPU_IDLE)
34 The ARM series is a line of low-power-consumption RISC chip designs
35 licensed by ARM Ltd and targeted at embedded applications and
36 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
37 manufactured, but legacy ARM-based PC hardware remains popular in
38 Europe. There is an ARM Linux project with a web page at
39 <http://www.arm.linux.org.uk/>.
41 config ARM_HAS_SG_CHAIN
50 config SYS_SUPPORTS_APM_EMULATION
53 config HAVE_SCHED_CLOCK
59 config ARCH_USES_GETTIMEOFFSET
63 config GENERIC_CLOCKEVENTS
66 config GENERIC_CLOCKEVENTS_BROADCAST
68 depends on GENERIC_CLOCKEVENTS
77 select GENERIC_ALLOCATOR
88 The Extended Industry Standard Architecture (EISA) bus was
89 developed as an open alternative to the IBM MicroChannel bus.
91 The EISA bus provided some of the features of the IBM MicroChannel
92 bus while maintaining backward compatibility with cards made for
93 the older ISA bus. The EISA bus saw limited use between 1988 and
94 1995 when it was made obsolete by the PCI bus.
96 Say Y here if you are building a kernel for an EISA-based machine.
106 MicroChannel Architecture is found in some IBM PS/2 machines and
107 laptops. It is a bus system similar to PCI or ISA. See
108 <file:Documentation/mca.txt> (and especially the web page given
109 there) before attempting to build an MCA bus kernel.
111 config STACKTRACE_SUPPORT
115 config HAVE_LATENCYTOP_SUPPORT
120 config LOCKDEP_SUPPORT
124 config TRACE_IRQFLAGS_SUPPORT
128 config HARDIRQS_SW_RESEND
132 config GENERIC_IRQ_PROBE
136 config GENERIC_LOCKBREAK
139 depends on SMP && PREEMPT
141 config RWSEM_GENERIC_SPINLOCK
145 config RWSEM_XCHGADD_ALGORITHM
148 config ARCH_HAS_ILOG2_U32
151 config ARCH_HAS_ILOG2_U64
154 config ARCH_HAS_CPUFREQ
157 Internal node to signify that the ARCH has CPUFREQ support
158 and that the relevant menu configurations are displayed for
161 config ARCH_HAS_CPU_IDLE_WAIT
164 config GENERIC_HWEIGHT
168 config GENERIC_CALIBRATE_DELAY
172 config ARCH_MAY_HAVE_PC_FDC
178 config NEED_DMA_MAP_STATE
181 config GENERIC_ISA_DMA
192 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
193 default DRAM_BASE if REMAP_VECTORS_TO_RAM
196 The base address of exception vectors.
198 config ARM_PATCH_PHYS_VIRT
199 bool "Patch physical to virtual translations at runtime" if EMBEDDED
201 depends on !XIP_KERNEL && MMU
202 depends on !ARCH_REALVIEW || !SPARSEMEM
204 Patch phys-to-virt and virt-to-phys translation functions at
205 boot and module load time according to the position of the
206 kernel in system memory.
208 This can only be used with non-XIP MMU kernels where the base
209 of physical memory is at a 16MB boundary.
211 Only disable this option if you know that you do not require
212 this feature (eg, building a kernel for a single machine) and
213 you need to shrink the kernel to the minimal size.
215 config NEED_MACH_MEMORY_H
218 Select this when mach/memory.h is required to provide special
219 definitions for this platform. The need for mach/memory.h should
220 be avoided when possible.
223 hex "Physical address of main memory"
224 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
226 Please provide the physical address corresponding to the
227 location of main memory in your system.
229 source "init/Kconfig"
231 source "kernel/Kconfig.freezer"
236 bool "MMU-based Paged Memory Management Support"
239 Select if you want MMU-based virtualised addressing space
240 support by paged memory management. If unsure, say 'Y'.
243 # The "ARM system type" choice list is ordered alphabetically by option
244 # text. Please add new entries in the option alphabetic order.
247 prompt "ARM system type"
248 default ARCH_VERSATILE
250 config ARCH_INTEGRATOR
251 bool "ARM Ltd. Integrator family"
253 select ARCH_HAS_CPUFREQ
255 select HAVE_MACH_CLKDEV
257 select GENERIC_CLOCKEVENTS
258 select PLAT_VERSATILE
259 select PLAT_VERSATILE_FPGA_IRQ
260 select NEED_MACH_MEMORY_H
262 Support for ARM's Integrator platform.
265 bool "ARM Ltd. RealView family"
268 select HAVE_MACH_CLKDEV
270 select GENERIC_CLOCKEVENTS
271 select ARCH_WANT_OPTIONAL_GPIOLIB
272 select PLAT_VERSATILE
273 select PLAT_VERSATILE_CLCD
274 select ARM_TIMER_SP804
275 select GPIO_PL061 if GPIOLIB
276 select NEED_MACH_MEMORY_H
278 This enables support for ARM Ltd RealView boards.
280 config ARCH_VERSATILE
281 bool "ARM Ltd. Versatile family"
285 select HAVE_MACH_CLKDEV
287 select GENERIC_CLOCKEVENTS
288 select ARCH_WANT_OPTIONAL_GPIOLIB
289 select PLAT_VERSATILE
290 select PLAT_VERSATILE_CLCD
291 select PLAT_VERSATILE_FPGA_IRQ
292 select ARM_TIMER_SP804
294 This enables support for ARM Ltd Versatile board.
297 bool "ARM Ltd. Versatile Express family"
298 select ARCH_WANT_OPTIONAL_GPIOLIB
300 select ARM_TIMER_SP804
302 select HAVE_MACH_CLKDEV
303 select GENERIC_CLOCKEVENTS
305 select HAVE_PATA_PLATFORM
307 select PLAT_VERSATILE
308 select PLAT_VERSATILE_CLCD
310 This enables support for the ARM Ltd Versatile Express boards.
314 select ARCH_REQUIRE_GPIOLIB
318 This enables support for systems based on the Atmel AT91RM9200,
319 AT91SAM9 and AT91CAP9 processors.
322 bool "Broadcom BCMRING"
326 select ARM_TIMER_SP804
328 select GENERIC_CLOCKEVENTS
329 select ARCH_WANT_OPTIONAL_GPIOLIB
331 Support for Broadcom's BCMRing platform.
334 bool "Calxeda Highbank-based"
335 select ARCH_WANT_OPTIONAL_GPIOLIB
338 select ARM_TIMER_SP804
341 select GENERIC_CLOCKEVENTS
345 Support for the Calxeda Highbank SoC based boards.
348 bool "Cirrus Logic CLPS711x/EP721x-based"
350 select ARCH_USES_GETTIMEOFFSET
351 select NEED_MACH_MEMORY_H
353 Support for Cirrus Logic 711x/721x based boards.
356 bool "Cavium Networks CNS3XXX family"
358 select GENERIC_CLOCKEVENTS
360 select MIGHT_HAVE_PCI
361 select PCI_DOMAINS if PCI
363 Support for Cavium Networks CNS3XXX platform.
366 bool "Cortina Systems Gemini"
368 select ARCH_REQUIRE_GPIOLIB
369 select ARCH_USES_GETTIMEOFFSET
371 Support for the Cortina Systems Gemini family SoCs
374 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
378 select GENERIC_CLOCKEVENTS
380 select GENERIC_IRQ_CHIP
384 Support for CSR SiRFSoC ARM Cortex A9 Platform
391 select ARCH_USES_GETTIMEOFFSET
392 select NEED_MACH_MEMORY_H
394 This is an evaluation board for the StrongARM processor available
395 from Digital. It has limited hardware on-board, including an
396 Ethernet interface, two PCMCIA sockets, two serial ports and a
405 select ARCH_REQUIRE_GPIOLIB
406 select ARCH_HAS_HOLES_MEMORYMODEL
407 select ARCH_USES_GETTIMEOFFSET
410 This enables support for the Cirrus EP93xx series of CPUs.
412 config ARCH_FOOTBRIDGE
416 select GENERIC_CLOCKEVENTS
417 select NEED_MACH_MEMORY_H
419 Support for systems based on the DC21285 companion chip
420 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
423 bool "Freescale MXC/iMX-based"
424 select GENERIC_CLOCKEVENTS
425 select ARCH_REQUIRE_GPIOLIB
428 select GENERIC_IRQ_CHIP
429 select HAVE_SCHED_CLOCK
430 select MULTI_IRQ_HANDLER
432 Support for Freescale MXC/iMX-based family of processors
435 bool "Freescale MXS-based"
436 select GENERIC_CLOCKEVENTS
437 select ARCH_REQUIRE_GPIOLIB
441 Support for Freescale MXS-based family of processors
444 bool "Hilscher NetX based"
448 select GENERIC_CLOCKEVENTS
450 This enables support for systems based on the Hilscher NetX Soc
453 bool "Hynix HMS720x-based"
456 select ARCH_USES_GETTIMEOFFSET
458 This enables support for systems based on the Hynix HMS720x
466 select ARCH_SUPPORTS_MSI
468 select NEED_MACH_MEMORY_H
470 Support for Intel's IOP13XX (XScale) family of processors.
478 select ARCH_REQUIRE_GPIOLIB
480 Support for Intel's 80219 and IOP32X (XScale) family of
489 select ARCH_REQUIRE_GPIOLIB
491 Support for Intel's IOP33X (XScale) family of processors.
498 select ARCH_USES_GETTIMEOFFSET
499 select NEED_MACH_MEMORY_H
501 Support for Intel's IXP23xx (XScale) family of processors.
504 bool "IXP2400/2800-based"
508 select ARCH_USES_GETTIMEOFFSET
509 select NEED_MACH_MEMORY_H
511 Support for Intel's IXP2400/2800 (XScale) family of processors.
519 select GENERIC_CLOCKEVENTS
520 select HAVE_SCHED_CLOCK
521 select MIGHT_HAVE_PCI
522 select DMABOUNCE if PCI
524 Support for Intel's IXP4XX (XScale) family of processors.
530 select ARCH_REQUIRE_GPIOLIB
531 select GENERIC_CLOCKEVENTS
534 Support for the Marvell Dove SoC 88AP510
537 bool "Marvell Kirkwood"
540 select ARCH_REQUIRE_GPIOLIB
541 select GENERIC_CLOCKEVENTS
544 Support for the following Marvell Kirkwood series SoCs:
545 88F6180, 88F6192 and 88F6281.
551 select ARCH_REQUIRE_GPIOLIB
554 select USB_ARCH_HAS_OHCI
557 select GENERIC_CLOCKEVENTS
559 Support for the NXP LPC32XX family of processors
562 bool "Marvell MV78xx0"
565 select ARCH_REQUIRE_GPIOLIB
566 select GENERIC_CLOCKEVENTS
569 Support for the following Marvell MV78xx0 series SoCs:
577 select ARCH_REQUIRE_GPIOLIB
578 select GENERIC_CLOCKEVENTS
581 Support for the following Marvell Orion 5x series SoCs:
582 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
583 Orion-2 (5281), Orion-1-90 (6183).
586 bool "Marvell PXA168/910/MMP2"
588 select ARCH_REQUIRE_GPIOLIB
590 select GENERIC_CLOCKEVENTS
591 select HAVE_SCHED_CLOCK
596 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
599 bool "Micrel/Kendin KS8695"
601 select ARCH_REQUIRE_GPIOLIB
602 select ARCH_USES_GETTIMEOFFSET
603 select NEED_MACH_MEMORY_H
605 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
606 System-on-Chip devices.
609 bool "Nuvoton W90X900 CPU"
611 select ARCH_REQUIRE_GPIOLIB
614 select GENERIC_CLOCKEVENTS
616 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
617 At present, the w90x900 has been renamed nuc900, regarding
618 the ARM series product line, you can login the following
619 link address to know more.
621 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
622 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
625 bool "Nuvoton NUC93X CPU"
629 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
630 low-power and high performance MPEG-4/JPEG multimedia controller chip.
637 select GENERIC_CLOCKEVENTS
640 select HAVE_SCHED_CLOCK
641 select ARCH_HAS_CPUFREQ
643 This enables support for NVIDIA Tegra based systems (Tegra APX,
644 Tegra 6xx and Tegra 2 series).
647 bool "Philips Nexperia PNX4008 Mobile"
650 select ARCH_USES_GETTIMEOFFSET
652 This enables support for Philips PNX4008 mobile platform.
655 bool "PXA2xx/PXA3xx-based"
658 select ARCH_HAS_CPUFREQ
661 select ARCH_REQUIRE_GPIOLIB
662 select GENERIC_CLOCKEVENTS
663 select HAVE_SCHED_CLOCK
668 select MULTI_IRQ_HANDLER
670 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
675 select GENERIC_CLOCKEVENTS
676 select ARCH_REQUIRE_GPIOLIB
679 Support for Qualcomm MSM/QSD based systems. This runs on the
680 apps processor of the MSM/QSD and depends on a shared memory
681 interface to the modem processor which runs the baseband
682 stack and controls some vital subsystems
683 (clock and power control, etc).
686 bool "Renesas SH-Mobile / R-Mobile"
689 select HAVE_MACH_CLKDEV
690 select GENERIC_CLOCKEVENTS
693 select MULTI_IRQ_HANDLER
694 select PM_GENERIC_DOMAINS if PM
695 select NEED_MACH_MEMORY_H
697 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
704 select ARCH_MAY_HAVE_PC_FDC
705 select HAVE_PATA_PLATFORM
708 select ARCH_SPARSEMEM_ENABLE
709 select ARCH_USES_GETTIMEOFFSET
710 select NEED_MACH_MEMORY_H
712 On the Acorn Risc-PC, Linux can support the internal IDE disk and
713 CD-ROM interface, serial and parallel port, and the floppy drive.
720 select ARCH_SPARSEMEM_ENABLE
722 select ARCH_HAS_CPUFREQ
724 select GENERIC_CLOCKEVENTS
726 select HAVE_SCHED_CLOCK
728 select ARCH_REQUIRE_GPIOLIB
729 select NEED_MACH_MEMORY_H
731 Support for StrongARM 11x0 based boards.
734 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
736 select ARCH_HAS_CPUFREQ
739 select ARCH_USES_GETTIMEOFFSET
740 select HAVE_S3C2410_I2C if I2C
742 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
743 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
744 the Samsung SMDK2410 development board (and derivatives).
746 Note, the S3C2416 and the S3C2450 are so close that they even share
747 the same SoC ID code. This means that there is no separate machine
748 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
751 bool "Samsung S3C64XX"
758 select ARCH_USES_GETTIMEOFFSET
759 select ARCH_HAS_CPUFREQ
760 select ARCH_REQUIRE_GPIOLIB
761 select SAMSUNG_CLKSRC
762 select SAMSUNG_IRQ_VIC_TIMER
763 select SAMSUNG_IRQ_UART
764 select S3C_GPIO_TRACK
765 select S3C_GPIO_PULL_UPDOWN
766 select S3C_GPIO_CFG_S3C24XX
767 select S3C_GPIO_CFG_S3C64XX
769 select USB_ARCH_HAS_OHCI
770 select SAMSUNG_GPIOLIB_4BIT
771 select HAVE_S3C2410_I2C if I2C
772 select HAVE_S3C2410_WATCHDOG if WATCHDOG
774 Samsung S3C64XX series based systems
777 bool "Samsung S5P6440 S5P6450"
783 select HAVE_S3C2410_WATCHDOG if WATCHDOG
784 select GENERIC_CLOCKEVENTS
785 select HAVE_SCHED_CLOCK
786 select HAVE_S3C2410_I2C if I2C
787 select HAVE_S3C_RTC if RTC_CLASS
789 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
793 bool "Samsung S5PC100"
798 select ARM_L1_CACHE_SHIFT_6
799 select ARCH_USES_GETTIMEOFFSET
800 select HAVE_S3C2410_I2C if I2C
801 select HAVE_S3C_RTC if RTC_CLASS
802 select HAVE_S3C2410_WATCHDOG if WATCHDOG
804 Samsung S5PC100 series based systems
807 bool "Samsung S5PV210/S5PC110"
809 select ARCH_SPARSEMEM_ENABLE
810 select ARCH_HAS_HOLES_MEMORYMODEL
815 select ARM_L1_CACHE_SHIFT_6
816 select ARCH_HAS_CPUFREQ
817 select GENERIC_CLOCKEVENTS
818 select HAVE_SCHED_CLOCK
819 select HAVE_S3C2410_I2C if I2C
820 select HAVE_S3C_RTC if RTC_CLASS
821 select HAVE_S3C2410_WATCHDOG if WATCHDOG
822 select NEED_MACH_MEMORY_H
824 Samsung S5PV210/S5PC110 series based systems
827 bool "Samsung EXYNOS4"
829 select ARCH_SPARSEMEM_ENABLE
830 select ARCH_HAS_HOLES_MEMORYMODEL
834 select ARCH_HAS_CPUFREQ
835 select GENERIC_CLOCKEVENTS
836 select HAVE_S3C_RTC if RTC_CLASS
837 select HAVE_S3C2410_I2C if I2C
838 select HAVE_S3C2410_WATCHDOG if WATCHDOG
839 select NEED_MACH_MEMORY_H
841 Samsung EXYNOS4 series based systems
850 select ARCH_USES_GETTIMEOFFSET
851 select NEED_MACH_MEMORY_H
853 Support for the StrongARM based Digital DNARD machine, also known
854 as "Shark" (<http://www.shark-linux.de/shark.html>).
857 bool "Telechips TCC ARM926-based systems"
862 select GENERIC_CLOCKEVENTS
864 Support for Telechips TCC ARM926-based systems.
867 bool "ST-Ericsson U300 Series"
871 select HAVE_SCHED_CLOCK
875 select GENERIC_CLOCKEVENTS
877 select HAVE_MACH_CLKDEV
879 select ARCH_REQUIRE_GPIOLIB
880 select NEED_MACH_MEMORY_H
882 Support for ST-Ericsson U300 series mobile platforms.
885 bool "ST-Ericsson U8500 Series"
888 select GENERIC_CLOCKEVENTS
890 select ARCH_REQUIRE_GPIOLIB
891 select ARCH_HAS_CPUFREQ
893 Support for ST-Ericsson's Ux500 architecture
896 bool "STMicroelectronics Nomadik"
901 select GENERIC_CLOCKEVENTS
902 select ARCH_REQUIRE_GPIOLIB
904 Support for the Nomadik platform by ST-Ericsson
908 select GENERIC_CLOCKEVENTS
909 select ARCH_REQUIRE_GPIOLIB
913 select GENERIC_ALLOCATOR
914 select GENERIC_IRQ_CHIP
915 select ARCH_HAS_HOLES_MEMORYMODEL
917 Support for TI's DaVinci platform.
922 select ARCH_REQUIRE_GPIOLIB
923 select ARCH_HAS_CPUFREQ
925 select GENERIC_CLOCKEVENTS
926 select HAVE_SCHED_CLOCK
927 select ARCH_HAS_HOLES_MEMORYMODEL
929 Support for TI's OMAP platform (OMAP1/2/3/4).
934 select ARCH_REQUIRE_GPIOLIB
937 select GENERIC_CLOCKEVENTS
940 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
943 bool "VIA/WonderMedia 85xx"
946 select ARCH_HAS_CPUFREQ
947 select GENERIC_CLOCKEVENTS
948 select ARCH_REQUIRE_GPIOLIB
951 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
954 bool "Xilinx Zynq ARM Cortex A9 Platform"
957 select GENERIC_CLOCKEVENTS
964 Support for Xilinx Zynq ARM Cortex A9 Platform
968 # This is sorted alphabetically by mach-* pathname. However, plat-*
969 # Kconfigs may be included either alphabetically (according to the
970 # plat- suffix) or along side the corresponding mach-* source.
972 source "arch/arm/mach-at91/Kconfig"
974 source "arch/arm/mach-bcmring/Kconfig"
976 source "arch/arm/mach-clps711x/Kconfig"
978 source "arch/arm/mach-cns3xxx/Kconfig"
980 source "arch/arm/mach-davinci/Kconfig"
982 source "arch/arm/mach-dove/Kconfig"
984 source "arch/arm/mach-ep93xx/Kconfig"
986 source "arch/arm/mach-footbridge/Kconfig"
988 source "arch/arm/mach-gemini/Kconfig"
990 source "arch/arm/mach-h720x/Kconfig"
992 source "arch/arm/mach-integrator/Kconfig"
994 source "arch/arm/mach-iop32x/Kconfig"
996 source "arch/arm/mach-iop33x/Kconfig"
998 source "arch/arm/mach-iop13xx/Kconfig"
1000 source "arch/arm/mach-ixp4xx/Kconfig"
1002 source "arch/arm/mach-ixp2000/Kconfig"
1004 source "arch/arm/mach-ixp23xx/Kconfig"
1006 source "arch/arm/mach-kirkwood/Kconfig"
1008 source "arch/arm/mach-ks8695/Kconfig"
1010 source "arch/arm/mach-lpc32xx/Kconfig"
1012 source "arch/arm/mach-msm/Kconfig"
1014 source "arch/arm/mach-mv78xx0/Kconfig"
1016 source "arch/arm/plat-mxc/Kconfig"
1018 source "arch/arm/mach-mxs/Kconfig"
1020 source "arch/arm/mach-netx/Kconfig"
1022 source "arch/arm/mach-nomadik/Kconfig"
1023 source "arch/arm/plat-nomadik/Kconfig"
1025 source "arch/arm/mach-nuc93x/Kconfig"
1027 source "arch/arm/plat-omap/Kconfig"
1029 source "arch/arm/mach-omap1/Kconfig"
1031 source "arch/arm/mach-omap2/Kconfig"
1033 source "arch/arm/mach-orion5x/Kconfig"
1035 source "arch/arm/mach-pxa/Kconfig"
1036 source "arch/arm/plat-pxa/Kconfig"
1038 source "arch/arm/mach-mmp/Kconfig"
1040 source "arch/arm/mach-realview/Kconfig"
1042 source "arch/arm/mach-sa1100/Kconfig"
1044 source "arch/arm/plat-samsung/Kconfig"
1045 source "arch/arm/plat-s3c24xx/Kconfig"
1046 source "arch/arm/plat-s5p/Kconfig"
1048 source "arch/arm/plat-spear/Kconfig"
1050 source "arch/arm/plat-tcc/Kconfig"
1053 source "arch/arm/mach-s3c2410/Kconfig"
1054 source "arch/arm/mach-s3c2412/Kconfig"
1055 source "arch/arm/mach-s3c2416/Kconfig"
1056 source "arch/arm/mach-s3c2440/Kconfig"
1057 source "arch/arm/mach-s3c2443/Kconfig"
1061 source "arch/arm/mach-s3c64xx/Kconfig"
1064 source "arch/arm/mach-s5p64x0/Kconfig"
1066 source "arch/arm/mach-s5pc100/Kconfig"
1068 source "arch/arm/mach-s5pv210/Kconfig"
1070 source "arch/arm/mach-exynos4/Kconfig"
1072 source "arch/arm/mach-shmobile/Kconfig"
1074 source "arch/arm/mach-tegra/Kconfig"
1076 source "arch/arm/mach-u300/Kconfig"
1078 source "arch/arm/mach-ux500/Kconfig"
1080 source "arch/arm/mach-versatile/Kconfig"
1082 source "arch/arm/mach-vexpress/Kconfig"
1083 source "arch/arm/plat-versatile/Kconfig"
1085 source "arch/arm/mach-vt8500/Kconfig"
1087 source "arch/arm/mach-w90x900/Kconfig"
1089 # Definitions to make life easier
1095 select GENERIC_CLOCKEVENTS
1096 select HAVE_SCHED_CLOCK
1101 select GENERIC_IRQ_CHIP
1102 select HAVE_SCHED_CLOCK
1107 config PLAT_VERSATILE
1110 config ARM_TIMER_SP804
1114 source arch/arm/mm/Kconfig
1117 bool "Enable iWMMXt support"
1118 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1119 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1121 Enable support for iWMMXt context switching at run time if
1122 running on a CPU that supports it.
1124 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1127 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1131 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1132 (!ARCH_OMAP3 || OMAP3_EMU)
1136 config MULTI_IRQ_HANDLER
1139 Allow each machine to specify it's own IRQ handler at run time.
1142 source "arch/arm/Kconfig-nommu"
1145 config ARM_ERRATA_411920
1146 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1147 depends on CPU_V6 || CPU_V6K
1149 Invalidation of the Instruction Cache operation can
1150 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1151 It does not affect the MPCore. This option enables the ARM Ltd.
1152 recommended workaround.
1154 config ARM_ERRATA_430973
1155 bool "ARM errata: Stale prediction on replaced interworking branch"
1158 This option enables the workaround for the 430973 Cortex-A8
1159 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1160 interworking branch is replaced with another code sequence at the
1161 same virtual address, whether due to self-modifying code or virtual
1162 to physical address re-mapping, Cortex-A8 does not recover from the
1163 stale interworking branch prediction. This results in Cortex-A8
1164 executing the new code sequence in the incorrect ARM or Thumb state.
1165 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1166 and also flushes the branch target cache at every context switch.
1167 Note that setting specific bits in the ACTLR register may not be
1168 available in non-secure mode.
1170 config ARM_ERRATA_458693
1171 bool "ARM errata: Processor deadlock when a false hazard is created"
1174 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1175 erratum. For very specific sequences of memory operations, it is
1176 possible for a hazard condition intended for a cache line to instead
1177 be incorrectly associated with a different cache line. This false
1178 hazard might then cause a processor deadlock. The workaround enables
1179 the L1 caching of the NEON accesses and disables the PLD instruction
1180 in the ACTLR register. Note that setting specific bits in the ACTLR
1181 register may not be available in non-secure mode.
1183 config ARM_ERRATA_460075
1184 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1187 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1188 erratum. Any asynchronous access to the L2 cache may encounter a
1189 situation in which recent store transactions to the L2 cache are lost
1190 and overwritten with stale memory contents from external memory. The
1191 workaround disables the write-allocate mode for the L2 cache via the
1192 ACTLR register. Note that setting specific bits in the ACTLR register
1193 may not be available in non-secure mode.
1195 config ARM_ERRATA_742230
1196 bool "ARM errata: DMB operation may be faulty"
1197 depends on CPU_V7 && SMP
1199 This option enables the workaround for the 742230 Cortex-A9
1200 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1201 between two write operations may not ensure the correct visibility
1202 ordering of the two writes. This workaround sets a specific bit in
1203 the diagnostic register of the Cortex-A9 which causes the DMB
1204 instruction to behave as a DSB, ensuring the correct behaviour of
1207 config ARM_ERRATA_742231
1208 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1209 depends on CPU_V7 && SMP
1211 This option enables the workaround for the 742231 Cortex-A9
1212 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1213 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1214 accessing some data located in the same cache line, may get corrupted
1215 data due to bad handling of the address hazard when the line gets
1216 replaced from one of the CPUs at the same time as another CPU is
1217 accessing it. This workaround sets specific bits in the diagnostic
1218 register of the Cortex-A9 which reduces the linefill issuing
1219 capabilities of the processor.
1221 config PL310_ERRATA_588369
1222 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1223 depends on CACHE_L2X0
1225 The PL310 L2 cache controller implements three types of Clean &
1226 Invalidate maintenance operations: by Physical Address
1227 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1228 They are architecturally defined to behave as the execution of a
1229 clean operation followed immediately by an invalidate operation,
1230 both performing to the same memory location. This functionality
1231 is not correctly implemented in PL310 as clean lines are not
1232 invalidated as a result of these operations.
1234 config ARM_ERRATA_720789
1235 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1236 depends on CPU_V7 && SMP
1238 This option enables the workaround for the 720789 Cortex-A9 (prior to
1239 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1240 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1241 As a consequence of this erratum, some TLB entries which should be
1242 invalidated are not, resulting in an incoherency in the system page
1243 tables. The workaround changes the TLB flushing routines to invalidate
1244 entries regardless of the ASID.
1246 config PL310_ERRATA_727915
1247 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1248 depends on CACHE_L2X0
1250 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1251 operation (offset 0x7FC). This operation runs in background so that
1252 PL310 can handle normal accesses while it is in progress. Under very
1253 rare circumstances, due to this erratum, write data can be lost when
1254 PL310 treats a cacheable write transaction during a Clean &
1255 Invalidate by Way operation.
1257 config ARM_ERRATA_743622
1258 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1261 This option enables the workaround for the 743622 Cortex-A9
1262 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1263 optimisation in the Cortex-A9 Store Buffer may lead to data
1264 corruption. This workaround sets a specific bit in the diagnostic
1265 register of the Cortex-A9 which disables the Store Buffer
1266 optimisation, preventing the defect from occurring. This has no
1267 visible impact on the overall performance or power consumption of the
1270 config ARM_ERRATA_751472
1271 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1272 depends on CPU_V7 && SMP
1274 This option enables the workaround for the 751472 Cortex-A9 (prior
1275 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1276 completion of a following broadcasted operation if the second
1277 operation is received by a CPU before the ICIALLUIS has completed,
1278 potentially leading to corrupted entries in the cache or TLB.
1280 config ARM_ERRATA_753970
1281 bool "ARM errata: cache sync operation may be faulty"
1282 depends on CACHE_PL310
1284 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1286 Under some condition the effect of cache sync operation on
1287 the store buffer still remains when the operation completes.
1288 This means that the store buffer is always asked to drain and
1289 this prevents it from merging any further writes. The workaround
1290 is to replace the normal offset of cache sync operation (0x730)
1291 by another offset targeting an unmapped PL310 register 0x740.
1292 This has the same effect as the cache sync operation: store buffer
1293 drain and waiting for all buffers empty.
1295 config ARM_ERRATA_754322
1296 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1299 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1300 r3p*) erratum. A speculative memory access may cause a page table walk
1301 which starts prior to an ASID switch but completes afterwards. This
1302 can populate the micro-TLB with a stale entry which may be hit with
1303 the new ASID. This workaround places two dsb instructions in the mm
1304 switching code so that no page table walks can cross the ASID switch.
1306 config ARM_ERRATA_754327
1307 bool "ARM errata: no automatic Store Buffer drain"
1308 depends on CPU_V7 && SMP
1310 This option enables the workaround for the 754327 Cortex-A9 (prior to
1311 r2p0) erratum. The Store Buffer does not have any automatic draining
1312 mechanism and therefore a livelock may occur if an external agent
1313 continuously polls a memory location waiting to observe an update.
1314 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1315 written polling loops from denying visibility of updates to memory.
1317 config ARM_ERRATA_364296
1318 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1319 depends on CPU_V6 && !SMP
1321 This options enables the workaround for the 364296 ARM1136
1322 r0p2 erratum (possible cache data corruption with
1323 hit-under-miss enabled). It sets the undocumented bit 31 in
1324 the auxiliary control register and the FI bit in the control
1325 register, thus disabling hit-under-miss without putting the
1326 processor into full low interrupt latency mode. ARM11MPCore
1329 config ARM_ERRATA_764369
1330 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1331 depends on CPU_V7 && SMP
1333 This option enables the workaround for erratum 764369
1334 affecting Cortex-A9 MPCore with two or more processors (all
1335 current revisions). Under certain timing circumstances, a data
1336 cache line maintenance operation by MVA targeting an Inner
1337 Shareable memory region may fail to proceed up to either the
1338 Point of Coherency or to the Point of Unification of the
1339 system. This workaround adds a DSB instruction before the
1340 relevant cache maintenance functions and sets a specific bit
1341 in the diagnostic control register of the SCU.
1345 source "arch/arm/common/Kconfig"
1355 Find out whether you have ISA slots on your motherboard. ISA is the
1356 name of a bus system, i.e. the way the CPU talks to the other stuff
1357 inside your box. Other bus systems are PCI, EISA, MicroChannel
1358 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1359 newer boards don't support it. If you have ISA, say Y, otherwise N.
1361 # Select ISA DMA controller support
1366 # Select ISA DMA interface
1371 bool "PCI support" if MIGHT_HAVE_PCI
1373 Find out whether you have a PCI motherboard. PCI is the name of a
1374 bus system, i.e. the way the CPU talks to the other stuff inside
1375 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1376 VESA. If you have PCI, say Y, otherwise N.
1382 config PCI_NANOENGINE
1383 bool "BSE nanoEngine PCI support"
1384 depends on SA1100_NANOENGINE
1386 Enable PCI on the BSE nanoEngine board.
1391 # Select the host bridge type
1392 config PCI_HOST_VIA82C505
1394 depends on PCI && ARCH_SHARK
1397 config PCI_HOST_ITE8152
1399 depends on PCI && MACH_ARMCORE
1403 source "drivers/pci/Kconfig"
1405 source "drivers/pcmcia/Kconfig"
1409 menu "Kernel Features"
1411 source "kernel/time/Kconfig"
1414 bool "Symmetric Multi-Processing"
1415 depends on CPU_V6K || CPU_V7
1416 depends on GENERIC_CLOCKEVENTS
1417 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1418 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1419 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1420 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE || ARCH_HIGHBANK
1421 select USE_GENERIC_SMP_HELPERS
1422 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1424 This enables support for systems with more than one CPU. If you have
1425 a system with only one CPU, like most personal computers, say N. If
1426 you have a system with more than one CPU, say Y.
1428 If you say N here, the kernel will run on single and multiprocessor
1429 machines, but will use only one CPU of a multiprocessor machine. If
1430 you say Y here, the kernel will run on many, but not all, single
1431 processor machines. On a single processor machine, the kernel will
1432 run faster if you say N here.
1434 See also <file:Documentation/i386/IO-APIC.txt>,
1435 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1436 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1438 If you don't know what to do here, say N.
1441 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1442 depends on EXPERIMENTAL
1443 depends on SMP && !XIP_KERNEL
1446 SMP kernels contain instructions which fail on non-SMP processors.
1447 Enabling this option allows the kernel to modify itself to make
1448 these instructions safe. Disabling it allows about 1K of space
1451 If you don't know what to do here, say Y.
1453 config ARM_CPU_TOPOLOGY
1454 bool "Support cpu topology definition"
1455 depends on SMP && CPU_V7
1458 Support ARM cpu topology definition. The MPIDR register defines
1459 affinity between processors which is then used to describe the cpu
1460 topology of an ARM System.
1463 bool "Multi-core scheduler support"
1464 depends on ARM_CPU_TOPOLOGY
1466 Multi-core scheduler support improves the CPU scheduler's decision
1467 making when dealing with multi-core CPU chips at a cost of slightly
1468 increased overhead in some places. If unsure say N here.
1471 bool "SMT scheduler support"
1472 depends on ARM_CPU_TOPOLOGY
1474 Improves the CPU scheduler's decision making when dealing with
1475 MultiThreading at a cost of slightly increased overhead in some
1476 places. If unsure say N here.
1481 This option enables support for the ARM system coherency unit
1488 This options enables support for the ARM timer and watchdog unit
1491 prompt "Memory split"
1494 Select the desired split between kernel and user memory.
1496 If you are not absolutely sure what you are doing, leave this
1500 bool "3G/1G user/kernel split"
1502 bool "2G/2G user/kernel split"
1504 bool "1G/3G user/kernel split"
1509 default 0x40000000 if VMSPLIT_1G
1510 default 0x80000000 if VMSPLIT_2G
1514 int "Maximum number of CPUs (2-32)"
1520 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1521 depends on SMP && HOTPLUG && EXPERIMENTAL
1523 Say Y here to experiment with turning CPUs off and on. CPUs
1524 can be controlled through /sys/devices/system/cpu.
1527 bool "Use local timer interrupts"
1530 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1532 Enable support for local timers on SMP platforms, rather then the
1533 legacy IPI broadcast method. Local timers allows the system
1534 accounting to be spread across the timer interval, preventing a
1535 "thundering herd" at every timer tick.
1537 source kernel/Kconfig.preempt
1541 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1542 ARCH_S5PV210 || ARCH_EXYNOS4
1543 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1544 default AT91_TIMER_HZ if ARCH_AT91
1545 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1548 config THUMB2_KERNEL
1549 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1550 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1552 select ARM_ASM_UNIFIED
1554 By enabling this option, the kernel will be compiled in
1555 Thumb-2 mode. A compiler/assembler that understand the unified
1556 ARM-Thumb syntax is needed.
1560 config THUMB2_AVOID_R_ARM_THM_JUMP11
1561 bool "Work around buggy Thumb-2 short branch relocations in gas"
1562 depends on THUMB2_KERNEL && MODULES
1565 Various binutils versions can resolve Thumb-2 branches to
1566 locally-defined, preemptible global symbols as short-range "b.n"
1567 branch instructions.
1569 This is a problem, because there's no guarantee the final
1570 destination of the symbol, or any candidate locations for a
1571 trampoline, are within range of the branch. For this reason, the
1572 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1573 relocation in modules at all, and it makes little sense to add
1576 The symptom is that the kernel fails with an "unsupported
1577 relocation" error when loading some modules.
1579 Until fixed tools are available, passing
1580 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1581 code which hits this problem, at the cost of a bit of extra runtime
1582 stack usage in some cases.
1584 The problem is described in more detail at:
1585 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1587 Only Thumb-2 kernels are affected.
1589 Unless you are sure your tools don't have this problem, say Y.
1591 config ARM_ASM_UNIFIED
1595 bool "Use the ARM EABI to compile the kernel"
1597 This option allows for the kernel to be compiled using the latest
1598 ARM ABI (aka EABI). This is only useful if you are using a user
1599 space environment that is also compiled with EABI.
1601 Since there are major incompatibilities between the legacy ABI and
1602 EABI, especially with regard to structure member alignment, this
1603 option also changes the kernel syscall calling convention to
1604 disambiguate both ABIs and allow for backward compatibility support
1605 (selected with CONFIG_OABI_COMPAT).
1607 To use this you need GCC version 4.0.0 or later.
1610 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1611 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1614 This option preserves the old syscall interface along with the
1615 new (ARM EABI) one. It also provides a compatibility layer to
1616 intercept syscalls that have structure arguments which layout
1617 in memory differs between the legacy ABI and the new ARM EABI
1618 (only for non "thumb" binaries). This option adds a tiny
1619 overhead to all syscalls and produces a slightly larger kernel.
1620 If you know you'll be using only pure EABI user space then you
1621 can say N here. If this option is not selected and you attempt
1622 to execute a legacy ABI binary then the result will be
1623 UNPREDICTABLE (in fact it can be predicted that it won't work
1624 at all). If in doubt say Y.
1626 config ARCH_HAS_HOLES_MEMORYMODEL
1629 config ARCH_SPARSEMEM_ENABLE
1632 config ARCH_SPARSEMEM_DEFAULT
1633 def_bool ARCH_SPARSEMEM_ENABLE
1635 config ARCH_SELECT_MEMORY_MODEL
1636 def_bool ARCH_SPARSEMEM_ENABLE
1638 config HAVE_ARCH_PFN_VALID
1639 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1642 bool "High Memory Support"
1645 The address space of ARM processors is only 4 Gigabytes large
1646 and it has to accommodate user address space, kernel address
1647 space as well as some memory mapped IO. That means that, if you
1648 have a large amount of physical memory and/or IO, not all of the
1649 memory can be "permanently mapped" by the kernel. The physical
1650 memory that is not permanently mapped is called "high memory".
1652 Depending on the selected kernel/user memory split, minimum
1653 vmalloc space and actual amount of RAM, you may not need this
1654 option which should result in a slightly faster kernel.
1659 bool "Allocate 2nd-level pagetables from highmem"
1662 config HW_PERF_EVENTS
1663 bool "Enable hardware performance counter support for perf events"
1664 depends on PERF_EVENTS && CPU_HAS_PMU
1667 Enable hardware performance counter support for perf events. If
1668 disabled, perf events will use software events only.
1672 config FORCE_MAX_ZONEORDER
1673 int "Maximum zone order" if ARCH_SHMOBILE
1674 range 11 64 if ARCH_SHMOBILE
1675 default "9" if SA1111
1678 The kernel memory allocator divides physically contiguous memory
1679 blocks into "zones", where each zone is a power of two number of
1680 pages. This option selects the largest power of two that the kernel
1681 keeps in the memory allocator. If you need to allocate very large
1682 blocks of physically contiguous memory, then you may need to
1683 increase this value.
1685 This config option is actually maximum order plus one. For example,
1686 a value of 11 means that the largest free memory block is 2^10 pages.
1689 bool "Timer and CPU usage LEDs"
1690 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1691 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1692 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1693 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1694 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1695 ARCH_AT91 || ARCH_DAVINCI || \
1696 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1698 If you say Y here, the LEDs on your machine will be used
1699 to provide useful information about your current system status.
1701 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1702 be able to select which LEDs are active using the options below. If
1703 you are compiling a kernel for the EBSA-110 or the LART however, the
1704 red LED will simply flash regularly to indicate that the system is
1705 still functional. It is safe to say Y here if you have a CATS
1706 system, but the driver will do nothing.
1709 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1710 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1711 || MACH_OMAP_PERSEUS2
1713 depends on !GENERIC_CLOCKEVENTS
1714 default y if ARCH_EBSA110
1716 If you say Y here, one of the system LEDs (the green one on the
1717 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1718 will flash regularly to indicate that the system is still
1719 operational. This is mainly useful to kernel hackers who are
1720 debugging unstable kernels.
1722 The LART uses the same LED for both Timer LED and CPU usage LED
1723 functions. You may choose to use both, but the Timer LED function
1724 will overrule the CPU usage LED.
1727 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1729 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1730 || MACH_OMAP_PERSEUS2
1733 If you say Y here, the red LED will be used to give a good real
1734 time indication of CPU usage, by lighting whenever the idle task
1735 is not currently executing.
1737 The LART uses the same LED for both Timer LED and CPU usage LED
1738 functions. You may choose to use both, but the Timer LED function
1739 will overrule the CPU usage LED.
1741 config ALIGNMENT_TRAP
1743 depends on CPU_CP15_MMU
1744 default y if !ARCH_EBSA110
1745 select HAVE_PROC_CPU if PROC_FS
1747 ARM processors cannot fetch/store information which is not
1748 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1749 address divisible by 4. On 32-bit ARM processors, these non-aligned
1750 fetch/store instructions will be emulated in software if you say
1751 here, which has a severe performance impact. This is necessary for
1752 correct operation of some network protocols. With an IP-only
1753 configuration it is safe to say N, otherwise say Y.
1755 config UACCESS_WITH_MEMCPY
1756 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1757 depends on MMU && EXPERIMENTAL
1758 default y if CPU_FEROCEON
1760 Implement faster copy_to_user and clear_user methods for CPU
1761 cores where a 8-word STM instruction give significantly higher
1762 memory write throughput than a sequence of individual 32bit stores.
1764 A possible side effect is a slight increase in scheduling latency
1765 between threads sharing the same address space if they invoke
1766 such copy operations with large buffers.
1768 However, if the CPU data cache is using a write-allocate mode,
1769 this option is unlikely to provide any performance gain.
1773 prompt "Enable seccomp to safely compute untrusted bytecode"
1775 This kernel feature is useful for number crunching applications
1776 that may need to compute untrusted bytecode during their
1777 execution. By using pipes or other transports made available to
1778 the process as file descriptors supporting the read/write
1779 syscalls, it's possible to isolate those applications in
1780 their own address space using seccomp. Once seccomp is
1781 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1782 and the task is only allowed to execute a few safe syscalls
1783 defined by each seccomp mode.
1785 config CC_STACKPROTECTOR
1786 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1787 depends on EXPERIMENTAL
1789 This option turns on the -fstack-protector GCC feature. This
1790 feature puts, at the beginning of functions, a canary value on
1791 the stack just before the return address, and validates
1792 the value just before actually returning. Stack based buffer
1793 overflows (that need to overwrite this return address) now also
1794 overwrite the canary, which gets detected and the attack is then
1795 neutralized via a kernel panic.
1796 This feature requires gcc version 4.2 or above.
1798 config DEPRECATED_PARAM_STRUCT
1799 bool "Provide old way to pass kernel parameters"
1801 This was deprecated in 2001 and announced to live on for 5 years.
1802 Some old boot loaders still use this way.
1809 bool "Flattened Device Tree support"
1811 select OF_EARLY_FLATTREE
1814 Include support for flattened device tree machine descriptions.
1816 # Compressed boot loader in ROM. Yes, we really want to ask about
1817 # TEXT and BSS so we preserve their values in the config files.
1818 config ZBOOT_ROM_TEXT
1819 hex "Compressed ROM boot loader base address"
1822 The physical address at which the ROM-able zImage is to be
1823 placed in the target. Platforms which normally make use of
1824 ROM-able zImage formats normally set this to a suitable
1825 value in their defconfig file.
1827 If ZBOOT_ROM is not enabled, this has no effect.
1829 config ZBOOT_ROM_BSS
1830 hex "Compressed ROM boot loader BSS address"
1833 The base address of an area of read/write memory in the target
1834 for the ROM-able zImage which must be available while the
1835 decompressor is running. It must be large enough to hold the
1836 entire decompressed kernel plus an additional 128 KiB.
1837 Platforms which normally make use of ROM-able zImage formats
1838 normally set this to a suitable value in their defconfig file.
1840 If ZBOOT_ROM is not enabled, this has no effect.
1843 bool "Compressed boot loader in ROM/flash"
1844 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1846 Say Y here if you intend to execute your compressed kernel image
1847 (zImage) directly from ROM or flash. If unsure, say N.
1850 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1851 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1852 default ZBOOT_ROM_NONE
1854 Include experimental SD/MMC loading code in the ROM-able zImage.
1855 With this enabled it is possible to write the the ROM-able zImage
1856 kernel image to an MMC or SD card and boot the kernel straight
1857 from the reset vector. At reset the processor Mask ROM will load
1858 the first part of the the ROM-able zImage which in turn loads the
1859 rest the kernel image to RAM.
1861 config ZBOOT_ROM_NONE
1862 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1864 Do not load image from SD or MMC
1866 config ZBOOT_ROM_MMCIF
1867 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1869 Load image from MMCIF hardware block.
1871 config ZBOOT_ROM_SH_MOBILE_SDHI
1872 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1874 Load image from SDHI hardware block
1878 config ARM_APPENDED_DTB
1879 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1880 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1882 With this option, the boot code will look for a device tree binary
1883 (DTB) appended to zImage
1884 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1886 This is meant as a backward compatibility convenience for those
1887 systems with a bootloader that can't be upgraded to accommodate
1888 the documented boot protocol using a device tree.
1890 Beware that there is very little in terms of protection against
1891 this option being confused by leftover garbage in memory that might
1892 look like a DTB header after a reboot if no actual DTB is appended
1893 to zImage. Do not leave this option active in a production kernel
1894 if you don't intend to always append a DTB. Proper passing of the
1895 location into r2 of a bootloader provided DTB is always preferable
1898 config ARM_ATAG_DTB_COMPAT
1899 bool "Supplement the appended DTB with traditional ATAG information"
1900 depends on ARM_APPENDED_DTB
1902 Some old bootloaders can't be updated to a DTB capable one, yet
1903 they provide ATAGs with memory configuration, the ramdisk address,
1904 the kernel cmdline string, etc. Such information is dynamically
1905 provided by the bootloader and can't always be stored in a static
1906 DTB. To allow a device tree enabled kernel to be used with such
1907 bootloaders, this option allows zImage to extract the information
1908 from the ATAG list and store it at run time into the appended DTB.
1911 string "Default kernel command string"
1914 On some architectures (EBSA110 and CATS), there is currently no way
1915 for the boot loader to pass arguments to the kernel. For these
1916 architectures, you should supply some command-line options at build
1917 time by entering them here. As a minimum, you should specify the
1918 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1921 prompt "Kernel command line type" if CMDLINE != ""
1922 default CMDLINE_FROM_BOOTLOADER
1924 config CMDLINE_FROM_BOOTLOADER
1925 bool "Use bootloader kernel arguments if available"
1927 Uses the command-line options passed by the boot loader. If
1928 the boot loader doesn't provide any, the default kernel command
1929 string provided in CMDLINE will be used.
1931 config CMDLINE_EXTEND
1932 bool "Extend bootloader kernel arguments"
1934 The command-line arguments provided by the boot loader will be
1935 appended to the default kernel command string.
1937 config CMDLINE_FORCE
1938 bool "Always use the default kernel command string"
1940 Always use the default kernel command string, even if the boot
1941 loader passes other arguments to the kernel.
1942 This is useful if you cannot or don't want to change the
1943 command-line options your boot loader passes to the kernel.
1947 bool "Kernel Execute-In-Place from ROM"
1948 depends on !ZBOOT_ROM
1950 Execute-In-Place allows the kernel to run from non-volatile storage
1951 directly addressable by the CPU, such as NOR flash. This saves RAM
1952 space since the text section of the kernel is not loaded from flash
1953 to RAM. Read-write sections, such as the data section and stack,
1954 are still copied to RAM. The XIP kernel is not compressed since
1955 it has to run directly from flash, so it will take more space to
1956 store it. The flash address used to link the kernel object files,
1957 and for storing it, is configuration dependent. Therefore, if you
1958 say Y here, you must know the proper physical address where to
1959 store the kernel image depending on your own flash memory usage.
1961 Also note that the make target becomes "make xipImage" rather than
1962 "make zImage" or "make Image". The final kernel binary to put in
1963 ROM memory will be arch/arm/boot/xipImage.
1967 config XIP_PHYS_ADDR
1968 hex "XIP Kernel Physical Location"
1969 depends on XIP_KERNEL
1970 default "0x00080000"
1972 This is the physical address in your flash memory the kernel will
1973 be linked for and stored to. This address is dependent on your
1977 bool "Kexec system call (EXPERIMENTAL)"
1978 depends on EXPERIMENTAL
1980 kexec is a system call that implements the ability to shutdown your
1981 current kernel, and to start another kernel. It is like a reboot
1982 but it is independent of the system firmware. And like a reboot
1983 you can start any kernel with it, not just Linux.
1985 It is an ongoing process to be certain the hardware in a machine
1986 is properly shutdown, so do not be surprised if this code does not
1987 initially work for you. It may help to enable device hotplugging
1991 bool "Export atags in procfs"
1995 Should the atags used to boot the kernel be exported in an "atags"
1996 file in procfs. Useful with kexec.
1999 bool "Build kdump crash kernel (EXPERIMENTAL)"
2000 depends on EXPERIMENTAL
2002 Generate crash dump after being started by kexec. This should
2003 be normally only set in special crash dump kernels which are
2004 loaded in the main kernel with kexec-tools into a specially
2005 reserved region and then later executed after a crash by
2006 kdump/kexec. The crash dump kernel must be compiled to a
2007 memory address not used by the main kernel
2009 For more details see Documentation/kdump/kdump.txt
2011 config AUTO_ZRELADDR
2012 bool "Auto calculation of the decompressed kernel image address"
2013 depends on !ZBOOT_ROM && !ARCH_U300
2015 ZRELADDR is the physical address where the decompressed kernel
2016 image will be placed. If AUTO_ZRELADDR is selected, the address
2017 will be determined at run-time by masking the current IP with
2018 0xf8000000. This assumes the zImage being placed in the first 128MB
2019 from start of memory.
2023 menu "CPU Power Management"
2027 source "drivers/cpufreq/Kconfig"
2030 tristate "CPUfreq driver for i.MX CPUs"
2031 depends on ARCH_MXC && CPU_FREQ
2033 This enables the CPUfreq driver for i.MX CPUs.
2035 config CPU_FREQ_SA1100
2038 config CPU_FREQ_SA1110
2041 config CPU_FREQ_INTEGRATOR
2042 tristate "CPUfreq driver for ARM Integrator CPUs"
2043 depends on ARCH_INTEGRATOR && CPU_FREQ
2046 This enables the CPUfreq driver for ARM Integrator CPUs.
2048 For details, take a look at <file:Documentation/cpu-freq>.
2054 depends on CPU_FREQ && ARCH_PXA && PXA25x
2056 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2061 Internal configuration node for common cpufreq on Samsung SoC
2063 config CPU_FREQ_S3C24XX
2064 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2065 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
2068 This enables the CPUfreq driver for the Samsung S3C24XX family
2071 For details, take a look at <file:Documentation/cpu-freq>.
2075 config CPU_FREQ_S3C24XX_PLL
2076 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2077 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2079 Compile in support for changing the PLL frequency from the
2080 S3C24XX series CPUfreq driver. The PLL takes time to settle
2081 after a frequency change, so by default it is not enabled.
2083 This also means that the PLL tables for the selected CPU(s) will
2084 be built which may increase the size of the kernel image.
2086 config CPU_FREQ_S3C24XX_DEBUG
2087 bool "Debug CPUfreq Samsung driver core"
2088 depends on CPU_FREQ_S3C24XX
2090 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2092 config CPU_FREQ_S3C24XX_IODEBUG
2093 bool "Debug CPUfreq Samsung driver IO timing"
2094 depends on CPU_FREQ_S3C24XX
2096 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2098 config CPU_FREQ_S3C24XX_DEBUGFS
2099 bool "Export debugfs for CPUFreq"
2100 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2102 Export status information via debugfs.
2106 source "drivers/cpuidle/Kconfig"
2110 menu "Floating point emulation"
2112 comment "At least one emulation must be selected"
2115 bool "NWFPE math emulation"
2116 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2118 Say Y to include the NWFPE floating point emulator in the kernel.
2119 This is necessary to run most binaries. Linux does not currently
2120 support floating point hardware so you need to say Y here even if
2121 your machine has an FPA or floating point co-processor podule.
2123 You may say N here if you are going to load the Acorn FPEmulator
2124 early in the bootup.
2127 bool "Support extended precision"
2128 depends on FPE_NWFPE
2130 Say Y to include 80-bit support in the kernel floating-point
2131 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2132 Note that gcc does not generate 80-bit operations by default,
2133 so in most cases this option only enlarges the size of the
2134 floating point emulator without any good reason.
2136 You almost surely want to say N here.
2139 bool "FastFPE math emulation (EXPERIMENTAL)"
2140 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2142 Say Y here to include the FAST floating point emulator in the kernel.
2143 This is an experimental much faster emulator which now also has full
2144 precision for the mantissa. It does not support any exceptions.
2145 It is very simple, and approximately 3-6 times faster than NWFPE.
2147 It should be sufficient for most programs. It may be not suitable
2148 for scientific calculations, but you have to check this for yourself.
2149 If you do not feel you need a faster FP emulation you should better
2153 bool "VFP-format floating point maths"
2154 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2156 Say Y to include VFP support code in the kernel. This is needed
2157 if your hardware includes a VFP unit.
2159 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2160 release notes and additional status information.
2162 Say N if your target does not have VFP hardware.
2170 bool "Advanced SIMD (NEON) Extension support"
2171 depends on VFPv3 && CPU_V7
2173 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2178 menu "Userspace binary formats"
2180 source "fs/Kconfig.binfmt"
2183 tristate "RISC OS personality"
2186 Say Y here to include the kernel code necessary if you want to run
2187 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2188 experimental; if this sounds frightening, say N and sleep in peace.
2189 You can also say M here to compile this support as a module (which
2190 will be called arthur).
2194 menu "Power management options"
2196 source "kernel/power/Kconfig"
2198 config ARCH_SUSPEND_POSSIBLE
2199 depends on !ARCH_S5P64X0 && !ARCH_S5PC100
2200 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2201 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2206 source "net/Kconfig"
2208 source "drivers/Kconfig"
2212 source "arch/arm/Kconfig.debug"
2214 source "security/Kconfig"
2216 source "crypto/Kconfig"
2218 source "lib/Kconfig"