4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_MIGHT_HAVE_PC_PARPORT
9 select ARCH_SUPPORTS_ATOMIC_RMW
10 select ARCH_USE_BUILTIN_BSWAP
11 select ARCH_USE_CMPXCHG_LOCKREF
12 select ARCH_WANT_IPC_PARSE_VERSION
13 select BUILDTIME_EXTABLE_SORT if MMU
14 select CLONE_BACKWARDS
15 select CPU_PM if (SUSPEND || CPU_IDLE)
16 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
17 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
18 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
19 select GENERIC_IDLE_POLL_SETUP
20 select GENERIC_IRQ_PROBE
21 select GENERIC_IRQ_SHOW
22 select GENERIC_PCI_IOMAP
23 select GENERIC_SCHED_CLOCK
24 select GENERIC_SMP_IDLE_THREAD
25 select GENERIC_STRNCPY_FROM_USER
26 select GENERIC_STRNLEN_USER
27 select HARDIRQS_SW_RESEND
28 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
29 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
31 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
32 select HAVE_ARCH_TRACEHOOK
34 select HAVE_CC_STACKPROTECTOR
35 select HAVE_CONTEXT_TRACKING
36 select HAVE_C_RECORDMCOUNT
37 select HAVE_DEBUG_KMEMLEAK
38 select HAVE_DMA_API_DEBUG
40 select HAVE_DMA_CONTIGUOUS if MMU
41 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
42 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
43 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
44 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
45 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
46 select HAVE_GENERIC_DMA_COHERENT
47 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
48 select HAVE_IDE if PCI || ISA || PCMCIA
49 select HAVE_IRQ_TIME_ACCOUNTING
50 select HAVE_KERNEL_GZIP
51 select HAVE_KERNEL_LZ4
52 select HAVE_KERNEL_LZMA
53 select HAVE_KERNEL_LZO
55 select HAVE_KPROBES if !XIP_KERNEL
56 select HAVE_KRETPROBES if (HAVE_KPROBES)
58 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
59 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
60 select HAVE_PERF_EVENTS
62 select HAVE_PERF_USER_STACK_DUMP
63 select HAVE_REGS_AND_STACK_ACCESS_API
64 select HAVE_SYSCALL_TRACEPOINTS
66 select HAVE_VIRT_CPU_ACCOUNTING_GEN
67 select IRQ_FORCED_THREADING
68 select MODULES_USE_ELF_REL
71 select OLD_SIGSUSPEND3
72 select PERF_USE_VMALLOC
74 select SYS_SUPPORTS_APM_EMULATION
75 # Above selects are sorted alphabetically; please add new ones
76 # according to that. Thanks.
78 The ARM series is a line of low-power-consumption RISC chip designs
79 licensed by ARM Ltd and targeted at embedded applications and
80 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
81 manufactured, but legacy ARM-based PC hardware remains popular in
82 Europe. There is an ARM Linux project with a web page at
83 <http://www.arm.linux.org.uk/>.
85 config ARM_HAS_SG_CHAIN
88 config NEED_SG_DMA_LENGTH
91 config ARM_DMA_USE_IOMMU
93 select ARM_HAS_SG_CHAIN
94 select NEED_SG_DMA_LENGTH
98 config ARM_DMA_IOMMU_ALIGNMENT
99 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
103 DMA mapping framework by default aligns all buffers to the smallest
104 PAGE_SIZE order which is greater than or equal to the requested buffer
105 size. This works well for buffers up to a few hundreds kilobytes, but
106 for larger buffers it just a waste of address space. Drivers which has
107 relatively small addressing window (like 64Mib) might run out of
108 virtual space with just a few allocations.
110 With this parameter you can specify the maximum PAGE_SIZE order for
111 DMA IOMMU buffers. Larger buffers will be aligned only to this
112 specified order. The order is expressed as a power of two multiplied
117 config MIGHT_HAVE_PCI
120 config SYS_SUPPORTS_APM_EMULATION
125 select GENERIC_ALLOCATOR
136 The Extended Industry Standard Architecture (EISA) bus was
137 developed as an open alternative to the IBM MicroChannel bus.
139 The EISA bus provided some of the features of the IBM MicroChannel
140 bus while maintaining backward compatibility with cards made for
141 the older ISA bus. The EISA bus saw limited use between 1988 and
142 1995 when it was made obsolete by the PCI bus.
144 Say Y here if you are building a kernel for an EISA-based machine.
151 config STACKTRACE_SUPPORT
155 config HAVE_LATENCYTOP_SUPPORT
160 config LOCKDEP_SUPPORT
164 config TRACE_IRQFLAGS_SUPPORT
168 config RWSEM_XCHGADD_ALGORITHM
172 config ARCH_HAS_ILOG2_U32
175 config ARCH_HAS_ILOG2_U64
178 config ARCH_HAS_BANDGAP
181 config GENERIC_HWEIGHT
185 config GENERIC_CALIBRATE_DELAY
189 config ARCH_MAY_HAVE_PC_FDC
195 config NEED_DMA_MAP_STATE
198 config ARCH_SUPPORTS_UPROBES
201 config ARCH_HAS_DMA_SET_COHERENT_MASK
204 config GENERIC_ISA_DMA
210 config NEED_RET_TO_USER
218 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
219 default DRAM_BASE if REMAP_VECTORS_TO_RAM
222 The base address of exception vectors. This must be two pages
225 config ARM_PATCH_PHYS_VIRT
226 bool "Patch physical to virtual translations at runtime" if EMBEDDED
228 depends on !XIP_KERNEL && MMU
229 depends on !ARCH_REALVIEW || !SPARSEMEM
231 Patch phys-to-virt and virt-to-phys translation functions at
232 boot and module load time according to the position of the
233 kernel in system memory.
235 This can only be used with non-XIP MMU kernels where the base
236 of physical memory is at a 16MB boundary.
238 Only disable this option if you know that you do not require
239 this feature (eg, building a kernel for a single machine) and
240 you need to shrink the kernel to the minimal size.
242 config NEED_MACH_GPIO_H
245 Select this when mach/gpio.h is required to provide special
246 definitions for this platform. The need for mach/gpio.h should
247 be avoided when possible.
249 config NEED_MACH_IO_H
252 Select this when mach/io.h is required to provide special
253 definitions for this platform. The need for mach/io.h should
254 be avoided when possible.
256 config NEED_MACH_MEMORY_H
259 Select this when mach/memory.h is required to provide special
260 definitions for this platform. The need for mach/memory.h should
261 be avoided when possible.
264 hex "Physical address of main memory" if MMU
265 depends on !ARM_PATCH_PHYS_VIRT
266 default DRAM_BASE if !MMU
267 default 0x00000000 if ARCH_EBSA110 || \
268 EP93XX_SDCE3_SYNC_PHYS_OFFSET || \
273 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
274 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
275 default 0x20000000 if ARCH_S5PV210
276 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
277 default 0xc0000000 if EP93XX_SDCE0_PHYS_OFFSET || ARCH_SA1100
278 default 0xd0000000 if EP93XX_SDCE1_PHYS_OFFSET
279 default 0xe0000000 if EP93XX_SDCE2_PHYS_OFFSET
280 default 0xf0000000 if EP93XX_SDCE3_ASYNC_PHYS_OFFSET
282 Please provide the physical address corresponding to the
283 location of main memory in your system.
289 source "init/Kconfig"
291 source "kernel/Kconfig.freezer"
296 bool "MMU-based Paged Memory Management Support"
299 Select if you want MMU-based virtualised addressing space
300 support by paged memory management. If unsure, say 'Y'.
303 # The "ARM system type" choice list is ordered alphabetically by option
304 # text. Please add new entries in the option alphabetic order.
307 prompt "ARM system type"
308 default ARCH_VERSATILE if !MMU
309 default ARCH_MULTIPLATFORM if MMU
311 config ARCH_MULTIPLATFORM
312 bool "Allow multiple platforms to be selected"
314 select ARCH_WANT_OPTIONAL_GPIOLIB
315 select ARM_HAS_SG_CHAIN
316 select ARM_PATCH_PHYS_VIRT
320 select GENERIC_CLOCKEVENTS
321 select MIGHT_HAVE_PCI
322 select MULTI_IRQ_HANDLER
326 config ARCH_INTEGRATOR
327 bool "ARM Ltd. Integrator family"
329 select ARM_PATCH_PHYS_VIRT if MMU
332 select COMMON_CLK_VERSATILE
333 select GENERIC_CLOCKEVENTS
336 select MULTI_IRQ_HANDLER
337 select NEED_MACH_MEMORY_H
338 select PLAT_VERSATILE
341 select VERSATILE_FPGA_IRQ
343 Support for ARM's Integrator platform.
346 bool "ARM Ltd. RealView family"
347 select ARCH_WANT_OPTIONAL_GPIOLIB
349 select ARM_TIMER_SP804
351 select COMMON_CLK_VERSATILE
352 select GENERIC_CLOCKEVENTS
353 select GPIO_PL061 if GPIOLIB
355 select NEED_MACH_MEMORY_H
356 select PLAT_VERSATILE
357 select PLAT_VERSATILE_CLCD
359 This enables support for ARM Ltd RealView boards.
361 config ARCH_VERSATILE
362 bool "ARM Ltd. Versatile family"
363 select ARCH_WANT_OPTIONAL_GPIOLIB
365 select ARM_TIMER_SP804
368 select GENERIC_CLOCKEVENTS
369 select HAVE_MACH_CLKDEV
371 select PLAT_VERSATILE
372 select PLAT_VERSATILE_CLCD
373 select PLAT_VERSATILE_CLOCK
374 select VERSATILE_FPGA_IRQ
376 This enables support for ARM Ltd Versatile board.
380 select ARCH_REQUIRE_GPIOLIB
383 select NEED_MACH_IO_H if PCCARD
385 select PINCTRL_AT91 if USE_OF
387 This enables support for systems based on Atmel
388 AT91RM9200 and AT91SAM9* processors.
391 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
392 select ARCH_REQUIRE_GPIOLIB
397 select GENERIC_CLOCKEVENTS
400 Support for Cirrus Logic 711x/721x/731x based boards.
403 bool "Cortina Systems Gemini"
404 select ARCH_REQUIRE_GPIOLIB
407 select GENERIC_CLOCKEVENTS
409 Support for the Cortina Systems Gemini family SoCs
413 select ARCH_USES_GETTIMEOFFSET
416 select NEED_MACH_IO_H
417 select NEED_MACH_MEMORY_H
420 This is an evaluation board for the StrongARM processor available
421 from Digital. It has limited hardware on-board, including an
422 Ethernet interface, two PCMCIA sockets, two serial ports and a
426 bool "Energy Micro efm32"
428 select ARCH_REQUIRE_GPIOLIB
434 select GENERIC_CLOCKEVENTS
440 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
445 select ARCH_HAS_HOLES_MEMORYMODEL
446 select ARCH_REQUIRE_GPIOLIB
447 select ARCH_USES_GETTIMEOFFSET
453 This enables support for the Cirrus EP93xx series of CPUs.
455 config ARCH_FOOTBRIDGE
459 select GENERIC_CLOCKEVENTS
461 select NEED_MACH_IO_H if !MMU
462 select NEED_MACH_MEMORY_H
464 Support for systems based on the DC21285 companion chip
465 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
468 bool "Hilscher NetX based"
472 select GENERIC_CLOCKEVENTS
474 This enables support for systems based on the Hilscher NetX Soc
480 select NEED_MACH_MEMORY_H
481 select NEED_RET_TO_USER
487 Support for Intel's IOP13XX (XScale) family of processors.
492 select ARCH_REQUIRE_GPIOLIB
495 select NEED_RET_TO_USER
499 Support for Intel's 80219 and IOP32X (XScale) family of
505 select ARCH_REQUIRE_GPIOLIB
508 select NEED_RET_TO_USER
512 Support for Intel's IOP33X (XScale) family of processors.
517 select ARCH_HAS_DMA_SET_COHERENT_MASK
518 select ARCH_REQUIRE_GPIOLIB
519 select ARCH_SUPPORTS_BIG_ENDIAN
522 select DMABOUNCE if PCI
523 select GENERIC_CLOCKEVENTS
524 select MIGHT_HAVE_PCI
525 select NEED_MACH_IO_H
526 select USB_EHCI_BIG_ENDIAN_DESC
527 select USB_EHCI_BIG_ENDIAN_MMIO
529 Support for Intel's IXP4XX (XScale) family of processors.
533 select ARCH_REQUIRE_GPIOLIB
535 select GENERIC_CLOCKEVENTS
536 select MIGHT_HAVE_PCI
540 select PLAT_ORION_LEGACY
542 Support for the Marvell Dove SoC 88AP510
545 bool "Marvell Kirkwood"
546 select ARCH_REQUIRE_GPIOLIB
548 select GENERIC_CLOCKEVENTS
553 select PINCTRL_KIRKWOOD
554 select PLAT_ORION_LEGACY
556 Support for the following Marvell Kirkwood series SoCs:
557 88F6180, 88F6192 and 88F6281.
560 bool "Marvell MV78xx0"
561 select ARCH_REQUIRE_GPIOLIB
563 select GENERIC_CLOCKEVENTS
566 select PLAT_ORION_LEGACY
568 Support for the following Marvell MV78xx0 series SoCs:
574 select ARCH_REQUIRE_GPIOLIB
576 select GENERIC_CLOCKEVENTS
579 select PLAT_ORION_LEGACY
581 Support for the following Marvell Orion 5x series SoCs:
582 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
583 Orion-2 (5281), Orion-1-90 (6183).
586 bool "Marvell PXA168/910/MMP2"
588 select ARCH_REQUIRE_GPIOLIB
590 select GENERIC_ALLOCATOR
591 select GENERIC_CLOCKEVENTS
594 select MULTI_IRQ_HANDLER
599 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
602 bool "Micrel/Kendin KS8695"
603 select ARCH_REQUIRE_GPIOLIB
606 select GENERIC_CLOCKEVENTS
607 select NEED_MACH_MEMORY_H
609 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
610 System-on-Chip devices.
613 bool "Nuvoton W90X900 CPU"
614 select ARCH_REQUIRE_GPIOLIB
618 select GENERIC_CLOCKEVENTS
620 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
621 At present, the w90x900 has been renamed nuc900, regarding
622 the ARM series product line, you can login the following
623 link address to know more.
625 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
626 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
630 select ARCH_REQUIRE_GPIOLIB
635 select GENERIC_CLOCKEVENTS
639 Support for the NXP LPC32XX family of processors
642 bool "PXA2xx/PXA3xx-based"
645 select ARCH_REQUIRE_GPIOLIB
646 select ARM_CPU_SUSPEND if PM
651 select GENERIC_CLOCKEVENTS
654 select MULTI_IRQ_HANDLER
658 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
661 bool "Qualcomm MSM (non-multiplatform)"
662 select ARCH_REQUIRE_GPIOLIB
664 select GENERIC_CLOCKEVENTS
666 Support for Qualcomm MSM/QSD based systems. This runs on the
667 apps processor of the MSM/QSD and depends on a shared memory
668 interface to the modem processor which runs the baseband
669 stack and controls some vital subsystems
670 (clock and power control, etc).
672 config ARCH_SHMOBILE_LEGACY
673 bool "Renesas ARM SoCs (non-multiplatform)"
675 select ARM_PATCH_PHYS_VIRT if MMU
677 select GENERIC_CLOCKEVENTS
678 select HAVE_ARM_SCU if SMP
679 select HAVE_ARM_TWD if SMP
680 select HAVE_MACH_CLKDEV
682 select MIGHT_HAVE_CACHE_L2X0
683 select MULTI_IRQ_HANDLER
686 select PM_GENERIC_DOMAINS if PM
689 Support for Renesas ARM SoC platforms using a non-multiplatform
690 kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
696 select ARCH_MAY_HAVE_PC_FDC
697 select ARCH_SPARSEMEM_ENABLE
698 select ARCH_USES_GETTIMEOFFSET
702 select HAVE_PATA_PLATFORM
704 select NEED_MACH_IO_H
705 select NEED_MACH_MEMORY_H
709 On the Acorn Risc-PC, Linux can support the internal IDE disk and
710 CD-ROM interface, serial and parallel port, and the floppy drive.
715 select ARCH_REQUIRE_GPIOLIB
716 select ARCH_SPARSEMEM_ENABLE
721 select GENERIC_CLOCKEVENTS
724 select NEED_MACH_MEMORY_H
727 Support for StrongARM 11x0 based boards.
730 bool "Samsung S3C24XX SoCs"
731 select ARCH_REQUIRE_GPIOLIB
734 select CLKSRC_SAMSUNG_PWM
735 select GENERIC_CLOCKEVENTS
737 select HAVE_S3C2410_I2C if I2C
738 select HAVE_S3C2410_WATCHDOG if WATCHDOG
739 select HAVE_S3C_RTC if RTC_CLASS
740 select MULTI_IRQ_HANDLER
741 select NEED_MACH_IO_H
744 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
745 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
746 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
747 Samsung SMDK2410 development board (and derivatives).
750 bool "Samsung S3C64XX"
751 select ARCH_REQUIRE_GPIOLIB
756 select CLKSRC_SAMSUNG_PWM
757 select COMMON_CLK_SAMSUNG
759 select GENERIC_CLOCKEVENTS
761 select HAVE_S3C2410_I2C if I2C
762 select HAVE_S3C2410_WATCHDOG if WATCHDOG
766 select PM_GENERIC_DOMAINS if PM
768 select S3C_GPIO_TRACK
770 select SAMSUNG_WAKEMASK
771 select SAMSUNG_WDT_RESET
773 Samsung S3C64XX series based systems
776 bool "Samsung S5P6440 S5P6450"
779 select CLKSRC_SAMSUNG_PWM
781 select GENERIC_CLOCKEVENTS
783 select HAVE_S3C2410_I2C if I2C
784 select HAVE_S3C2410_WATCHDOG if WATCHDOG
785 select HAVE_S3C_RTC if RTC_CLASS
786 select NEED_MACH_GPIO_H
788 select SAMSUNG_WDT_RESET
790 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
794 bool "Samsung S5PC100"
795 select ARCH_REQUIRE_GPIOLIB
798 select CLKSRC_SAMSUNG_PWM
800 select GENERIC_CLOCKEVENTS
802 select HAVE_S3C2410_I2C if I2C
803 select HAVE_S3C2410_WATCHDOG if WATCHDOG
804 select HAVE_S3C_RTC if RTC_CLASS
805 select NEED_MACH_GPIO_H
807 select SAMSUNG_WDT_RESET
809 Samsung S5PC100 series based systems
812 bool "Samsung S5PV210/S5PC110"
813 select ARCH_HAS_HOLES_MEMORYMODEL
814 select ARCH_SPARSEMEM_ENABLE
817 select CLKSRC_SAMSUNG_PWM
819 select GENERIC_CLOCKEVENTS
821 select HAVE_S3C2410_I2C if I2C
822 select HAVE_S3C2410_WATCHDOG if WATCHDOG
823 select HAVE_S3C_RTC if RTC_CLASS
824 select NEED_MACH_GPIO_H
825 select NEED_MACH_MEMORY_H
828 Samsung S5PV210/S5PC110 series based systems
832 select ARCH_HAS_HOLES_MEMORYMODEL
833 select ARCH_REQUIRE_GPIOLIB
835 select GENERIC_ALLOCATOR
836 select GENERIC_CLOCKEVENTS
837 select GENERIC_IRQ_CHIP
843 Support for TI's DaVinci platform.
848 select ARCH_HAS_HOLES_MEMORYMODEL
850 select ARCH_REQUIRE_GPIOLIB
853 select GENERIC_CLOCKEVENTS
854 select GENERIC_IRQ_CHIP
857 select NEED_MACH_IO_H if PCCARD
858 select NEED_MACH_MEMORY_H
860 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
864 menu "Multiple platform selection"
865 depends on ARCH_MULTIPLATFORM
867 comment "CPU Core family selection"
870 bool "ARMv4 based platforms (FA526)"
871 depends on !ARCH_MULTI_V6_V7
872 select ARCH_MULTI_V4_V5
875 config ARCH_MULTI_V4T
876 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
877 depends on !ARCH_MULTI_V6_V7
878 select ARCH_MULTI_V4_V5
879 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
880 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
881 CPU_ARM925T || CPU_ARM940T)
884 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
885 depends on !ARCH_MULTI_V6_V7
886 select ARCH_MULTI_V4_V5
887 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
888 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
889 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
891 config ARCH_MULTI_V4_V5
895 bool "ARMv6 based platforms (ARM11)"
896 select ARCH_MULTI_V6_V7
900 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
902 select ARCH_MULTI_V6_V7
906 config ARCH_MULTI_V6_V7
908 select MIGHT_HAVE_CACHE_L2X0
910 config ARCH_MULTI_CPU_AUTO
911 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
917 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
921 select HAVE_ARM_ARCH_TIMER
924 # This is sorted alphabetically by mach-* pathname. However, plat-*
925 # Kconfigs may be included either alphabetically (according to the
926 # plat- suffix) or along side the corresponding mach-* source.
928 source "arch/arm/mach-mvebu/Kconfig"
930 source "arch/arm/mach-at91/Kconfig"
932 source "arch/arm/mach-axxia/Kconfig"
934 source "arch/arm/mach-bcm/Kconfig"
936 source "arch/arm/mach-berlin/Kconfig"
938 source "arch/arm/mach-clps711x/Kconfig"
940 source "arch/arm/mach-cns3xxx/Kconfig"
942 source "arch/arm/mach-davinci/Kconfig"
944 source "arch/arm/mach-dove/Kconfig"
946 source "arch/arm/mach-ep93xx/Kconfig"
948 source "arch/arm/mach-footbridge/Kconfig"
950 source "arch/arm/mach-gemini/Kconfig"
952 source "arch/arm/mach-highbank/Kconfig"
954 source "arch/arm/mach-hisi/Kconfig"
956 source "arch/arm/mach-integrator/Kconfig"
958 source "arch/arm/mach-iop32x/Kconfig"
960 source "arch/arm/mach-iop33x/Kconfig"
962 source "arch/arm/mach-iop13xx/Kconfig"
964 source "arch/arm/mach-ixp4xx/Kconfig"
966 source "arch/arm/mach-keystone/Kconfig"
968 source "arch/arm/mach-kirkwood/Kconfig"
970 source "arch/arm/mach-ks8695/Kconfig"
972 source "arch/arm/mach-msm/Kconfig"
974 source "arch/arm/mach-moxart/Kconfig"
976 source "arch/arm/mach-mv78xx0/Kconfig"
978 source "arch/arm/mach-imx/Kconfig"
980 source "arch/arm/mach-mxs/Kconfig"
982 source "arch/arm/mach-netx/Kconfig"
984 source "arch/arm/mach-nomadik/Kconfig"
986 source "arch/arm/mach-nspire/Kconfig"
988 source "arch/arm/plat-omap/Kconfig"
990 source "arch/arm/mach-omap1/Kconfig"
992 source "arch/arm/mach-omap2/Kconfig"
994 source "arch/arm/mach-orion5x/Kconfig"
996 source "arch/arm/mach-picoxcell/Kconfig"
998 source "arch/arm/mach-pxa/Kconfig"
999 source "arch/arm/plat-pxa/Kconfig"
1001 source "arch/arm/mach-mmp/Kconfig"
1003 source "arch/arm/mach-qcom/Kconfig"
1005 source "arch/arm/mach-realview/Kconfig"
1007 source "arch/arm/mach-rockchip/Kconfig"
1009 source "arch/arm/mach-sa1100/Kconfig"
1011 source "arch/arm/mach-socfpga/Kconfig"
1013 source "arch/arm/mach-spear/Kconfig"
1015 source "arch/arm/mach-sti/Kconfig"
1017 source "arch/arm/mach-s3c24xx/Kconfig"
1019 source "arch/arm/mach-s3c64xx/Kconfig"
1021 source "arch/arm/mach-s5p64x0/Kconfig"
1023 source "arch/arm/mach-s5pc100/Kconfig"
1025 source "arch/arm/mach-s5pv210/Kconfig"
1027 source "arch/arm/mach-exynos/Kconfig"
1028 source "arch/arm/plat-samsung/Kconfig"
1030 source "arch/arm/mach-shmobile/Kconfig"
1032 source "arch/arm/mach-sunxi/Kconfig"
1034 source "arch/arm/mach-prima2/Kconfig"
1036 source "arch/arm/mach-tegra/Kconfig"
1038 source "arch/arm/mach-u300/Kconfig"
1040 source "arch/arm/mach-ux500/Kconfig"
1042 source "arch/arm/mach-versatile/Kconfig"
1044 source "arch/arm/mach-vexpress/Kconfig"
1045 source "arch/arm/plat-versatile/Kconfig"
1047 source "arch/arm/mach-vt8500/Kconfig"
1049 source "arch/arm/mach-w90x900/Kconfig"
1051 source "arch/arm/mach-zynq/Kconfig"
1053 # Definitions to make life easier
1059 select GENERIC_CLOCKEVENTS
1065 select GENERIC_IRQ_CHIP
1068 config PLAT_ORION_LEGACY
1075 config PLAT_VERSATILE
1078 config ARM_TIMER_SP804
1081 select CLKSRC_OF if OF
1083 source "arch/arm/firmware/Kconfig"
1085 source arch/arm/mm/Kconfig
1088 bool "Enable iWMMXt support"
1089 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1090 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1092 Enable support for iWMMXt context switching at run time if
1093 running on a CPU that supports it.
1095 config MULTI_IRQ_HANDLER
1098 Allow each machine to specify it's own IRQ handler at run time.
1101 source "arch/arm/Kconfig-nommu"
1104 config PJ4B_ERRATA_4742
1105 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1106 depends on CPU_PJ4B && MACH_ARMADA_370
1109 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1110 Event (WFE) IDLE states, a specific timing sensitivity exists between
1111 the retiring WFI/WFE instructions and the newly issued subsequent
1112 instructions. This sensitivity can result in a CPU hang scenario.
1114 The software must insert either a Data Synchronization Barrier (DSB)
1115 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1118 config ARM_ERRATA_326103
1119 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1122 Executing a SWP instruction to read-only memory does not set bit 11
1123 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1124 treat the access as a read, preventing a COW from occurring and
1125 causing the faulting task to livelock.
1127 config ARM_ERRATA_411920
1128 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1129 depends on CPU_V6 || CPU_V6K
1131 Invalidation of the Instruction Cache operation can
1132 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1133 It does not affect the MPCore. This option enables the ARM Ltd.
1134 recommended workaround.
1136 config ARM_ERRATA_430973
1137 bool "ARM errata: Stale prediction on replaced interworking branch"
1140 This option enables the workaround for the 430973 Cortex-A8
1141 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1142 interworking branch is replaced with another code sequence at the
1143 same virtual address, whether due to self-modifying code or virtual
1144 to physical address re-mapping, Cortex-A8 does not recover from the
1145 stale interworking branch prediction. This results in Cortex-A8
1146 executing the new code sequence in the incorrect ARM or Thumb state.
1147 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1148 and also flushes the branch target cache at every context switch.
1149 Note that setting specific bits in the ACTLR register may not be
1150 available in non-secure mode.
1152 config ARM_ERRATA_458693
1153 bool "ARM errata: Processor deadlock when a false hazard is created"
1155 depends on !ARCH_MULTIPLATFORM
1157 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1158 erratum. For very specific sequences of memory operations, it is
1159 possible for a hazard condition intended for a cache line to instead
1160 be incorrectly associated with a different cache line. This false
1161 hazard might then cause a processor deadlock. The workaround enables
1162 the L1 caching of the NEON accesses and disables the PLD instruction
1163 in the ACTLR register. Note that setting specific bits in the ACTLR
1164 register may not be available in non-secure mode.
1166 config ARM_ERRATA_460075
1167 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1169 depends on !ARCH_MULTIPLATFORM
1171 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1172 erratum. Any asynchronous access to the L2 cache may encounter a
1173 situation in which recent store transactions to the L2 cache are lost
1174 and overwritten with stale memory contents from external memory. The
1175 workaround disables the write-allocate mode for the L2 cache via the
1176 ACTLR register. Note that setting specific bits in the ACTLR register
1177 may not be available in non-secure mode.
1179 config ARM_ERRATA_742230
1180 bool "ARM errata: DMB operation may be faulty"
1181 depends on CPU_V7 && SMP
1182 depends on !ARCH_MULTIPLATFORM
1184 This option enables the workaround for the 742230 Cortex-A9
1185 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1186 between two write operations may not ensure the correct visibility
1187 ordering of the two writes. This workaround sets a specific bit in
1188 the diagnostic register of the Cortex-A9 which causes the DMB
1189 instruction to behave as a DSB, ensuring the correct behaviour of
1192 config ARM_ERRATA_742231
1193 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1194 depends on CPU_V7 && SMP
1195 depends on !ARCH_MULTIPLATFORM
1197 This option enables the workaround for the 742231 Cortex-A9
1198 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1199 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1200 accessing some data located in the same cache line, may get corrupted
1201 data due to bad handling of the address hazard when the line gets
1202 replaced from one of the CPUs at the same time as another CPU is
1203 accessing it. This workaround sets specific bits in the diagnostic
1204 register of the Cortex-A9 which reduces the linefill issuing
1205 capabilities of the processor.
1207 config ARM_ERRATA_643719
1208 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1209 depends on CPU_V7 && SMP
1211 This option enables the workaround for the 643719 Cortex-A9 (prior to
1212 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1213 register returns zero when it should return one. The workaround
1214 corrects this value, ensuring cache maintenance operations which use
1215 it behave as intended and avoiding data corruption.
1217 config ARM_ERRATA_720789
1218 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1221 This option enables the workaround for the 720789 Cortex-A9 (prior to
1222 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1223 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1224 As a consequence of this erratum, some TLB entries which should be
1225 invalidated are not, resulting in an incoherency in the system page
1226 tables. The workaround changes the TLB flushing routines to invalidate
1227 entries regardless of the ASID.
1229 config ARM_ERRATA_743622
1230 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1232 depends on !ARCH_MULTIPLATFORM
1234 This option enables the workaround for the 743622 Cortex-A9
1235 (r2p*) erratum. Under very rare conditions, a faulty
1236 optimisation in the Cortex-A9 Store Buffer may lead to data
1237 corruption. This workaround sets a specific bit in the diagnostic
1238 register of the Cortex-A9 which disables the Store Buffer
1239 optimisation, preventing the defect from occurring. This has no
1240 visible impact on the overall performance or power consumption of the
1243 config ARM_ERRATA_751472
1244 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1246 depends on !ARCH_MULTIPLATFORM
1248 This option enables the workaround for the 751472 Cortex-A9 (prior
1249 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1250 completion of a following broadcasted operation if the second
1251 operation is received by a CPU before the ICIALLUIS has completed,
1252 potentially leading to corrupted entries in the cache or TLB.
1254 config ARM_ERRATA_754322
1255 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1258 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1259 r3p*) erratum. A speculative memory access may cause a page table walk
1260 which starts prior to an ASID switch but completes afterwards. This
1261 can populate the micro-TLB with a stale entry which may be hit with
1262 the new ASID. This workaround places two dsb instructions in the mm
1263 switching code so that no page table walks can cross the ASID switch.
1265 config ARM_ERRATA_754327
1266 bool "ARM errata: no automatic Store Buffer drain"
1267 depends on CPU_V7 && SMP
1269 This option enables the workaround for the 754327 Cortex-A9 (prior to
1270 r2p0) erratum. The Store Buffer does not have any automatic draining
1271 mechanism and therefore a livelock may occur if an external agent
1272 continuously polls a memory location waiting to observe an update.
1273 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1274 written polling loops from denying visibility of updates to memory.
1276 config ARM_ERRATA_364296
1277 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1280 This options enables the workaround for the 364296 ARM1136
1281 r0p2 erratum (possible cache data corruption with
1282 hit-under-miss enabled). It sets the undocumented bit 31 in
1283 the auxiliary control register and the FI bit in the control
1284 register, thus disabling hit-under-miss without putting the
1285 processor into full low interrupt latency mode. ARM11MPCore
1288 config ARM_ERRATA_764369
1289 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1290 depends on CPU_V7 && SMP
1292 This option enables the workaround for erratum 764369
1293 affecting Cortex-A9 MPCore with two or more processors (all
1294 current revisions). Under certain timing circumstances, a data
1295 cache line maintenance operation by MVA targeting an Inner
1296 Shareable memory region may fail to proceed up to either the
1297 Point of Coherency or to the Point of Unification of the
1298 system. This workaround adds a DSB instruction before the
1299 relevant cache maintenance functions and sets a specific bit
1300 in the diagnostic control register of the SCU.
1302 config ARM_ERRATA_775420
1303 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1306 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1307 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1308 operation aborts with MMU exception, it might cause the processor
1309 to deadlock. This workaround puts DSB before executing ISB if
1310 an abort may occur on cache maintenance.
1312 config ARM_ERRATA_798181
1313 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1314 depends on CPU_V7 && SMP
1316 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1317 adequately shooting down all use of the old entries. This
1318 option enables the Linux kernel workaround for this erratum
1319 which sends an IPI to the CPUs that are running the same ASID
1320 as the one being invalidated.
1322 config ARM_ERRATA_773022
1323 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1326 This option enables the workaround for the 773022 Cortex-A15
1327 (up to r0p4) erratum. In certain rare sequences of code, the
1328 loop buffer may deliver incorrect instructions. This
1329 workaround disables the loop buffer to avoid the erratum.
1333 source "arch/arm/common/Kconfig"
1343 Find out whether you have ISA slots on your motherboard. ISA is the
1344 name of a bus system, i.e. the way the CPU talks to the other stuff
1345 inside your box. Other bus systems are PCI, EISA, MicroChannel
1346 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1347 newer boards don't support it. If you have ISA, say Y, otherwise N.
1349 # Select ISA DMA controller support
1354 # Select ISA DMA interface
1359 bool "PCI support" if MIGHT_HAVE_PCI
1361 Find out whether you have a PCI motherboard. PCI is the name of a
1362 bus system, i.e. the way the CPU talks to the other stuff inside
1363 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1364 VESA. If you have PCI, say Y, otherwise N.
1370 config PCI_NANOENGINE
1371 bool "BSE nanoEngine PCI support"
1372 depends on SA1100_NANOENGINE
1374 Enable PCI on the BSE nanoEngine board.
1379 config PCI_HOST_ITE8152
1381 depends on PCI && MACH_ARMCORE
1385 source "drivers/pci/Kconfig"
1386 source "drivers/pci/pcie/Kconfig"
1388 source "drivers/pcmcia/Kconfig"
1392 menu "Kernel Features"
1397 This option should be selected by machines which have an SMP-
1400 The only effect of this option is to make the SMP-related
1401 options available to the user for configuration.
1404 bool "Symmetric Multi-Processing"
1405 depends on CPU_V6K || CPU_V7
1406 depends on GENERIC_CLOCKEVENTS
1408 depends on MMU || ARM_MPU
1410 This enables support for systems with more than one CPU. If you have
1411 a system with only one CPU, say N. If you have a system with more
1412 than one CPU, say Y.
1414 If you say N here, the kernel will run on uni- and multiprocessor
1415 machines, but will use only one CPU of a multiprocessor machine. If
1416 you say Y here, the kernel will run on many, but not all,
1417 uniprocessor machines. On a uniprocessor machine, the kernel
1418 will run faster if you say N here.
1420 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1421 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1422 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1424 If you don't know what to do here, say N.
1427 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1428 depends on SMP && !XIP_KERNEL && MMU
1431 SMP kernels contain instructions which fail on non-SMP processors.
1432 Enabling this option allows the kernel to modify itself to make
1433 these instructions safe. Disabling it allows about 1K of space
1436 If you don't know what to do here, say Y.
1438 config ARM_CPU_TOPOLOGY
1439 bool "Support cpu topology definition"
1440 depends on SMP && CPU_V7
1443 Support ARM cpu topology definition. The MPIDR register defines
1444 affinity between processors which is then used to describe the cpu
1445 topology of an ARM System.
1448 bool "Multi-core scheduler support"
1449 depends on ARM_CPU_TOPOLOGY
1451 Multi-core scheduler support improves the CPU scheduler's decision
1452 making when dealing with multi-core CPU chips at a cost of slightly
1453 increased overhead in some places. If unsure say N here.
1456 bool "SMT scheduler support"
1457 depends on ARM_CPU_TOPOLOGY
1459 Improves the CPU scheduler's decision making when dealing with
1460 MultiThreading at a cost of slightly increased overhead in some
1461 places. If unsure say N here.
1466 This option enables support for the ARM system coherency unit
1468 config HAVE_ARM_ARCH_TIMER
1469 bool "Architected timer support"
1471 select ARM_ARCH_TIMER
1472 select GENERIC_CLOCKEVENTS
1474 This option enables support for the ARM architected timer
1479 select CLKSRC_OF if OF
1481 This options enables support for the ARM timer and watchdog unit
1484 bool "Multi-Cluster Power Management"
1485 depends on CPU_V7 && SMP
1487 This option provides the common power management infrastructure
1488 for (multi-)cluster based systems, such as big.LITTLE based
1492 bool "big.LITTLE support (Experimental)"
1493 depends on CPU_V7 && SMP
1496 This option enables support selections for the big.LITTLE
1497 system architecture.
1500 bool "big.LITTLE switcher support"
1501 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1502 select ARM_CPU_SUSPEND
1505 The big.LITTLE "switcher" provides the core functionality to
1506 transparently handle transition between a cluster of A15's
1507 and a cluster of A7's in a big.LITTLE system.
1509 config BL_SWITCHER_DUMMY_IF
1510 tristate "Simple big.LITTLE switcher user interface"
1511 depends on BL_SWITCHER && DEBUG_KERNEL
1513 This is a simple and dummy char dev interface to control
1514 the big.LITTLE switcher core code. It is meant for
1515 debugging purposes only.
1518 prompt "Memory split"
1522 Select the desired split between kernel and user memory.
1524 If you are not absolutely sure what you are doing, leave this
1528 bool "3G/1G user/kernel split"
1530 bool "2G/2G user/kernel split"
1532 bool "1G/3G user/kernel split"
1537 default PHYS_OFFSET if !MMU
1538 default 0x40000000 if VMSPLIT_1G
1539 default 0x80000000 if VMSPLIT_2G
1543 int "Maximum number of CPUs (2-32)"
1549 bool "Support for hot-pluggable CPUs"
1552 Say Y here to experiment with turning CPUs off and on. CPUs
1553 can be controlled through /sys/devices/system/cpu.
1556 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1559 Say Y here if you want Linux to communicate with system firmware
1560 implementing the PSCI specification for CPU-centric power
1561 management operations described in ARM document number ARM DEN
1562 0022A ("Power State Coordination Interface System Software on
1565 # The GPIO number here must be sorted by descending number. In case of
1566 # a multiplatform kernel, we just want the highest value required by the
1567 # selected platforms.
1570 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1571 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX
1572 default 416 if ARCH_SUNXI
1573 default 392 if ARCH_U8500
1574 default 352 if ARCH_VT8500
1575 default 264 if MACH_H4700
1578 Maximum number of GPIOs in the system.
1580 If unsure, leave the default value.
1582 source kernel/Kconfig.preempt
1586 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1587 ARCH_S5PV210 || ARCH_EXYNOS4
1588 default AT91_TIMER_HZ if ARCH_AT91
1589 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1593 depends on HZ_FIXED = 0
1594 prompt "Timer frequency"
1618 default HZ_FIXED if HZ_FIXED != 0
1619 default 100 if HZ_100
1620 default 200 if HZ_200
1621 default 250 if HZ_250
1622 default 300 if HZ_300
1623 default 500 if HZ_500
1627 def_bool HIGH_RES_TIMERS
1629 config THUMB2_KERNEL
1630 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1631 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1632 default y if CPU_THUMBONLY
1634 select ARM_ASM_UNIFIED
1637 By enabling this option, the kernel will be compiled in
1638 Thumb-2 mode. A compiler/assembler that understand the unified
1639 ARM-Thumb syntax is needed.
1643 config THUMB2_AVOID_R_ARM_THM_JUMP11
1644 bool "Work around buggy Thumb-2 short branch relocations in gas"
1645 depends on THUMB2_KERNEL && MODULES
1648 Various binutils versions can resolve Thumb-2 branches to
1649 locally-defined, preemptible global symbols as short-range "b.n"
1650 branch instructions.
1652 This is a problem, because there's no guarantee the final
1653 destination of the symbol, or any candidate locations for a
1654 trampoline, are within range of the branch. For this reason, the
1655 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1656 relocation in modules at all, and it makes little sense to add
1659 The symptom is that the kernel fails with an "unsupported
1660 relocation" error when loading some modules.
1662 Until fixed tools are available, passing
1663 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1664 code which hits this problem, at the cost of a bit of extra runtime
1665 stack usage in some cases.
1667 The problem is described in more detail at:
1668 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1670 Only Thumb-2 kernels are affected.
1672 Unless you are sure your tools don't have this problem, say Y.
1674 config ARM_ASM_UNIFIED
1678 bool "Use the ARM EABI to compile the kernel"
1680 This option allows for the kernel to be compiled using the latest
1681 ARM ABI (aka EABI). This is only useful if you are using a user
1682 space environment that is also compiled with EABI.
1684 Since there are major incompatibilities between the legacy ABI and
1685 EABI, especially with regard to structure member alignment, this
1686 option also changes the kernel syscall calling convention to
1687 disambiguate both ABIs and allow for backward compatibility support
1688 (selected with CONFIG_OABI_COMPAT).
1690 To use this you need GCC version 4.0.0 or later.
1693 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1694 depends on AEABI && !THUMB2_KERNEL
1696 This option preserves the old syscall interface along with the
1697 new (ARM EABI) one. It also provides a compatibility layer to
1698 intercept syscalls that have structure arguments which layout
1699 in memory differs between the legacy ABI and the new ARM EABI
1700 (only for non "thumb" binaries). This option adds a tiny
1701 overhead to all syscalls and produces a slightly larger kernel.
1703 The seccomp filter system will not be available when this is
1704 selected, since there is no way yet to sensibly distinguish
1705 between calling conventions during filtering.
1707 If you know you'll be using only pure EABI user space then you
1708 can say N here. If this option is not selected and you attempt
1709 to execute a legacy ABI binary then the result will be
1710 UNPREDICTABLE (in fact it can be predicted that it won't work
1711 at all). If in doubt say N.
1713 config ARCH_HAS_HOLES_MEMORYMODEL
1716 config ARCH_SPARSEMEM_ENABLE
1719 config ARCH_SPARSEMEM_DEFAULT
1720 def_bool ARCH_SPARSEMEM_ENABLE
1722 config ARCH_SELECT_MEMORY_MODEL
1723 def_bool ARCH_SPARSEMEM_ENABLE
1725 config HAVE_ARCH_PFN_VALID
1726 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1729 bool "High Memory Support"
1732 The address space of ARM processors is only 4 Gigabytes large
1733 and it has to accommodate user address space, kernel address
1734 space as well as some memory mapped IO. That means that, if you
1735 have a large amount of physical memory and/or IO, not all of the
1736 memory can be "permanently mapped" by the kernel. The physical
1737 memory that is not permanently mapped is called "high memory".
1739 Depending on the selected kernel/user memory split, minimum
1740 vmalloc space and actual amount of RAM, you may not need this
1741 option which should result in a slightly faster kernel.
1746 bool "Allocate 2nd-level pagetables from highmem"
1749 config HW_PERF_EVENTS
1750 bool "Enable hardware performance counter support for perf events"
1751 depends on PERF_EVENTS
1754 Enable hardware performance counter support for perf events. If
1755 disabled, perf events will use software events only.
1757 config SYS_SUPPORTS_HUGETLBFS
1761 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1765 config ARCH_WANT_GENERAL_HUGETLB
1770 config FORCE_MAX_ZONEORDER
1771 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1772 range 11 64 if ARCH_SHMOBILE_LEGACY
1773 default "12" if SOC_AM33XX
1774 default "9" if SA1111 || ARCH_EFM32
1777 The kernel memory allocator divides physically contiguous memory
1778 blocks into "zones", where each zone is a power of two number of
1779 pages. This option selects the largest power of two that the kernel
1780 keeps in the memory allocator. If you need to allocate very large
1781 blocks of physically contiguous memory, then you may need to
1782 increase this value.
1784 This config option is actually maximum order plus one. For example,
1785 a value of 11 means that the largest free memory block is 2^10 pages.
1787 config ALIGNMENT_TRAP
1789 depends on CPU_CP15_MMU
1790 default y if !ARCH_EBSA110
1791 select HAVE_PROC_CPU if PROC_FS
1793 ARM processors cannot fetch/store information which is not
1794 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1795 address divisible by 4. On 32-bit ARM processors, these non-aligned
1796 fetch/store instructions will be emulated in software if you say
1797 here, which has a severe performance impact. This is necessary for
1798 correct operation of some network protocols. With an IP-only
1799 configuration it is safe to say N, otherwise say Y.
1801 config UACCESS_WITH_MEMCPY
1802 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1804 default y if CPU_FEROCEON
1806 Implement faster copy_to_user and clear_user methods for CPU
1807 cores where a 8-word STM instruction give significantly higher
1808 memory write throughput than a sequence of individual 32bit stores.
1810 A possible side effect is a slight increase in scheduling latency
1811 between threads sharing the same address space if they invoke
1812 such copy operations with large buffers.
1814 However, if the CPU data cache is using a write-allocate mode,
1815 this option is unlikely to provide any performance gain.
1819 prompt "Enable seccomp to safely compute untrusted bytecode"
1821 This kernel feature is useful for number crunching applications
1822 that may need to compute untrusted bytecode during their
1823 execution. By using pipes or other transports made available to
1824 the process as file descriptors supporting the read/write
1825 syscalls, it's possible to isolate those applications in
1826 their own address space using seccomp. Once seccomp is
1827 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1828 and the task is only allowed to execute a few safe syscalls
1829 defined by each seccomp mode.
1842 bool "Xen guest support on ARM (EXPERIMENTAL)"
1843 depends on ARM && AEABI && OF
1844 depends on CPU_V7 && !CPU_V6
1845 depends on !GENERIC_ATOMIC64
1847 select ARCH_DMA_ADDR_T_64BIT
1851 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1858 bool "Flattened Device Tree support"
1861 select OF_EARLY_FLATTREE
1862 select OF_RESERVED_MEM
1864 Include support for flattened device tree machine descriptions.
1867 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1870 This is the traditional way of passing data to the kernel at boot
1871 time. If you are solely relying on the flattened device tree (or
1872 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1873 to remove ATAGS support from your kernel binary. If unsure,
1876 config DEPRECATED_PARAM_STRUCT
1877 bool "Provide old way to pass kernel parameters"
1880 This was deprecated in 2001 and announced to live on for 5 years.
1881 Some old boot loaders still use this way.
1883 # Compressed boot loader in ROM. Yes, we really want to ask about
1884 # TEXT and BSS so we preserve their values in the config files.
1885 config ZBOOT_ROM_TEXT
1886 hex "Compressed ROM boot loader base address"
1889 The physical address at which the ROM-able zImage is to be
1890 placed in the target. Platforms which normally make use of
1891 ROM-able zImage formats normally set this to a suitable
1892 value in their defconfig file.
1894 If ZBOOT_ROM is not enabled, this has no effect.
1896 config ZBOOT_ROM_BSS
1897 hex "Compressed ROM boot loader BSS address"
1900 The base address of an area of read/write memory in the target
1901 for the ROM-able zImage which must be available while the
1902 decompressor is running. It must be large enough to hold the
1903 entire decompressed kernel plus an additional 128 KiB.
1904 Platforms which normally make use of ROM-able zImage formats
1905 normally set this to a suitable value in their defconfig file.
1907 If ZBOOT_ROM is not enabled, this has no effect.
1910 bool "Compressed boot loader in ROM/flash"
1911 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1912 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1914 Say Y here if you intend to execute your compressed kernel image
1915 (zImage) directly from ROM or flash. If unsure, say N.
1918 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1919 depends on ZBOOT_ROM && ARCH_SH7372
1920 default ZBOOT_ROM_NONE
1922 Include experimental SD/MMC loading code in the ROM-able zImage.
1923 With this enabled it is possible to write the ROM-able zImage
1924 kernel image to an MMC or SD card and boot the kernel straight
1925 from the reset vector. At reset the processor Mask ROM will load
1926 the first part of the ROM-able zImage which in turn loads the
1927 rest the kernel image to RAM.
1929 config ZBOOT_ROM_NONE
1930 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1932 Do not load image from SD or MMC
1934 config ZBOOT_ROM_MMCIF
1935 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1937 Load image from MMCIF hardware block.
1939 config ZBOOT_ROM_SH_MOBILE_SDHI
1940 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1942 Load image from SDHI hardware block
1946 config ARM_APPENDED_DTB
1947 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1950 With this option, the boot code will look for a device tree binary
1951 (DTB) appended to zImage
1952 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1954 This is meant as a backward compatibility convenience for those
1955 systems with a bootloader that can't be upgraded to accommodate
1956 the documented boot protocol using a device tree.
1958 Beware that there is very little in terms of protection against
1959 this option being confused by leftover garbage in memory that might
1960 look like a DTB header after a reboot if no actual DTB is appended
1961 to zImage. Do not leave this option active in a production kernel
1962 if you don't intend to always append a DTB. Proper passing of the
1963 location into r2 of a bootloader provided DTB is always preferable
1966 config ARM_ATAG_DTB_COMPAT
1967 bool "Supplement the appended DTB with traditional ATAG information"
1968 depends on ARM_APPENDED_DTB
1970 Some old bootloaders can't be updated to a DTB capable one, yet
1971 they provide ATAGs with memory configuration, the ramdisk address,
1972 the kernel cmdline string, etc. Such information is dynamically
1973 provided by the bootloader and can't always be stored in a static
1974 DTB. To allow a device tree enabled kernel to be used with such
1975 bootloaders, this option allows zImage to extract the information
1976 from the ATAG list and store it at run time into the appended DTB.
1979 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1980 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1982 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1983 bool "Use bootloader kernel arguments if available"
1985 Uses the command-line options passed by the boot loader instead of
1986 the device tree bootargs property. If the boot loader doesn't provide
1987 any, the device tree bootargs property will be used.
1989 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1990 bool "Extend with bootloader kernel arguments"
1992 The command-line arguments provided by the boot loader will be
1993 appended to the the device tree bootargs property.
1998 string "Default kernel command string"
2001 On some architectures (EBSA110 and CATS), there is currently no way
2002 for the boot loader to pass arguments to the kernel. For these
2003 architectures, you should supply some command-line options at build
2004 time by entering them here. As a minimum, you should specify the
2005 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2008 prompt "Kernel command line type" if CMDLINE != ""
2009 default CMDLINE_FROM_BOOTLOADER
2012 config CMDLINE_FROM_BOOTLOADER
2013 bool "Use bootloader kernel arguments if available"
2015 Uses the command-line options passed by the boot loader. If
2016 the boot loader doesn't provide any, the default kernel command
2017 string provided in CMDLINE will be used.
2019 config CMDLINE_EXTEND
2020 bool "Extend bootloader kernel arguments"
2022 The command-line arguments provided by the boot loader will be
2023 appended to the default kernel command string.
2025 config CMDLINE_FORCE
2026 bool "Always use the default kernel command string"
2028 Always use the default kernel command string, even if the boot
2029 loader passes other arguments to the kernel.
2030 This is useful if you cannot or don't want to change the
2031 command-line options your boot loader passes to the kernel.
2035 bool "Kernel Execute-In-Place from ROM"
2036 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
2038 Execute-In-Place allows the kernel to run from non-volatile storage
2039 directly addressable by the CPU, such as NOR flash. This saves RAM
2040 space since the text section of the kernel is not loaded from flash
2041 to RAM. Read-write sections, such as the data section and stack,
2042 are still copied to RAM. The XIP kernel is not compressed since
2043 it has to run directly from flash, so it will take more space to
2044 store it. The flash address used to link the kernel object files,
2045 and for storing it, is configuration dependent. Therefore, if you
2046 say Y here, you must know the proper physical address where to
2047 store the kernel image depending on your own flash memory usage.
2049 Also note that the make target becomes "make xipImage" rather than
2050 "make zImage" or "make Image". The final kernel binary to put in
2051 ROM memory will be arch/arm/boot/xipImage.
2055 config XIP_PHYS_ADDR
2056 hex "XIP Kernel Physical Location"
2057 depends on XIP_KERNEL
2058 default "0x00080000"
2060 This is the physical address in your flash memory the kernel will
2061 be linked for and stored to. This address is dependent on your
2065 bool "Kexec system call (EXPERIMENTAL)"
2066 depends on (!SMP || PM_SLEEP_SMP)
2068 kexec is a system call that implements the ability to shutdown your
2069 current kernel, and to start another kernel. It is like a reboot
2070 but it is independent of the system firmware. And like a reboot
2071 you can start any kernel with it, not just Linux.
2073 It is an ongoing process to be certain the hardware in a machine
2074 is properly shutdown, so do not be surprised if this code does not
2075 initially work for you.
2078 bool "Export atags in procfs"
2079 depends on ATAGS && KEXEC
2082 Should the atags used to boot the kernel be exported in an "atags"
2083 file in procfs. Useful with kexec.
2086 bool "Build kdump crash kernel (EXPERIMENTAL)"
2088 Generate crash dump after being started by kexec. This should
2089 be normally only set in special crash dump kernels which are
2090 loaded in the main kernel with kexec-tools into a specially
2091 reserved region and then later executed after a crash by
2092 kdump/kexec. The crash dump kernel must be compiled to a
2093 memory address not used by the main kernel
2095 For more details see Documentation/kdump/kdump.txt
2097 config AUTO_ZRELADDR
2098 bool "Auto calculation of the decompressed kernel image address"
2100 ZRELADDR is the physical address where the decompressed kernel
2101 image will be placed. If AUTO_ZRELADDR is selected, the address
2102 will be determined at run-time by masking the current IP with
2103 0xf8000000. This assumes the zImage being placed in the first 128MB
2104 from start of memory.
2108 menu "CPU Power Management"
2110 source "drivers/cpufreq/Kconfig"
2112 source "drivers/cpuidle/Kconfig"
2116 menu "Floating point emulation"
2118 comment "At least one emulation must be selected"
2121 bool "NWFPE math emulation"
2122 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2124 Say Y to include the NWFPE floating point emulator in the kernel.
2125 This is necessary to run most binaries. Linux does not currently
2126 support floating point hardware so you need to say Y here even if
2127 your machine has an FPA or floating point co-processor podule.
2129 You may say N here if you are going to load the Acorn FPEmulator
2130 early in the bootup.
2133 bool "Support extended precision"
2134 depends on FPE_NWFPE
2136 Say Y to include 80-bit support in the kernel floating-point
2137 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2138 Note that gcc does not generate 80-bit operations by default,
2139 so in most cases this option only enlarges the size of the
2140 floating point emulator without any good reason.
2142 You almost surely want to say N here.
2145 bool "FastFPE math emulation (EXPERIMENTAL)"
2146 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2148 Say Y here to include the FAST floating point emulator in the kernel.
2149 This is an experimental much faster emulator which now also has full
2150 precision for the mantissa. It does not support any exceptions.
2151 It is very simple, and approximately 3-6 times faster than NWFPE.
2153 It should be sufficient for most programs. It may be not suitable
2154 for scientific calculations, but you have to check this for yourself.
2155 If you do not feel you need a faster FP emulation you should better
2159 bool "VFP-format floating point maths"
2160 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2162 Say Y to include VFP support code in the kernel. This is needed
2163 if your hardware includes a VFP unit.
2165 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2166 release notes and additional status information.
2168 Say N if your target does not have VFP hardware.
2176 bool "Advanced SIMD (NEON) Extension support"
2177 depends on VFPv3 && CPU_V7
2179 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2182 config KERNEL_MODE_NEON
2183 bool "Support for NEON in kernel mode"
2184 depends on NEON && AEABI
2186 Say Y to include support for NEON in kernel mode.
2190 menu "Userspace binary formats"
2192 source "fs/Kconfig.binfmt"
2195 tristate "RISC OS personality"
2198 Say Y here to include the kernel code necessary if you want to run
2199 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2200 experimental; if this sounds frightening, say N and sleep in peace.
2201 You can also say M here to compile this support as a module (which
2202 will be called arthur).
2206 menu "Power management options"
2208 source "kernel/power/Kconfig"
2210 config ARCH_SUSPEND_POSSIBLE
2211 depends on !ARCH_S5PC100
2212 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2213 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2216 config ARM_CPU_SUSPEND
2219 config ARCH_HIBERNATION_POSSIBLE
2222 default y if ARCH_SUSPEND_POSSIBLE
2226 source "net/Kconfig"
2228 source "drivers/Kconfig"
2232 source "arch/arm/Kconfig.debug"
2234 source "security/Kconfig"
2236 source "crypto/Kconfig"
2238 source "lib/Kconfig"
2240 source "arch/arm/kvm/Kconfig"