4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
8 select ARCH_WANT_IPC_PARSE_VERSION
9 select BUILDTIME_EXTABLE_SORT if MMU
10 select CPU_PM if (SUSPEND || CPU_IDLE)
11 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
12 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
13 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
14 select GENERIC_IRQ_PROBE
15 select GENERIC_IRQ_SHOW
16 select GENERIC_PCI_IOMAP
17 select GENERIC_SMP_IDLE_THREAD
18 select GENERIC_IDLE_POLL_SETUP
19 select GENERIC_STRNCPY_FROM_USER
20 select GENERIC_STRNLEN_USER
21 select HARDIRQS_SW_RESEND
22 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
24 select HAVE_ARCH_SECCOMP_FILTER
25 select HAVE_ARCH_TRACEHOOK
27 select HAVE_C_RECORDMCOUNT
28 select HAVE_DEBUG_KMEMLEAK
29 select HAVE_DMA_API_DEBUG
31 select HAVE_DMA_CONTIGUOUS if MMU
32 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
33 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
34 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
35 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
36 select HAVE_GENERIC_DMA_COHERENT
37 select HAVE_GENERIC_HARDIRQS
38 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
39 select HAVE_IDE if PCI || ISA || PCMCIA
40 select HAVE_IRQ_TIME_ACCOUNTING
41 select HAVE_KERNEL_GZIP
42 select HAVE_KERNEL_LZMA
43 select HAVE_KERNEL_LZO
45 select HAVE_KPROBES if !XIP_KERNEL
46 select HAVE_KRETPROBES if (HAVE_KPROBES)
48 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
49 select HAVE_PERF_EVENTS
50 select HAVE_REGS_AND_STACK_ACCESS_API
51 select HAVE_SYSCALL_TRACEPOINTS
54 select PERF_USE_VMALLOC
56 select SYS_SUPPORTS_APM_EMULATION
57 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
58 select MODULES_USE_ELF_REL
59 select CLONE_BACKWARDS
60 select OLD_SIGSUSPEND3
62 select HAVE_CONTEXT_TRACKING
64 The ARM series is a line of low-power-consumption RISC chip designs
65 licensed by ARM Ltd and targeted at embedded applications and
66 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
67 manufactured, but legacy ARM-based PC hardware remains popular in
68 Europe. There is an ARM Linux project with a web page at
69 <http://www.arm.linux.org.uk/>.
71 config ARM_HAS_SG_CHAIN
74 config NEED_SG_DMA_LENGTH
77 config ARM_DMA_USE_IOMMU
79 select ARM_HAS_SG_CHAIN
80 select NEED_SG_DMA_LENGTH
84 config ARM_DMA_IOMMU_ALIGNMENT
85 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
89 DMA mapping framework by default aligns all buffers to the smallest
90 PAGE_SIZE order which is greater than or equal to the requested buffer
91 size. This works well for buffers up to a few hundreds kilobytes, but
92 for larger buffers it just a waste of address space. Drivers which has
93 relatively small addressing window (like 64Mib) might run out of
94 virtual space with just a few allocations.
96 With this parameter you can specify the maximum PAGE_SIZE order for
97 DMA IOMMU buffers. Larger buffers will be aligned only to this
98 specified order. The order is expressed as a power of two multiplied
106 config MIGHT_HAVE_PCI
109 config SYS_SUPPORTS_APM_EMULATION
114 select GENERIC_ALLOCATOR
125 The Extended Industry Standard Architecture (EISA) bus was
126 developed as an open alternative to the IBM MicroChannel bus.
128 The EISA bus provided some of the features of the IBM MicroChannel
129 bus while maintaining backward compatibility with cards made for
130 the older ISA bus. The EISA bus saw limited use between 1988 and
131 1995 when it was made obsolete by the PCI bus.
133 Say Y here if you are building a kernel for an EISA-based machine.
140 config STACKTRACE_SUPPORT
144 config HAVE_LATENCYTOP_SUPPORT
149 config LOCKDEP_SUPPORT
153 config TRACE_IRQFLAGS_SUPPORT
157 config RWSEM_GENERIC_SPINLOCK
161 config RWSEM_XCHGADD_ALGORITHM
164 config ARCH_HAS_ILOG2_U32
167 config ARCH_HAS_ILOG2_U64
170 config ARCH_HAS_CPUFREQ
173 Internal node to signify that the ARCH has CPUFREQ support
174 and that the relevant menu configurations are displayed for
177 config GENERIC_HWEIGHT
181 config GENERIC_CALIBRATE_DELAY
185 config ARCH_MAY_HAVE_PC_FDC
191 config NEED_DMA_MAP_STATE
194 config ARCH_HAS_DMA_SET_COHERENT_MASK
197 config GENERIC_ISA_DMA
203 config NEED_RET_TO_USER
211 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
212 default DRAM_BASE if REMAP_VECTORS_TO_RAM
215 The base address of exception vectors. This must be two pages
218 config ARM_PATCH_PHYS_VIRT
219 bool "Patch physical to virtual translations at runtime" if EMBEDDED
221 depends on !XIP_KERNEL && MMU
222 depends on !ARCH_REALVIEW || !SPARSEMEM
224 Patch phys-to-virt and virt-to-phys translation functions at
225 boot and module load time according to the position of the
226 kernel in system memory.
228 This can only be used with non-XIP MMU kernels where the base
229 of physical memory is at a 16MB boundary.
231 Only disable this option if you know that you do not require
232 this feature (eg, building a kernel for a single machine) and
233 you need to shrink the kernel to the minimal size.
235 config NEED_MACH_GPIO_H
238 Select this when mach/gpio.h is required to provide special
239 definitions for this platform. The need for mach/gpio.h should
240 be avoided when possible.
242 config NEED_MACH_IO_H
245 Select this when mach/io.h is required to provide special
246 definitions for this platform. The need for mach/io.h should
247 be avoided when possible.
249 config NEED_MACH_MEMORY_H
252 Select this when mach/memory.h is required to provide special
253 definitions for this platform. The need for mach/memory.h should
254 be avoided when possible.
257 hex "Physical address of main memory" if MMU
258 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
259 default DRAM_BASE if !MMU
261 Please provide the physical address corresponding to the
262 location of main memory in your system.
268 source "init/Kconfig"
270 source "kernel/Kconfig.freezer"
275 bool "MMU-based Paged Memory Management Support"
278 Select if you want MMU-based virtualised addressing space
279 support by paged memory management. If unsure, say 'Y'.
282 # The "ARM system type" choice list is ordered alphabetically by option
283 # text. Please add new entries in the option alphabetic order.
286 prompt "ARM system type"
287 default ARCH_VERSATILE if !MMU
288 default ARCH_MULTIPLATFORM if MMU
290 config ARCH_MULTIPLATFORM
291 bool "Allow multiple platforms to be selected"
293 select ARM_PATCH_PHYS_VIRT
296 select MULTI_IRQ_HANDLER
300 config ARCH_INTEGRATOR
301 bool "ARM Ltd. Integrator family"
302 select ARCH_HAS_CPUFREQ
305 select COMMON_CLK_VERSATILE
306 select GENERIC_CLOCKEVENTS
309 select MULTI_IRQ_HANDLER
310 select NEED_MACH_MEMORY_H
311 select PLAT_VERSATILE
313 select VERSATILE_FPGA_IRQ
315 Support for ARM's Integrator platform.
318 bool "ARM Ltd. RealView family"
319 select ARCH_WANT_OPTIONAL_GPIOLIB
321 select ARM_TIMER_SP804
323 select COMMON_CLK_VERSATILE
324 select GENERIC_CLOCKEVENTS
325 select GPIO_PL061 if GPIOLIB
327 select NEED_MACH_MEMORY_H
328 select PLAT_VERSATILE
329 select PLAT_VERSATILE_CLCD
331 This enables support for ARM Ltd RealView boards.
333 config ARCH_VERSATILE
334 bool "ARM Ltd. Versatile family"
335 select ARCH_WANT_OPTIONAL_GPIOLIB
337 select ARM_TIMER_SP804
340 select GENERIC_CLOCKEVENTS
341 select HAVE_MACH_CLKDEV
343 select PLAT_VERSATILE
344 select PLAT_VERSATILE_CLCD
345 select PLAT_VERSATILE_CLOCK
346 select VERSATILE_FPGA_IRQ
348 This enables support for ARM Ltd Versatile board.
352 select ARCH_REQUIRE_GPIOLIB
356 select NEED_MACH_GPIO_H
357 select NEED_MACH_IO_H if PCCARD
359 select PINCTRL_AT91 if USE_OF
361 This enables support for systems based on Atmel
362 AT91RM9200 and AT91SAM9* processors.
365 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
366 select ARCH_REQUIRE_GPIOLIB
371 select GENERIC_CLOCKEVENTS
372 select MULTI_IRQ_HANDLER
373 select NEED_MACH_MEMORY_H
376 Support for Cirrus Logic 711x/721x/731x based boards.
379 bool "Cortina Systems Gemini"
380 select ARCH_REQUIRE_GPIOLIB
381 select ARCH_USES_GETTIMEOFFSET
382 select NEED_MACH_GPIO_H
385 Support for the Cortina Systems Gemini family SoCs
389 select ARCH_USES_GETTIMEOFFSET
392 select NEED_MACH_IO_H
393 select NEED_MACH_MEMORY_H
396 This is an evaluation board for the StrongARM processor available
397 from Digital. It has limited hardware on-board, including an
398 Ethernet interface, two PCMCIA sockets, two serial ports and a
403 select ARCH_HAS_HOLES_MEMORYMODEL
404 select ARCH_REQUIRE_GPIOLIB
405 select ARCH_USES_GETTIMEOFFSET
410 select NEED_MACH_MEMORY_H
412 This enables support for the Cirrus EP93xx series of CPUs.
414 config ARCH_FOOTBRIDGE
418 select GENERIC_CLOCKEVENTS
420 select NEED_MACH_IO_H if !MMU
421 select NEED_MACH_MEMORY_H
423 Support for systems based on the DC21285 companion chip
424 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
427 bool "Hilscher NetX based"
431 select GENERIC_CLOCKEVENTS
433 This enables support for systems based on the Hilscher NetX Soc
438 select ARCH_SUPPORTS_MSI
440 select NEED_MACH_MEMORY_H
441 select NEED_RET_TO_USER
446 Support for Intel's IOP13XX (XScale) family of processors.
451 select ARCH_REQUIRE_GPIOLIB
453 select NEED_MACH_GPIO_H
454 select NEED_RET_TO_USER
458 Support for Intel's 80219 and IOP32X (XScale) family of
464 select ARCH_REQUIRE_GPIOLIB
466 select NEED_MACH_GPIO_H
467 select NEED_RET_TO_USER
471 Support for Intel's IOP33X (XScale) family of processors.
476 select ARCH_HAS_DMA_SET_COHERENT_MASK
477 select ARCH_SUPPORTS_BIG_ENDIAN
478 select ARCH_REQUIRE_GPIOLIB
481 select DMABOUNCE if PCI
482 select GENERIC_CLOCKEVENTS
483 select MIGHT_HAVE_PCI
484 select NEED_MACH_IO_H
485 select USB_EHCI_BIG_ENDIAN_MMIO
486 select USB_EHCI_BIG_ENDIAN_DESC
488 Support for Intel's IXP4XX (XScale) family of processors.
492 select ARCH_REQUIRE_GPIOLIB
494 select GENERIC_CLOCKEVENTS
495 select MIGHT_HAVE_PCI
498 select PLAT_ORION_LEGACY
499 select USB_ARCH_HAS_EHCI
502 Support for the Marvell Dove SoC 88AP510
505 bool "Marvell Kirkwood"
506 select ARCH_REQUIRE_GPIOLIB
508 select GENERIC_CLOCKEVENTS
512 select PINCTRL_KIRKWOOD
513 select PLAT_ORION_LEGACY
516 Support for the following Marvell Kirkwood series SoCs:
517 88F6180, 88F6192 and 88F6281.
520 bool "Marvell MV78xx0"
521 select ARCH_REQUIRE_GPIOLIB
523 select GENERIC_CLOCKEVENTS
525 select PLAT_ORION_LEGACY
528 Support for the following Marvell MV78xx0 series SoCs:
534 select ARCH_REQUIRE_GPIOLIB
536 select GENERIC_CLOCKEVENTS
538 select PLAT_ORION_LEGACY
541 Support for the following Marvell Orion 5x series SoCs:
542 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
543 Orion-2 (5281), Orion-1-90 (6183).
546 bool "Marvell PXA168/910/MMP2"
548 select ARCH_REQUIRE_GPIOLIB
550 select GENERIC_ALLOCATOR
551 select GENERIC_CLOCKEVENTS
554 select NEED_MACH_GPIO_H
559 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
562 bool "Micrel/Kendin KS8695"
563 select ARCH_REQUIRE_GPIOLIB
566 select GENERIC_CLOCKEVENTS
567 select NEED_MACH_MEMORY_H
569 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
570 System-on-Chip devices.
573 bool "Nuvoton W90X900 CPU"
574 select ARCH_REQUIRE_GPIOLIB
578 select GENERIC_CLOCKEVENTS
580 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
581 At present, the w90x900 has been renamed nuc900, regarding
582 the ARM series product line, you can login the following
583 link address to know more.
585 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
586 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
590 select ARCH_REQUIRE_GPIOLIB
595 select GENERIC_CLOCKEVENTS
598 select USB_ARCH_HAS_OHCI
601 Support for the NXP LPC32XX family of processors
604 bool "PXA2xx/PXA3xx-based"
606 select ARCH_HAS_CPUFREQ
608 select ARCH_REQUIRE_GPIOLIB
609 select ARM_CPU_SUSPEND if PM
613 select GENERIC_CLOCKEVENTS
616 select MULTI_IRQ_HANDLER
617 select NEED_MACH_GPIO_H
621 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
625 select ARCH_REQUIRE_GPIOLIB
627 select GENERIC_CLOCKEVENTS
630 Support for Qualcomm MSM/QSD based systems. This runs on the
631 apps processor of the MSM/QSD and depends on a shared memory
632 interface to the modem processor which runs the baseband
633 stack and controls some vital subsystems
634 (clock and power control, etc).
637 bool "Renesas SH-Mobile / R-Mobile"
639 select GENERIC_CLOCKEVENTS
640 select HAVE_ARM_SCU if SMP
641 select HAVE_ARM_TWD if LOCAL_TIMERS
643 select HAVE_MACH_CLKDEV
645 select MIGHT_HAVE_CACHE_L2X0
646 select MULTI_IRQ_HANDLER
647 select NEED_MACH_MEMORY_H
649 select PINCTRL if ARCH_WANT_OPTIONAL_GPIOLIB
650 select PM_GENERIC_DOMAINS if PM
653 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
658 select ARCH_MAY_HAVE_PC_FDC
659 select ARCH_SPARSEMEM_ENABLE
660 select ARCH_USES_GETTIMEOFFSET
663 select HAVE_PATA_PLATFORM
665 select NEED_MACH_IO_H
666 select NEED_MACH_MEMORY_H
670 On the Acorn Risc-PC, Linux can support the internal IDE disk and
671 CD-ROM interface, serial and parallel port, and the floppy drive.
675 select ARCH_HAS_CPUFREQ
677 select ARCH_REQUIRE_GPIOLIB
678 select ARCH_SPARSEMEM_ENABLE
683 select GENERIC_CLOCKEVENTS
686 select NEED_MACH_GPIO_H
687 select NEED_MACH_MEMORY_H
690 Support for StrongARM 11x0 based boards.
693 bool "Samsung S3C24XX SoCs"
694 select ARCH_HAS_CPUFREQ
695 select ARCH_REQUIRE_GPIOLIB
698 select GENERIC_CLOCKEVENTS
700 select HAVE_S3C2410_I2C if I2C
701 select HAVE_S3C2410_WATCHDOG if WATCHDOG
702 select HAVE_S3C_RTC if RTC_CLASS
703 select MULTI_IRQ_HANDLER
704 select NEED_MACH_GPIO_H
705 select NEED_MACH_IO_H
707 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
708 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
709 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
710 Samsung SMDK2410 development board (and derivatives).
713 bool "Samsung S3C64XX"
714 select ARCH_HAS_CPUFREQ
715 select ARCH_REQUIRE_GPIOLIB
720 select GENERIC_CLOCKEVENTS
722 select HAVE_S3C2410_I2C if I2C
723 select HAVE_S3C2410_WATCHDOG if WATCHDOG
725 select NEED_MACH_GPIO_H
729 select S3C_GPIO_TRACK
730 select SAMSUNG_CLKSRC
731 select SAMSUNG_GPIOLIB_4BIT
732 select SAMSUNG_IRQ_VIC_TIMER
733 select USB_ARCH_HAS_OHCI
735 Samsung S3C64XX series based systems
738 bool "Samsung S5P6440 S5P6450"
742 select GENERIC_CLOCKEVENTS
744 select HAVE_S3C2410_I2C if I2C
745 select HAVE_S3C2410_WATCHDOG if WATCHDOG
746 select HAVE_S3C_RTC if RTC_CLASS
747 select NEED_MACH_GPIO_H
749 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
753 bool "Samsung S5PC100"
754 select ARCH_REQUIRE_GPIOLIB
758 select GENERIC_CLOCKEVENTS
760 select HAVE_S3C2410_I2C if I2C
761 select HAVE_S3C2410_WATCHDOG if WATCHDOG
762 select HAVE_S3C_RTC if RTC_CLASS
763 select NEED_MACH_GPIO_H
765 Samsung S5PC100 series based systems
768 bool "Samsung S5PV210/S5PC110"
769 select ARCH_HAS_CPUFREQ
770 select ARCH_HAS_HOLES_MEMORYMODEL
771 select ARCH_SPARSEMEM_ENABLE
775 select GENERIC_CLOCKEVENTS
777 select HAVE_S3C2410_I2C if I2C
778 select HAVE_S3C2410_WATCHDOG if WATCHDOG
779 select HAVE_S3C_RTC if RTC_CLASS
780 select NEED_MACH_GPIO_H
781 select NEED_MACH_MEMORY_H
783 Samsung S5PV210/S5PC110 series based systems
786 bool "Samsung EXYNOS"
787 select ARCH_HAS_CPUFREQ
788 select ARCH_HAS_HOLES_MEMORYMODEL
789 select ARCH_SPARSEMEM_ENABLE
793 select GENERIC_CLOCKEVENTS
795 select HAVE_S3C2410_I2C if I2C
796 select HAVE_S3C2410_WATCHDOG if WATCHDOG
797 select HAVE_S3C_RTC if RTC_CLASS
798 select NEED_MACH_GPIO_H
799 select NEED_MACH_MEMORY_H
801 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
805 select ARCH_USES_GETTIMEOFFSET
809 select NEED_MACH_MEMORY_H
814 Support for the StrongARM based Digital DNARD machine, also known
815 as "Shark" (<http://www.shark-linux.de/shark.html>).
818 bool "ST-Ericsson U300 Series"
820 select ARCH_REQUIRE_GPIOLIB
822 select ARM_PATCH_PHYS_VIRT
828 select GENERIC_CLOCKEVENTS
832 Support for ST-Ericsson U300 series mobile platforms.
836 select ARCH_HAS_HOLES_MEMORYMODEL
837 select ARCH_REQUIRE_GPIOLIB
839 select GENERIC_ALLOCATOR
840 select GENERIC_CLOCKEVENTS
841 select GENERIC_IRQ_CHIP
843 select NEED_MACH_GPIO_H
847 Support for TI's DaVinci platform.
852 select ARCH_HAS_CPUFREQ
853 select ARCH_HAS_HOLES_MEMORYMODEL
855 select ARCH_REQUIRE_GPIOLIB
858 select GENERIC_CLOCKEVENTS
859 select GENERIC_IRQ_CHIP
863 select NEED_MACH_IO_H if PCCARD
864 select NEED_MACH_MEMORY_H
866 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
870 menu "Multiple platform selection"
871 depends on ARCH_MULTIPLATFORM
873 comment "CPU Core family selection"
876 bool "ARMv4 based platforms (FA526, StrongARM)"
877 depends on !ARCH_MULTI_V6_V7
878 select ARCH_MULTI_V4_V5
880 config ARCH_MULTI_V4T
881 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
882 depends on !ARCH_MULTI_V6_V7
883 select ARCH_MULTI_V4_V5
886 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
887 depends on !ARCH_MULTI_V6_V7
888 select ARCH_MULTI_V4_V5
890 config ARCH_MULTI_V4_V5
894 bool "ARMv6 based platforms (ARM11)"
895 select ARCH_MULTI_V6_V7
899 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
901 select ARCH_MULTI_V6_V7
904 config ARCH_MULTI_V6_V7
907 config ARCH_MULTI_CPU_AUTO
908 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
914 # This is sorted alphabetically by mach-* pathname. However, plat-*
915 # Kconfigs may be included either alphabetically (according to the
916 # plat- suffix) or along side the corresponding mach-* source.
918 source "arch/arm/mach-mvebu/Kconfig"
920 source "arch/arm/mach-at91/Kconfig"
922 source "arch/arm/mach-bcm/Kconfig"
924 source "arch/arm/mach-bcm2835/Kconfig"
926 source "arch/arm/mach-clps711x/Kconfig"
928 source "arch/arm/mach-cns3xxx/Kconfig"
930 source "arch/arm/mach-davinci/Kconfig"
932 source "arch/arm/mach-dove/Kconfig"
934 source "arch/arm/mach-ep93xx/Kconfig"
936 source "arch/arm/mach-footbridge/Kconfig"
938 source "arch/arm/mach-gemini/Kconfig"
940 source "arch/arm/mach-highbank/Kconfig"
942 source "arch/arm/mach-integrator/Kconfig"
944 source "arch/arm/mach-iop32x/Kconfig"
946 source "arch/arm/mach-iop33x/Kconfig"
948 source "arch/arm/mach-iop13xx/Kconfig"
950 source "arch/arm/mach-ixp4xx/Kconfig"
952 source "arch/arm/mach-kirkwood/Kconfig"
954 source "arch/arm/mach-ks8695/Kconfig"
956 source "arch/arm/mach-msm/Kconfig"
958 source "arch/arm/mach-mv78xx0/Kconfig"
960 source "arch/arm/mach-imx/Kconfig"
962 source "arch/arm/mach-mxs/Kconfig"
964 source "arch/arm/mach-netx/Kconfig"
966 source "arch/arm/mach-nomadik/Kconfig"
968 source "arch/arm/plat-omap/Kconfig"
970 source "arch/arm/mach-omap1/Kconfig"
972 source "arch/arm/mach-omap2/Kconfig"
974 source "arch/arm/mach-orion5x/Kconfig"
976 source "arch/arm/mach-picoxcell/Kconfig"
978 source "arch/arm/mach-pxa/Kconfig"
979 source "arch/arm/plat-pxa/Kconfig"
981 source "arch/arm/mach-mmp/Kconfig"
983 source "arch/arm/mach-realview/Kconfig"
985 source "arch/arm/mach-sa1100/Kconfig"
987 source "arch/arm/plat-samsung/Kconfig"
989 source "arch/arm/mach-socfpga/Kconfig"
991 source "arch/arm/mach-spear/Kconfig"
993 source "arch/arm/mach-s3c24xx/Kconfig"
996 source "arch/arm/mach-s3c64xx/Kconfig"
999 source "arch/arm/mach-s5p64x0/Kconfig"
1001 source "arch/arm/mach-s5pc100/Kconfig"
1003 source "arch/arm/mach-s5pv210/Kconfig"
1005 source "arch/arm/mach-exynos/Kconfig"
1007 source "arch/arm/mach-shmobile/Kconfig"
1009 source "arch/arm/mach-sunxi/Kconfig"
1011 source "arch/arm/mach-prima2/Kconfig"
1013 source "arch/arm/mach-tegra/Kconfig"
1015 source "arch/arm/mach-u300/Kconfig"
1017 source "arch/arm/mach-ux500/Kconfig"
1019 source "arch/arm/mach-versatile/Kconfig"
1021 source "arch/arm/mach-vexpress/Kconfig"
1022 source "arch/arm/plat-versatile/Kconfig"
1024 source "arch/arm/mach-virt/Kconfig"
1026 source "arch/arm/mach-vt8500/Kconfig"
1028 source "arch/arm/mach-w90x900/Kconfig"
1030 source "arch/arm/mach-zynq/Kconfig"
1032 # Definitions to make life easier
1038 select GENERIC_CLOCKEVENTS
1044 select GENERIC_IRQ_CHIP
1047 config PLAT_ORION_LEGACY
1054 config PLAT_VERSATILE
1057 config ARM_TIMER_SP804
1060 select CLKSRC_OF if OF
1062 source arch/arm/mm/Kconfig
1066 default 16 if ARCH_EP93XX
1070 bool "Enable iWMMXt support" if !CPU_PJ4
1071 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1072 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1074 Enable support for iWMMXt context switching at run time if
1075 running on a CPU that supports it.
1079 depends on CPU_XSCALE
1082 config MULTI_IRQ_HANDLER
1085 Allow each machine to specify it's own IRQ handler at run time.
1088 source "arch/arm/Kconfig-nommu"
1091 config PJ4B_ERRATA_4742
1092 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1093 depends on CPU_PJ4B && MACH_ARMADA_370
1096 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1097 Event (WFE) IDLE states, a specific timing sensitivity exists between
1098 the retiring WFI/WFE instructions and the newly issued subsequent
1099 instructions. This sensitivity can result in a CPU hang scenario.
1101 The software must insert either a Data Synchronization Barrier (DSB)
1102 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1105 config ARM_ERRATA_326103
1106 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1109 Executing a SWP instruction to read-only memory does not set bit 11
1110 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1111 treat the access as a read, preventing a COW from occurring and
1112 causing the faulting task to livelock.
1114 config ARM_ERRATA_411920
1115 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1116 depends on CPU_V6 || CPU_V6K
1118 Invalidation of the Instruction Cache operation can
1119 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1120 It does not affect the MPCore. This option enables the ARM Ltd.
1121 recommended workaround.
1123 config ARM_ERRATA_430973
1124 bool "ARM errata: Stale prediction on replaced interworking branch"
1127 This option enables the workaround for the 430973 Cortex-A8
1128 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1129 interworking branch is replaced with another code sequence at the
1130 same virtual address, whether due to self-modifying code or virtual
1131 to physical address re-mapping, Cortex-A8 does not recover from the
1132 stale interworking branch prediction. This results in Cortex-A8
1133 executing the new code sequence in the incorrect ARM or Thumb state.
1134 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1135 and also flushes the branch target cache at every context switch.
1136 Note that setting specific bits in the ACTLR register may not be
1137 available in non-secure mode.
1139 config ARM_ERRATA_458693
1140 bool "ARM errata: Processor deadlock when a false hazard is created"
1142 depends on !ARCH_MULTIPLATFORM
1144 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1145 erratum. For very specific sequences of memory operations, it is
1146 possible for a hazard condition intended for a cache line to instead
1147 be incorrectly associated with a different cache line. This false
1148 hazard might then cause a processor deadlock. The workaround enables
1149 the L1 caching of the NEON accesses and disables the PLD instruction
1150 in the ACTLR register. Note that setting specific bits in the ACTLR
1151 register may not be available in non-secure mode.
1153 config ARM_ERRATA_460075
1154 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1156 depends on !ARCH_MULTIPLATFORM
1158 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1159 erratum. Any asynchronous access to the L2 cache may encounter a
1160 situation in which recent store transactions to the L2 cache are lost
1161 and overwritten with stale memory contents from external memory. The
1162 workaround disables the write-allocate mode for the L2 cache via the
1163 ACTLR register. Note that setting specific bits in the ACTLR register
1164 may not be available in non-secure mode.
1166 config ARM_ERRATA_742230
1167 bool "ARM errata: DMB operation may be faulty"
1168 depends on CPU_V7 && SMP
1169 depends on !ARCH_MULTIPLATFORM
1171 This option enables the workaround for the 742230 Cortex-A9
1172 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1173 between two write operations may not ensure the correct visibility
1174 ordering of the two writes. This workaround sets a specific bit in
1175 the diagnostic register of the Cortex-A9 which causes the DMB
1176 instruction to behave as a DSB, ensuring the correct behaviour of
1179 config ARM_ERRATA_742231
1180 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1181 depends on CPU_V7 && SMP
1182 depends on !ARCH_MULTIPLATFORM
1184 This option enables the workaround for the 742231 Cortex-A9
1185 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1186 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1187 accessing some data located in the same cache line, may get corrupted
1188 data due to bad handling of the address hazard when the line gets
1189 replaced from one of the CPUs at the same time as another CPU is
1190 accessing it. This workaround sets specific bits in the diagnostic
1191 register of the Cortex-A9 which reduces the linefill issuing
1192 capabilities of the processor.
1194 config PL310_ERRATA_588369
1195 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1196 depends on CACHE_L2X0
1198 The PL310 L2 cache controller implements three types of Clean &
1199 Invalidate maintenance operations: by Physical Address
1200 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1201 They are architecturally defined to behave as the execution of a
1202 clean operation followed immediately by an invalidate operation,
1203 both performing to the same memory location. This functionality
1204 is not correctly implemented in PL310 as clean lines are not
1205 invalidated as a result of these operations.
1207 config ARM_ERRATA_643719
1208 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1209 depends on CPU_V7 && SMP
1211 This option enables the workaround for the 643719 Cortex-A9 (prior to
1212 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1213 register returns zero when it should return one. The workaround
1214 corrects this value, ensuring cache maintenance operations which use
1215 it behave as intended and avoiding data corruption.
1217 config ARM_ERRATA_720789
1218 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1221 This option enables the workaround for the 720789 Cortex-A9 (prior to
1222 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1223 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1224 As a consequence of this erratum, some TLB entries which should be
1225 invalidated are not, resulting in an incoherency in the system page
1226 tables. The workaround changes the TLB flushing routines to invalidate
1227 entries regardless of the ASID.
1229 config PL310_ERRATA_727915
1230 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1231 depends on CACHE_L2X0
1233 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1234 operation (offset 0x7FC). This operation runs in background so that
1235 PL310 can handle normal accesses while it is in progress. Under very
1236 rare circumstances, due to this erratum, write data can be lost when
1237 PL310 treats a cacheable write transaction during a Clean &
1238 Invalidate by Way operation.
1240 config ARM_ERRATA_743622
1241 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1243 depends on !ARCH_MULTIPLATFORM
1245 This option enables the workaround for the 743622 Cortex-A9
1246 (r2p*) erratum. Under very rare conditions, a faulty
1247 optimisation in the Cortex-A9 Store Buffer may lead to data
1248 corruption. This workaround sets a specific bit in the diagnostic
1249 register of the Cortex-A9 which disables the Store Buffer
1250 optimisation, preventing the defect from occurring. This has no
1251 visible impact on the overall performance or power consumption of the
1254 config ARM_ERRATA_751472
1255 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1257 depends on !ARCH_MULTIPLATFORM
1259 This option enables the workaround for the 751472 Cortex-A9 (prior
1260 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1261 completion of a following broadcasted operation if the second
1262 operation is received by a CPU before the ICIALLUIS has completed,
1263 potentially leading to corrupted entries in the cache or TLB.
1265 config PL310_ERRATA_753970
1266 bool "PL310 errata: cache sync operation may be faulty"
1267 depends on CACHE_PL310
1269 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1271 Under some condition the effect of cache sync operation on
1272 the store buffer still remains when the operation completes.
1273 This means that the store buffer is always asked to drain and
1274 this prevents it from merging any further writes. The workaround
1275 is to replace the normal offset of cache sync operation (0x730)
1276 by another offset targeting an unmapped PL310 register 0x740.
1277 This has the same effect as the cache sync operation: store buffer
1278 drain and waiting for all buffers empty.
1280 config ARM_ERRATA_754322
1281 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1284 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1285 r3p*) erratum. A speculative memory access may cause a page table walk
1286 which starts prior to an ASID switch but completes afterwards. This
1287 can populate the micro-TLB with a stale entry which may be hit with
1288 the new ASID. This workaround places two dsb instructions in the mm
1289 switching code so that no page table walks can cross the ASID switch.
1291 config ARM_ERRATA_754327
1292 bool "ARM errata: no automatic Store Buffer drain"
1293 depends on CPU_V7 && SMP
1295 This option enables the workaround for the 754327 Cortex-A9 (prior to
1296 r2p0) erratum. The Store Buffer does not have any automatic draining
1297 mechanism and therefore a livelock may occur if an external agent
1298 continuously polls a memory location waiting to observe an update.
1299 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1300 written polling loops from denying visibility of updates to memory.
1302 config ARM_ERRATA_364296
1303 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1304 depends on CPU_V6 && !SMP
1306 This options enables the workaround for the 364296 ARM1136
1307 r0p2 erratum (possible cache data corruption with
1308 hit-under-miss enabled). It sets the undocumented bit 31 in
1309 the auxiliary control register and the FI bit in the control
1310 register, thus disabling hit-under-miss without putting the
1311 processor into full low interrupt latency mode. ARM11MPCore
1314 config ARM_ERRATA_764369
1315 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1316 depends on CPU_V7 && SMP
1318 This option enables the workaround for erratum 764369
1319 affecting Cortex-A9 MPCore with two or more processors (all
1320 current revisions). Under certain timing circumstances, a data
1321 cache line maintenance operation by MVA targeting an Inner
1322 Shareable memory region may fail to proceed up to either the
1323 Point of Coherency or to the Point of Unification of the
1324 system. This workaround adds a DSB instruction before the
1325 relevant cache maintenance functions and sets a specific bit
1326 in the diagnostic control register of the SCU.
1328 config PL310_ERRATA_769419
1329 bool "PL310 errata: no automatic Store Buffer drain"
1330 depends on CACHE_L2X0
1332 On revisions of the PL310 prior to r3p2, the Store Buffer does
1333 not automatically drain. This can cause normal, non-cacheable
1334 writes to be retained when the memory system is idle, leading
1335 to suboptimal I/O performance for drivers using coherent DMA.
1336 This option adds a write barrier to the cpu_idle loop so that,
1337 on systems with an outer cache, the store buffer is drained
1340 config ARM_ERRATA_775420
1341 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1344 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1345 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1346 operation aborts with MMU exception, it might cause the processor
1347 to deadlock. This workaround puts DSB before executing ISB if
1348 an abort may occur on cache maintenance.
1350 config ARM_ERRATA_798181
1351 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1352 depends on CPU_V7 && SMP
1354 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1355 adequately shooting down all use of the old entries. This
1356 option enables the Linux kernel workaround for this erratum
1357 which sends an IPI to the CPUs that are running the same ASID
1358 as the one being invalidated.
1362 source "arch/arm/common/Kconfig"
1372 Find out whether you have ISA slots on your motherboard. ISA is the
1373 name of a bus system, i.e. the way the CPU talks to the other stuff
1374 inside your box. Other bus systems are PCI, EISA, MicroChannel
1375 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1376 newer boards don't support it. If you have ISA, say Y, otherwise N.
1378 # Select ISA DMA controller support
1383 # Select ISA DMA interface
1388 bool "PCI support" if MIGHT_HAVE_PCI
1390 Find out whether you have a PCI motherboard. PCI is the name of a
1391 bus system, i.e. the way the CPU talks to the other stuff inside
1392 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1393 VESA. If you have PCI, say Y, otherwise N.
1399 config PCI_NANOENGINE
1400 bool "BSE nanoEngine PCI support"
1401 depends on SA1100_NANOENGINE
1403 Enable PCI on the BSE nanoEngine board.
1408 # Select the host bridge type
1409 config PCI_HOST_VIA82C505
1411 depends on PCI && ARCH_SHARK
1414 config PCI_HOST_ITE8152
1416 depends on PCI && MACH_ARMCORE
1420 source "drivers/pci/Kconfig"
1422 source "drivers/pcmcia/Kconfig"
1426 menu "Kernel Features"
1431 This option should be selected by machines which have an SMP-
1434 The only effect of this option is to make the SMP-related
1435 options available to the user for configuration.
1438 bool "Symmetric Multi-Processing"
1439 depends on CPU_V6K || CPU_V7
1440 depends on GENERIC_CLOCKEVENTS
1443 select USE_GENERIC_SMP_HELPERS
1445 This enables support for systems with more than one CPU. If you have
1446 a system with only one CPU, like most personal computers, say N. If
1447 you have a system with more than one CPU, say Y.
1449 If you say N here, the kernel will run on single and multiprocessor
1450 machines, but will use only one CPU of a multiprocessor machine. If
1451 you say Y here, the kernel will run on many, but not all, single
1452 processor machines. On a single processor machine, the kernel will
1453 run faster if you say N here.
1455 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1456 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1457 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1459 If you don't know what to do here, say N.
1462 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1463 depends on SMP && !XIP_KERNEL
1466 SMP kernels contain instructions which fail on non-SMP processors.
1467 Enabling this option allows the kernel to modify itself to make
1468 these instructions safe. Disabling it allows about 1K of space
1471 If you don't know what to do here, say Y.
1473 config ARM_CPU_TOPOLOGY
1474 bool "Support cpu topology definition"
1475 depends on SMP && CPU_V7
1478 Support ARM cpu topology definition. The MPIDR register defines
1479 affinity between processors which is then used to describe the cpu
1480 topology of an ARM System.
1483 bool "Multi-core scheduler support"
1484 depends on ARM_CPU_TOPOLOGY
1486 Multi-core scheduler support improves the CPU scheduler's decision
1487 making when dealing with multi-core CPU chips at a cost of slightly
1488 increased overhead in some places. If unsure say N here.
1491 bool "SMT scheduler support"
1492 depends on ARM_CPU_TOPOLOGY
1494 Improves the CPU scheduler's decision making when dealing with
1495 MultiThreading at a cost of slightly increased overhead in some
1496 places. If unsure say N here.
1498 config DISABLE_CPU_SCHED_DOMAIN_BALANCE
1499 bool "(EXPERIMENTAL) Disable CPU level scheduler load-balancing"
1501 Disables scheduler load-balancing at CPU sched domain level.
1504 bool "(EXPERIMENTAL) Heterogenous multiprocessor scheduling"
1505 depends on DISABLE_CPU_SCHED_DOMAIN_BALANCE && SCHED_MC && FAIR_GROUP_SCHED && !SCHED_AUTOGROUP
1507 Experimental scheduler optimizations for heterogeneous platforms.
1508 Attempts to introspectively select task affinity to optimize power
1509 and performance. Basic support for multiple (>2) cpu types is in place,
1510 but it has only been tested with two types of cpus.
1511 There is currently no support for migration of task groups, hence
1512 !SCHED_AUTOGROUP. Furthermore, normal load-balancing must be disabled
1513 between cpus of different type (DISABLE_CPU_SCHED_DOMAIN_BALANCE).
1514 When turned on, this option adds sys/kernel/hmp directory which
1515 contains the following files:
1516 up_threshold - the load average threshold used for up migration
1518 down_threshold - the load average threshold used for down migration
1520 hmp_domains - a list of cpumasks for the present HMP domains,
1521 starting with the 'biggest' and ending with the
1523 Note that both the threshold files can be written at runtime to
1524 control scheduler behaviour.
1526 config SCHED_HMP_PRIO_FILTER
1527 bool "(EXPERIMENTAL) Filter HMP migrations by task priority"
1528 depends on SCHED_HMP
1530 Enables task priority based HMP migration filter. Any task with
1531 a NICE value above the threshold will always be on low-power cpus
1532 with less compute capacity.
1534 config SCHED_HMP_PRIO_FILTER_VAL
1535 int "NICE priority threshold"
1537 depends on SCHED_HMP_PRIO_FILTER
1539 config HMP_FAST_CPU_MASK
1540 string "HMP scheduler fast CPU mask"
1541 depends on SCHED_HMP
1543 Leave empty to use device tree information.
1544 Specify the cpuids of the fast CPUs in the system as a list string,
1545 e.g. cpuid 0+1 should be specified as 0-1.
1547 config HMP_SLOW_CPU_MASK
1548 string "HMP scheduler slow CPU mask"
1549 depends on SCHED_HMP
1551 Leave empty to use device tree information.
1552 Specify the cpuids of the slow CPUs in the system as a list string,
1553 e.g. cpuid 0+1 should be specified as 0-1.
1555 config HMP_VARIABLE_SCALE
1556 bool "Allows changing the load tracking scale through sysfs"
1557 depends on SCHED_HMP
1559 When turned on, this option exports the load average period value
1560 for the load tracking patches through sysfs.
1561 The values can be modified to change the rate of load accumulation
1562 used for HMP migration. 'load_avg_period_ms' is the time in ms to
1563 reach a load average of 0.5 for an idle task of 0 load average
1564 ratio which becomes 100% busy.
1565 For example, with load_avg_period_ms = 128 and up_threshold = 512,
1566 a running task with a load of 0 will be migrated to a bigger CPU after
1567 128ms, because after 128ms its load_avg_ratio is 0.5 and the real
1568 up_threshold is 0.5.
1569 This patch has the same behavior as changing the Y of the load
1570 average computation to
1571 (1002/1024)^(LOAD_AVG_PERIOD/load_avg_period_ms)
1572 but removes intermediate overflows in computation.
1574 config HMP_FREQUENCY_INVARIANT_SCALE
1575 bool "(EXPERIMENTAL) Frequency-Invariant Tracked Load for HMP"
1576 depends on SCHED_HMP && CPU_FREQ
1578 Scales the current load contribution in line with the frequency
1579 of the CPU that the task was executed on.
1580 In this version, we use a simple linear scale derived from the
1581 maximum frequency reported by CPUFreq.
1582 Restricting tracked load to be scaled by the CPU's frequency
1583 represents the consumption of possible compute capacity
1584 (rather than consumption of actual instantaneous capacity as
1585 normal) and allows the HMP migration's simple threshold
1586 migration strategy to interact more predictably with CPUFreq's
1587 asynchronous compute capacity changes.
1589 config SCHED_HMP_LITTLE_PACKING
1590 bool "Small task packing for HMP"
1591 depends on SCHED_HMP
1594 Allows the HMP Scheduler to pack small tasks into CPUs in the
1595 smallest HMP domain.
1596 Controlled by two sysfs files in sys/kernel/hmp.
1597 packing_enable: 1 to enable, 0 to disable packing. Default 1.
1598 packing_limit: runqueue load ratio where a RQ is considered
1599 to be full. Default is NICE_0_LOAD * 9/8.
1604 This option enables support for the ARM system coherency unit
1606 config HAVE_ARM_ARCH_TIMER
1607 bool "Architected timer support"
1609 select ARM_ARCH_TIMER
1611 This option enables support for the ARM architected timer
1616 select CLKSRC_OF if OF
1618 This options enables support for the ARM timer and watchdog unit
1621 bool "Multi-Cluster Power Management"
1622 depends on CPU_V7 && SMP
1624 This option provides the common power management infrastructure
1625 for (multi-)cluster based systems, such as big.LITTLE based
1629 bool "big.LITTLE support (Experimental)"
1630 depends on CPU_V7 && SMP
1633 This option enables support for the big.LITTLE architecture.
1636 bool "big.LITTLE switcher support"
1637 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1639 select ARM_CPU_SUSPEND
1641 The big.LITTLE "switcher" provides the core functionality to
1642 transparently handle transition between a cluster of A15's
1643 and a cluster of A7's in a big.LITTLE system.
1645 config BL_SWITCHER_DUMMY_IF
1646 tristate "Simple big.LITTLE switcher user interface"
1647 depends on BL_SWITCHER && DEBUG_KERNEL
1649 This is a simple and dummy char dev interface to control
1650 the big.LITTLE switcher core code. It is meant for
1651 debugging purposes only.
1654 prompt "Memory split"
1657 Select the desired split between kernel and user memory.
1659 If you are not absolutely sure what you are doing, leave this
1663 bool "3G/1G user/kernel split"
1665 bool "2G/2G user/kernel split"
1667 bool "1G/3G user/kernel split"
1672 default 0x40000000 if VMSPLIT_1G
1673 default 0x80000000 if VMSPLIT_2G
1677 int "Maximum number of CPUs (2-32)"
1683 bool "Support for hot-pluggable CPUs"
1684 depends on SMP && HOTPLUG
1686 Say Y here to experiment with turning CPUs off and on. CPUs
1687 can be controlled through /sys/devices/system/cpu.
1690 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1693 Say Y here if you want Linux to communicate with system firmware
1694 implementing the PSCI specification for CPU-centric power
1695 management operations described in ARM document number ARM DEN
1696 0022A ("Power State Coordination Interface System Software on
1700 bool "Use local timer interrupts"
1704 Enable support for local timers on SMP platforms, rather then the
1705 legacy IPI broadcast method. Local timers allows the system
1706 accounting to be spread across the timer interval, preventing a
1707 "thundering herd" at every timer tick.
1709 # The GPIO number here must be sorted by descending number. In case of
1710 # a multiplatform kernel, we just want the highest value required by the
1711 # selected platforms.
1714 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1715 default 512 if SOC_OMAP5
1716 default 392 if ARCH_U8500
1717 default 352 if ARCH_VT8500
1718 default 288 if ARCH_SUNXI
1719 default 264 if MACH_H4700
1722 Maximum number of GPIOs in the system.
1724 If unsure, leave the default value.
1726 source kernel/Kconfig.preempt
1730 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1731 ARCH_S5PV210 || ARCH_EXYNOS4
1732 default AT91_TIMER_HZ if ARCH_AT91
1733 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1737 def_bool HIGH_RES_TIMERS
1739 config THUMB2_KERNEL
1740 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1741 depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1742 default y if CPU_THUMBONLY
1744 select ARM_ASM_UNIFIED
1747 By enabling this option, the kernel will be compiled in
1748 Thumb-2 mode. A compiler/assembler that understand the unified
1749 ARM-Thumb syntax is needed.
1753 config THUMB2_AVOID_R_ARM_THM_JUMP11
1754 bool "Work around buggy Thumb-2 short branch relocations in gas"
1755 depends on THUMB2_KERNEL && MODULES
1758 Various binutils versions can resolve Thumb-2 branches to
1759 locally-defined, preemptible global symbols as short-range "b.n"
1760 branch instructions.
1762 This is a problem, because there's no guarantee the final
1763 destination of the symbol, or any candidate locations for a
1764 trampoline, are within range of the branch. For this reason, the
1765 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1766 relocation in modules at all, and it makes little sense to add
1769 The symptom is that the kernel fails with an "unsupported
1770 relocation" error when loading some modules.
1772 Until fixed tools are available, passing
1773 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1774 code which hits this problem, at the cost of a bit of extra runtime
1775 stack usage in some cases.
1777 The problem is described in more detail at:
1778 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1780 Only Thumb-2 kernels are affected.
1782 Unless you are sure your tools don't have this problem, say Y.
1784 config ARM_ASM_UNIFIED
1788 bool "Use the ARM EABI to compile the kernel"
1790 This option allows for the kernel to be compiled using the latest
1791 ARM ABI (aka EABI). This is only useful if you are using a user
1792 space environment that is also compiled with EABI.
1794 Since there are major incompatibilities between the legacy ABI and
1795 EABI, especially with regard to structure member alignment, this
1796 option also changes the kernel syscall calling convention to
1797 disambiguate both ABIs and allow for backward compatibility support
1798 (selected with CONFIG_OABI_COMPAT).
1800 To use this you need GCC version 4.0.0 or later.
1803 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1804 depends on AEABI && !THUMB2_KERNEL
1807 This option preserves the old syscall interface along with the
1808 new (ARM EABI) one. It also provides a compatibility layer to
1809 intercept syscalls that have structure arguments which layout
1810 in memory differs between the legacy ABI and the new ARM EABI
1811 (only for non "thumb" binaries). This option adds a tiny
1812 overhead to all syscalls and produces a slightly larger kernel.
1813 If you know you'll be using only pure EABI user space then you
1814 can say N here. If this option is not selected and you attempt
1815 to execute a legacy ABI binary then the result will be
1816 UNPREDICTABLE (in fact it can be predicted that it won't work
1817 at all). If in doubt say Y.
1819 config ARCH_HAS_HOLES_MEMORYMODEL
1822 config ARCH_SPARSEMEM_ENABLE
1825 config ARCH_SPARSEMEM_DEFAULT
1826 def_bool ARCH_SPARSEMEM_ENABLE
1828 config ARCH_SELECT_MEMORY_MODEL
1829 def_bool ARCH_SPARSEMEM_ENABLE
1831 config HAVE_ARCH_PFN_VALID
1832 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1835 bool "High Memory Support"
1838 The address space of ARM processors is only 4 Gigabytes large
1839 and it has to accommodate user address space, kernel address
1840 space as well as some memory mapped IO. That means that, if you
1841 have a large amount of physical memory and/or IO, not all of the
1842 memory can be "permanently mapped" by the kernel. The physical
1843 memory that is not permanently mapped is called "high memory".
1845 Depending on the selected kernel/user memory split, minimum
1846 vmalloc space and actual amount of RAM, you may not need this
1847 option which should result in a slightly faster kernel.
1852 bool "Allocate 2nd-level pagetables from highmem"
1855 config HW_PERF_EVENTS
1856 bool "Enable hardware performance counter support for perf events"
1857 depends on PERF_EVENTS
1860 Enable hardware performance counter support for perf events. If
1861 disabled, perf events will use software events only.
1865 config FORCE_MAX_ZONEORDER
1866 int "Maximum zone order" if ARCH_SHMOBILE
1867 range 11 64 if ARCH_SHMOBILE
1868 default "12" if SOC_AM33XX
1869 default "9" if SA1111
1872 The kernel memory allocator divides physically contiguous memory
1873 blocks into "zones", where each zone is a power of two number of
1874 pages. This option selects the largest power of two that the kernel
1875 keeps in the memory allocator. If you need to allocate very large
1876 blocks of physically contiguous memory, then you may need to
1877 increase this value.
1879 This config option is actually maximum order plus one. For example,
1880 a value of 11 means that the largest free memory block is 2^10 pages.
1882 config ALIGNMENT_TRAP
1884 depends on CPU_CP15_MMU
1885 default y if !ARCH_EBSA110
1886 select HAVE_PROC_CPU if PROC_FS
1888 ARM processors cannot fetch/store information which is not
1889 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1890 address divisible by 4. On 32-bit ARM processors, these non-aligned
1891 fetch/store instructions will be emulated in software if you say
1892 here, which has a severe performance impact. This is necessary for
1893 correct operation of some network protocols. With an IP-only
1894 configuration it is safe to say N, otherwise say Y.
1896 config UACCESS_WITH_MEMCPY
1897 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1899 default y if CPU_FEROCEON
1901 Implement faster copy_to_user and clear_user methods for CPU
1902 cores where a 8-word STM instruction give significantly higher
1903 memory write throughput than a sequence of individual 32bit stores.
1905 A possible side effect is a slight increase in scheduling latency
1906 between threads sharing the same address space if they invoke
1907 such copy operations with large buffers.
1909 However, if the CPU data cache is using a write-allocate mode,
1910 this option is unlikely to provide any performance gain.
1914 prompt "Enable seccomp to safely compute untrusted bytecode"
1916 This kernel feature is useful for number crunching applications
1917 that may need to compute untrusted bytecode during their
1918 execution. By using pipes or other transports made available to
1919 the process as file descriptors supporting the read/write
1920 syscalls, it's possible to isolate those applications in
1921 their own address space using seccomp. Once seccomp is
1922 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1923 and the task is only allowed to execute a few safe syscalls
1924 defined by each seccomp mode.
1926 config CC_STACKPROTECTOR
1927 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1929 This option turns on the -fstack-protector GCC feature. This
1930 feature puts, at the beginning of functions, a canary value on
1931 the stack just before the return address, and validates
1932 the value just before actually returning. Stack based buffer
1933 overflows (that need to overwrite this return address) now also
1934 overwrite the canary, which gets detected and the attack is then
1935 neutralized via a kernel panic.
1936 This feature requires gcc version 4.2 or above.
1943 bool "Xen guest support on ARM (EXPERIMENTAL)"
1944 depends on ARM && AEABI && OF
1945 depends on CPU_V7 && !CPU_V6
1946 depends on !GENERIC_ATOMIC64
1949 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1951 config ARM_FLUSH_CONSOLE_ON_RESTART
1952 bool "Force flush the console on restart"
1954 If the console is locked while the system is rebooted, the messages
1955 in the temporary logbuffer would not have propogated to all the
1956 console drivers. This option forces the console lock to be
1957 released if it failed to be acquired, which will cause all the
1958 pending messages to be flushed.
1965 bool "Flattened Device Tree support"
1968 select OF_EARLY_FLATTREE
1970 Include support for flattened device tree machine descriptions.
1973 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1976 This is the traditional way of passing data to the kernel at boot
1977 time. If you are solely relying on the flattened device tree (or
1978 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1979 to remove ATAGS support from your kernel binary. If unsure,
1982 config DEPRECATED_PARAM_STRUCT
1983 bool "Provide old way to pass kernel parameters"
1986 This was deprecated in 2001 and announced to live on for 5 years.
1987 Some old boot loaders still use this way.
1989 config BUILD_ARM_APPENDED_DTB_IMAGE
1990 bool "Build a concatenated zImage/dtb by default"
1993 Enabling this option will cause a concatenated zImage and DTB to
1994 be built by default (instead of a standalone zImage.) The image
1995 will built in arch/arm/boot/zImage-dtb.<dtb name>
1997 config BUILD_ARM_APPENDED_DTB_IMAGE_NAME
1998 string "Default dtb name"
1999 depends on BUILD_ARM_APPENDED_DTB_IMAGE
2001 name of the dtb to append when building a concatenated
2004 # Compressed boot loader in ROM. Yes, we really want to ask about
2005 # TEXT and BSS so we preserve their values in the config files.
2006 config ZBOOT_ROM_TEXT
2007 hex "Compressed ROM boot loader base address"
2010 The physical address at which the ROM-able zImage is to be
2011 placed in the target. Platforms which normally make use of
2012 ROM-able zImage formats normally set this to a suitable
2013 value in their defconfig file.
2015 If ZBOOT_ROM is not enabled, this has no effect.
2017 config ZBOOT_ROM_BSS
2018 hex "Compressed ROM boot loader BSS address"
2021 The base address of an area of read/write memory in the target
2022 for the ROM-able zImage which must be available while the
2023 decompressor is running. It must be large enough to hold the
2024 entire decompressed kernel plus an additional 128 KiB.
2025 Platforms which normally make use of ROM-able zImage formats
2026 normally set this to a suitable value in their defconfig file.
2028 If ZBOOT_ROM is not enabled, this has no effect.
2031 bool "Compressed boot loader in ROM/flash"
2032 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
2034 Say Y here if you intend to execute your compressed kernel image
2035 (zImage) directly from ROM or flash. If unsure, say N.
2038 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
2039 depends on ZBOOT_ROM && ARCH_SH7372
2040 default ZBOOT_ROM_NONE
2042 Include experimental SD/MMC loading code in the ROM-able zImage.
2043 With this enabled it is possible to write the ROM-able zImage
2044 kernel image to an MMC or SD card and boot the kernel straight
2045 from the reset vector. At reset the processor Mask ROM will load
2046 the first part of the ROM-able zImage which in turn loads the
2047 rest the kernel image to RAM.
2049 config ZBOOT_ROM_NONE
2050 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
2052 Do not load image from SD or MMC
2054 config ZBOOT_ROM_MMCIF
2055 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
2057 Load image from MMCIF hardware block.
2059 config ZBOOT_ROM_SH_MOBILE_SDHI
2060 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
2062 Load image from SDHI hardware block
2066 config ARM_APPENDED_DTB
2067 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
2068 depends on OF && !ZBOOT_ROM
2070 With this option, the boot code will look for a device tree binary
2071 (DTB) appended to zImage
2072 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
2074 This is meant as a backward compatibility convenience for those
2075 systems with a bootloader that can't be upgraded to accommodate
2076 the documented boot protocol using a device tree.
2078 Beware that there is very little in terms of protection against
2079 this option being confused by leftover garbage in memory that might
2080 look like a DTB header after a reboot if no actual DTB is appended
2081 to zImage. Do not leave this option active in a production kernel
2082 if you don't intend to always append a DTB. Proper passing of the
2083 location into r2 of a bootloader provided DTB is always preferable
2086 config ARM_ATAG_DTB_COMPAT
2087 bool "Supplement the appended DTB with traditional ATAG information"
2088 depends on ARM_APPENDED_DTB
2090 Some old bootloaders can't be updated to a DTB capable one, yet
2091 they provide ATAGs with memory configuration, the ramdisk address,
2092 the kernel cmdline string, etc. Such information is dynamically
2093 provided by the bootloader and can't always be stored in a static
2094 DTB. To allow a device tree enabled kernel to be used with such
2095 bootloaders, this option allows zImage to extract the information
2096 from the ATAG list and store it at run time into the appended DTB.
2099 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2100 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2102 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2103 bool "Use bootloader kernel arguments if available"
2105 Uses the command-line options passed by the boot loader instead of
2106 the device tree bootargs property. If the boot loader doesn't provide
2107 any, the device tree bootargs property will be used.
2109 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2110 bool "Extend with bootloader kernel arguments"
2112 The command-line arguments provided by the boot loader will be
2113 appended to the the device tree bootargs property.
2118 string "Default kernel command string"
2121 On some architectures (EBSA110 and CATS), there is currently no way
2122 for the boot loader to pass arguments to the kernel. For these
2123 architectures, you should supply some command-line options at build
2124 time by entering them here. As a minimum, you should specify the
2125 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2128 prompt "Kernel command line type" if CMDLINE != ""
2129 default CMDLINE_FROM_BOOTLOADER
2132 config CMDLINE_FROM_BOOTLOADER
2133 bool "Use bootloader kernel arguments if available"
2135 Uses the command-line options passed by the boot loader. If
2136 the boot loader doesn't provide any, the default kernel command
2137 string provided in CMDLINE will be used.
2139 config CMDLINE_EXTEND
2140 bool "Extend bootloader kernel arguments"
2142 The command-line arguments provided by the boot loader will be
2143 appended to the default kernel command string.
2145 config CMDLINE_FORCE
2146 bool "Always use the default kernel command string"
2148 Always use the default kernel command string, even if the boot
2149 loader passes other arguments to the kernel.
2150 This is useful if you cannot or don't want to change the
2151 command-line options your boot loader passes to the kernel.
2155 bool "Kernel Execute-In-Place from ROM"
2156 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2158 Execute-In-Place allows the kernel to run from non-volatile storage
2159 directly addressable by the CPU, such as NOR flash. This saves RAM
2160 space since the text section of the kernel is not loaded from flash
2161 to RAM. Read-write sections, such as the data section and stack,
2162 are still copied to RAM. The XIP kernel is not compressed since
2163 it has to run directly from flash, so it will take more space to
2164 store it. The flash address used to link the kernel object files,
2165 and for storing it, is configuration dependent. Therefore, if you
2166 say Y here, you must know the proper physical address where to
2167 store the kernel image depending on your own flash memory usage.
2169 Also note that the make target becomes "make xipImage" rather than
2170 "make zImage" or "make Image". The final kernel binary to put in
2171 ROM memory will be arch/arm/boot/xipImage.
2175 config XIP_PHYS_ADDR
2176 hex "XIP Kernel Physical Location"
2177 depends on XIP_KERNEL
2178 default "0x00080000"
2180 This is the physical address in your flash memory the kernel will
2181 be linked for and stored to. This address is dependent on your
2185 bool "Kexec system call (EXPERIMENTAL)"
2186 depends on (!SMP || PM_SLEEP_SMP)
2188 kexec is a system call that implements the ability to shutdown your
2189 current kernel, and to start another kernel. It is like a reboot
2190 but it is independent of the system firmware. And like a reboot
2191 you can start any kernel with it, not just Linux.
2193 It is an ongoing process to be certain the hardware in a machine
2194 is properly shutdown, so do not be surprised if this code does not
2195 initially work for you. It may help to enable device hotplugging
2199 bool "Export atags in procfs"
2200 depends on ATAGS && KEXEC
2203 Should the atags used to boot the kernel be exported in an "atags"
2204 file in procfs. Useful with kexec.
2207 bool "Build kdump crash kernel (EXPERIMENTAL)"
2209 Generate crash dump after being started by kexec. This should
2210 be normally only set in special crash dump kernels which are
2211 loaded in the main kernel with kexec-tools into a specially
2212 reserved region and then later executed after a crash by
2213 kdump/kexec. The crash dump kernel must be compiled to a
2214 memory address not used by the main kernel
2216 For more details see Documentation/kdump/kdump.txt
2218 config AUTO_ZRELADDR
2219 bool "Auto calculation of the decompressed kernel image address"
2220 depends on !ZBOOT_ROM && !ARCH_U300
2222 ZRELADDR is the physical address where the decompressed kernel
2223 image will be placed. If AUTO_ZRELADDR is selected, the address
2224 will be determined at run-time by masking the current IP with
2225 0xf8000000. This assumes the zImage being placed in the first 128MB
2226 from start of memory.
2230 menu "CPU Power Management"
2233 source "drivers/cpufreq/Kconfig"
2238 Internal configuration node for common cpufreq on Samsung SoC
2240 config CPU_FREQ_S3C24XX
2241 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2242 depends on ARCH_S3C24XX && CPU_FREQ
2245 This enables the CPUfreq driver for the Samsung S3C24XX family
2248 For details, take a look at <file:Documentation/cpu-freq>.
2252 config CPU_FREQ_S3C24XX_PLL
2253 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2254 depends on CPU_FREQ_S3C24XX
2256 Compile in support for changing the PLL frequency from the
2257 S3C24XX series CPUfreq driver. The PLL takes time to settle
2258 after a frequency change, so by default it is not enabled.
2260 This also means that the PLL tables for the selected CPU(s) will
2261 be built which may increase the size of the kernel image.
2263 config CPU_FREQ_S3C24XX_DEBUG
2264 bool "Debug CPUfreq Samsung driver core"
2265 depends on CPU_FREQ_S3C24XX
2267 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2269 config CPU_FREQ_S3C24XX_IODEBUG
2270 bool "Debug CPUfreq Samsung driver IO timing"
2271 depends on CPU_FREQ_S3C24XX
2273 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2275 config CPU_FREQ_S3C24XX_DEBUGFS
2276 bool "Export debugfs for CPUFreq"
2277 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2279 Export status information via debugfs.
2283 source "drivers/cpuidle/Kconfig"
2287 menu "Floating point emulation"
2289 comment "At least one emulation must be selected"
2292 bool "NWFPE math emulation"
2293 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2295 Say Y to include the NWFPE floating point emulator in the kernel.
2296 This is necessary to run most binaries. Linux does not currently
2297 support floating point hardware so you need to say Y here even if
2298 your machine has an FPA or floating point co-processor podule.
2300 You may say N here if you are going to load the Acorn FPEmulator
2301 early in the bootup.
2304 bool "Support extended precision"
2305 depends on FPE_NWFPE
2307 Say Y to include 80-bit support in the kernel floating-point
2308 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2309 Note that gcc does not generate 80-bit operations by default,
2310 so in most cases this option only enlarges the size of the
2311 floating point emulator without any good reason.
2313 You almost surely want to say N here.
2316 bool "FastFPE math emulation (EXPERIMENTAL)"
2317 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2319 Say Y here to include the FAST floating point emulator in the kernel.
2320 This is an experimental much faster emulator which now also has full
2321 precision for the mantissa. It does not support any exceptions.
2322 It is very simple, and approximately 3-6 times faster than NWFPE.
2324 It should be sufficient for most programs. It may be not suitable
2325 for scientific calculations, but you have to check this for yourself.
2326 If you do not feel you need a faster FP emulation you should better
2330 bool "VFP-format floating point maths"
2331 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2333 Say Y to include VFP support code in the kernel. This is needed
2334 if your hardware includes a VFP unit.
2336 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2337 release notes and additional status information.
2339 Say N if your target does not have VFP hardware.
2347 bool "Advanced SIMD (NEON) Extension support"
2348 depends on VFPv3 && CPU_V7
2350 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2355 menu "Userspace binary formats"
2357 source "fs/Kconfig.binfmt"
2360 tristate "RISC OS personality"
2363 Say Y here to include the kernel code necessary if you want to run
2364 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2365 experimental; if this sounds frightening, say N and sleep in peace.
2366 You can also say M here to compile this support as a module (which
2367 will be called arthur).
2371 menu "Power management options"
2373 source "kernel/power/Kconfig"
2375 config ARCH_SUSPEND_POSSIBLE
2376 depends on !ARCH_S5PC100
2377 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2378 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2381 config ARM_CPU_SUSPEND
2386 source "net/Kconfig"
2388 source "drivers/Kconfig"
2392 source "arch/arm/Kconfig.debug"
2394 source "security/Kconfig"
2396 source "crypto/Kconfig"
2398 source "lib/Kconfig"
2400 source "arch/arm/kvm/Kconfig"