5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if !XIP_KERNEL
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
33 The ARM series is a line of low-power-consumption RISC chip designs
34 licensed by ARM Ltd and targeted at embedded applications and
35 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
36 manufactured, but legacy ARM-based PC hardware remains popular in
37 Europe. There is an ARM Linux project with a web page at
38 <http://www.arm.linux.org.uk/>.
40 config ARM_HAS_SG_CHAIN
49 config SYS_SUPPORTS_APM_EMULATION
52 config HAVE_SCHED_CLOCK
58 config ARCH_USES_GETTIMEOFFSET
62 config GENERIC_CLOCKEVENTS
65 config GENERIC_CLOCKEVENTS_BROADCAST
67 depends on GENERIC_CLOCKEVENTS
76 select GENERIC_ALLOCATOR
87 The Extended Industry Standard Architecture (EISA) bus was
88 developed as an open alternative to the IBM MicroChannel bus.
90 The EISA bus provided some of the features of the IBM MicroChannel
91 bus while maintaining backward compatibility with cards made for
92 the older ISA bus. The EISA bus saw limited use between 1988 and
93 1995 when it was made obsolete by the PCI bus.
95 Say Y here if you are building a kernel for an EISA-based machine.
105 MicroChannel Architecture is found in some IBM PS/2 machines and
106 laptops. It is a bus system similar to PCI or ISA. See
107 <file:Documentation/mca.txt> (and especially the web page given
108 there) before attempting to build an MCA bus kernel.
110 config STACKTRACE_SUPPORT
114 config HAVE_LATENCYTOP_SUPPORT
119 config LOCKDEP_SUPPORT
123 config TRACE_IRQFLAGS_SUPPORT
127 config HARDIRQS_SW_RESEND
131 config GENERIC_IRQ_PROBE
135 config GENERIC_LOCKBREAK
138 depends on SMP && PREEMPT
140 config RWSEM_GENERIC_SPINLOCK
144 config RWSEM_XCHGADD_ALGORITHM
147 config ARCH_HAS_ILOG2_U32
150 config ARCH_HAS_ILOG2_U64
153 config ARCH_HAS_CPUFREQ
156 Internal node to signify that the ARCH has CPUFREQ support
157 and that the relevant menu configurations are displayed for
160 config ARCH_HAS_CPU_IDLE_WAIT
163 config GENERIC_HWEIGHT
167 config GENERIC_CALIBRATE_DELAY
171 config ARCH_MAY_HAVE_PC_FDC
177 config NEED_DMA_MAP_STATE
180 config GENERIC_ISA_DMA
191 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
192 default DRAM_BASE if REMAP_VECTORS_TO_RAM
195 The base address of exception vectors.
197 config ARM_PATCH_PHYS_VIRT
198 bool "Patch physical to virtual translations at runtime" if EMBEDDED
200 depends on !XIP_KERNEL && MMU
201 depends on !ARCH_REALVIEW || !SPARSEMEM
203 Patch phys-to-virt and virt-to-phys translation functions at
204 boot and module load time according to the position of the
205 kernel in system memory.
207 This can only be used with non-XIP MMU kernels where the base
208 of physical memory is at a 16MB boundary.
210 Only disable this option if you know that you do not require
211 this feature (eg, building a kernel for a single machine) and
212 you need to shrink the kernel to the minimal size.
214 config NO_MACH_MEMORY_H
217 Select this when mach/memory.h is removed.
220 hex "Physical address of main memory"
221 depends on !ARM_PATCH_PHYS_VIRT && NO_MACH_MEMORY_H
223 Please provide the physical address corresponding to the
224 location of main memory in your system.
226 source "init/Kconfig"
228 source "kernel/Kconfig.freezer"
233 bool "MMU-based Paged Memory Management Support"
236 Select if you want MMU-based virtualised addressing space
237 support by paged memory management. If unsure, say 'Y'.
240 # The "ARM system type" choice list is ordered alphabetically by option
241 # text. Please add new entries in the option alphabetic order.
244 prompt "ARM system type"
245 default ARCH_VERSATILE
247 config ARCH_INTEGRATOR
248 bool "ARM Ltd. Integrator family"
250 select ARCH_HAS_CPUFREQ
252 select HAVE_MACH_CLKDEV
254 select GENERIC_CLOCKEVENTS
255 select PLAT_VERSATILE
256 select PLAT_VERSATILE_FPGA_IRQ
258 Support for ARM's Integrator platform.
261 bool "ARM Ltd. RealView family"
264 select HAVE_MACH_CLKDEV
266 select GENERIC_CLOCKEVENTS
267 select ARCH_WANT_OPTIONAL_GPIOLIB
268 select PLAT_VERSATILE
269 select PLAT_VERSATILE_CLCD
270 select ARM_TIMER_SP804
271 select GPIO_PL061 if GPIOLIB
273 This enables support for ARM Ltd RealView boards.
275 config ARCH_VERSATILE
276 bool "ARM Ltd. Versatile family"
280 select HAVE_MACH_CLKDEV
282 select GENERIC_CLOCKEVENTS
283 select ARCH_WANT_OPTIONAL_GPIOLIB
284 select PLAT_VERSATILE
285 select PLAT_VERSATILE_CLCD
286 select PLAT_VERSATILE_FPGA_IRQ
287 select ARM_TIMER_SP804
288 select NO_MACH_MEMORY_H
290 This enables support for ARM Ltd Versatile board.
293 bool "ARM Ltd. Versatile Express family"
294 select ARCH_WANT_OPTIONAL_GPIOLIB
296 select ARM_TIMER_SP804
298 select HAVE_MACH_CLKDEV
299 select GENERIC_CLOCKEVENTS
301 select HAVE_PATA_PLATFORM
303 select PLAT_VERSATILE
304 select PLAT_VERSATILE_CLCD
305 select NO_MACH_MEMORY_H
307 This enables support for the ARM Ltd Versatile Express boards.
311 select ARCH_REQUIRE_GPIOLIB
315 This enables support for systems based on the Atmel AT91RM9200,
316 AT91SAM9 and AT91CAP9 processors.
319 bool "Broadcom BCMRING"
323 select ARM_TIMER_SP804
325 select GENERIC_CLOCKEVENTS
326 select ARCH_WANT_OPTIONAL_GPIOLIB
328 Support for Broadcom's BCMRing platform.
331 bool "Cirrus Logic CLPS711x/EP721x-based"
333 select ARCH_USES_GETTIMEOFFSET
335 Support for Cirrus Logic 711x/721x based boards.
338 bool "Cavium Networks CNS3XXX family"
340 select GENERIC_CLOCKEVENTS
342 select MIGHT_HAVE_PCI
343 select PCI_DOMAINS if PCI
344 select NO_MACH_MEMORY_H
346 Support for Cavium Networks CNS3XXX platform.
349 bool "Cortina Systems Gemini"
351 select ARCH_REQUIRE_GPIOLIB
352 select ARCH_USES_GETTIMEOFFSET
353 select NO_MACH_MEMORY_H
355 Support for the Cortina Systems Gemini family SoCs
358 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
362 select GENERIC_CLOCKEVENTS
364 select GENERIC_IRQ_CHIP
368 Support for CSR SiRFSoC ARM Cortex A9 Platform
375 select ARCH_USES_GETTIMEOFFSET
377 This is an evaluation board for the StrongARM processor available
378 from Digital. It has limited hardware on-board, including an
379 Ethernet interface, two PCMCIA sockets, two serial ports and a
388 select ARCH_REQUIRE_GPIOLIB
389 select ARCH_HAS_HOLES_MEMORYMODEL
390 select ARCH_USES_GETTIMEOFFSET
392 This enables support for the Cirrus EP93xx series of CPUs.
394 config ARCH_FOOTBRIDGE
398 select GENERIC_CLOCKEVENTS
400 Support for systems based on the DC21285 companion chip
401 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
404 bool "Freescale MXC/iMX-based"
405 select GENERIC_CLOCKEVENTS
406 select ARCH_REQUIRE_GPIOLIB
409 select GENERIC_IRQ_CHIP
410 select HAVE_SCHED_CLOCK
412 Support for Freescale MXC/iMX-based family of processors
415 bool "Freescale MXS-based"
416 select GENERIC_CLOCKEVENTS
417 select ARCH_REQUIRE_GPIOLIB
420 select NO_MACH_MEMORY_H
422 Support for Freescale MXS-based family of processors
425 bool "Hilscher NetX based"
429 select GENERIC_CLOCKEVENTS
430 select NO_MACH_MEMORY_H
432 This enables support for systems based on the Hilscher NetX Soc
435 bool "Hynix HMS720x-based"
438 select ARCH_USES_GETTIMEOFFSET
440 This enables support for systems based on the Hynix HMS720x
448 select ARCH_SUPPORTS_MSI
451 Support for Intel's IOP13XX (XScale) family of processors.
459 select ARCH_REQUIRE_GPIOLIB
460 select NO_MACH_MEMORY_H
462 Support for Intel's 80219 and IOP32X (XScale) family of
471 select ARCH_REQUIRE_GPIOLIB
472 select NO_MACH_MEMORY_H
474 Support for Intel's IOP33X (XScale) family of processors.
481 select ARCH_USES_GETTIMEOFFSET
483 Support for Intel's IXP23xx (XScale) family of processors.
486 bool "IXP2400/2800-based"
490 select ARCH_USES_GETTIMEOFFSET
492 Support for Intel's IXP2400/2800 (XScale) family of processors.
500 select GENERIC_CLOCKEVENTS
501 select HAVE_SCHED_CLOCK
502 select MIGHT_HAVE_PCI
503 select DMABOUNCE if PCI
505 Support for Intel's IXP4XX (XScale) family of processors.
511 select ARCH_REQUIRE_GPIOLIB
512 select GENERIC_CLOCKEVENTS
514 select NO_MACH_MEMORY_H
516 Support for the Marvell Dove SoC 88AP510
519 bool "Marvell Kirkwood"
522 select ARCH_REQUIRE_GPIOLIB
523 select GENERIC_CLOCKEVENTS
525 select NO_MACH_MEMORY_H
527 Support for the following Marvell Kirkwood series SoCs:
528 88F6180, 88F6192 and 88F6281.
534 select ARCH_REQUIRE_GPIOLIB
537 select USB_ARCH_HAS_OHCI
540 select GENERIC_CLOCKEVENTS
541 select NO_MACH_MEMORY_H
543 Support for the NXP LPC32XX family of processors
546 bool "Marvell MV78xx0"
549 select ARCH_REQUIRE_GPIOLIB
550 select GENERIC_CLOCKEVENTS
552 select NO_MACH_MEMORY_H
554 Support for the following Marvell MV78xx0 series SoCs:
562 select ARCH_REQUIRE_GPIOLIB
563 select GENERIC_CLOCKEVENTS
565 select NO_MACH_MEMORY_H
567 Support for the following Marvell Orion 5x series SoCs:
568 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
569 Orion-2 (5281), Orion-1-90 (6183).
572 bool "Marvell PXA168/910/MMP2"
574 select ARCH_REQUIRE_GPIOLIB
576 select GENERIC_CLOCKEVENTS
577 select HAVE_SCHED_CLOCK
581 select NO_MACH_MEMORY_H
583 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
586 bool "Micrel/Kendin KS8695"
588 select ARCH_REQUIRE_GPIOLIB
589 select ARCH_USES_GETTIMEOFFSET
591 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
592 System-on-Chip devices.
595 bool "Nuvoton W90X900 CPU"
597 select ARCH_REQUIRE_GPIOLIB
600 select GENERIC_CLOCKEVENTS
601 select NO_MACH_MEMORY_H
603 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
604 At present, the w90x900 has been renamed nuc900, regarding
605 the ARM series product line, you can login the following
606 link address to know more.
608 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
609 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
612 bool "Nuvoton NUC93X CPU"
615 select NO_MACH_MEMORY_H
617 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
618 low-power and high performance MPEG-4/JPEG multimedia controller chip.
625 select GENERIC_CLOCKEVENTS
628 select HAVE_SCHED_CLOCK
629 select ARCH_HAS_CPUFREQ
630 select NO_MACH_MEMORY_H
632 This enables support for NVIDIA Tegra based systems (Tegra APX,
633 Tegra 6xx and Tegra 2 series).
636 bool "Philips Nexperia PNX4008 Mobile"
639 select ARCH_USES_GETTIMEOFFSET
640 select NO_MACH_MEMORY_H
642 This enables support for Philips PNX4008 mobile platform.
645 bool "PXA2xx/PXA3xx-based"
648 select ARCH_HAS_CPUFREQ
651 select ARCH_REQUIRE_GPIOLIB
652 select GENERIC_CLOCKEVENTS
653 select HAVE_SCHED_CLOCK
658 select MULTI_IRQ_HANDLER
660 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
665 select GENERIC_CLOCKEVENTS
666 select ARCH_REQUIRE_GPIOLIB
668 select NO_MACH_MEMORY_H
670 Support for Qualcomm MSM/QSD based systems. This runs on the
671 apps processor of the MSM/QSD and depends on a shared memory
672 interface to the modem processor which runs the baseband
673 stack and controls some vital subsystems
674 (clock and power control, etc).
677 bool "Renesas SH-Mobile / R-Mobile"
680 select HAVE_MACH_CLKDEV
681 select GENERIC_CLOCKEVENTS
684 select MULTI_IRQ_HANDLER
685 select PM_GENERIC_DOMAINS if PM
687 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
694 select ARCH_MAY_HAVE_PC_FDC
695 select HAVE_PATA_PLATFORM
698 select ARCH_SPARSEMEM_ENABLE
699 select ARCH_USES_GETTIMEOFFSET
701 On the Acorn Risc-PC, Linux can support the internal IDE disk and
702 CD-ROM interface, serial and parallel port, and the floppy drive.
709 select ARCH_SPARSEMEM_ENABLE
711 select ARCH_HAS_CPUFREQ
713 select GENERIC_CLOCKEVENTS
715 select HAVE_SCHED_CLOCK
717 select ARCH_REQUIRE_GPIOLIB
719 Support for StrongARM 11x0 based boards.
722 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
724 select ARCH_HAS_CPUFREQ
727 select ARCH_USES_GETTIMEOFFSET
728 select HAVE_S3C2410_I2C if I2C
729 select NO_MACH_MEMORY_H
731 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
732 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
733 the Samsung SMDK2410 development board (and derivatives).
735 Note, the S3C2416 and the S3C2450 are so close that they even share
736 the same SoC ID code. This means that there is no separate machine
737 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
740 bool "Samsung S3C64XX"
747 select ARCH_USES_GETTIMEOFFSET
748 select ARCH_HAS_CPUFREQ
749 select ARCH_REQUIRE_GPIOLIB
750 select SAMSUNG_CLKSRC
751 select SAMSUNG_IRQ_VIC_TIMER
752 select SAMSUNG_IRQ_UART
753 select S3C_GPIO_TRACK
754 select S3C_GPIO_PULL_UPDOWN
755 select S3C_GPIO_CFG_S3C24XX
756 select S3C_GPIO_CFG_S3C64XX
758 select USB_ARCH_HAS_OHCI
759 select SAMSUNG_GPIOLIB_4BIT
760 select HAVE_S3C2410_I2C if I2C
761 select HAVE_S3C2410_WATCHDOG if WATCHDOG
763 Samsung S3C64XX series based systems
766 bool "Samsung S5P6440 S5P6450"
772 select HAVE_S3C2410_WATCHDOG if WATCHDOG
773 select GENERIC_CLOCKEVENTS
774 select HAVE_SCHED_CLOCK
775 select HAVE_S3C2410_I2C if I2C
776 select HAVE_S3C_RTC if RTC_CLASS
778 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
782 bool "Samsung S5PC100"
787 select ARM_L1_CACHE_SHIFT_6
788 select ARCH_USES_GETTIMEOFFSET
789 select HAVE_S3C2410_I2C if I2C
790 select HAVE_S3C_RTC if RTC_CLASS
791 select HAVE_S3C2410_WATCHDOG if WATCHDOG
792 select NO_MACH_MEMORY_H
794 Samsung S5PC100 series based systems
797 bool "Samsung S5PV210/S5PC110"
799 select ARCH_SPARSEMEM_ENABLE
800 select ARCH_HAS_HOLES_MEMORYMODEL
805 select ARM_L1_CACHE_SHIFT_6
806 select ARCH_HAS_CPUFREQ
807 select GENERIC_CLOCKEVENTS
808 select HAVE_SCHED_CLOCK
809 select HAVE_S3C2410_I2C if I2C
810 select HAVE_S3C_RTC if RTC_CLASS
811 select HAVE_S3C2410_WATCHDOG if WATCHDOG
813 Samsung S5PV210/S5PC110 series based systems
816 bool "Samsung EXYNOS4"
818 select ARCH_SPARSEMEM_ENABLE
819 select ARCH_HAS_HOLES_MEMORYMODEL
823 select ARCH_HAS_CPUFREQ
824 select GENERIC_CLOCKEVENTS
825 select HAVE_S3C_RTC if RTC_CLASS
826 select HAVE_S3C2410_I2C if I2C
827 select HAVE_S3C2410_WATCHDOG if WATCHDOG
829 Samsung EXYNOS4 series based systems
838 select ARCH_USES_GETTIMEOFFSET
840 Support for the StrongARM based Digital DNARD machine, also known
841 as "Shark" (<http://www.shark-linux.de/shark.html>).
844 bool "Telechips TCC ARM926-based systems"
849 select GENERIC_CLOCKEVENTS
850 select NO_MACH_MEMORY_H
852 Support for Telechips TCC ARM926-based systems.
855 bool "ST-Ericsson U300 Series"
859 select HAVE_SCHED_CLOCK
863 select GENERIC_CLOCKEVENTS
865 select HAVE_MACH_CLKDEV
868 Support for ST-Ericsson U300 series mobile platforms.
871 bool "ST-Ericsson U8500 Series"
874 select GENERIC_CLOCKEVENTS
876 select ARCH_REQUIRE_GPIOLIB
877 select ARCH_HAS_CPUFREQ
878 select NO_MACH_MEMORY_H
880 Support for ST-Ericsson's Ux500 architecture
883 bool "STMicroelectronics Nomadik"
888 select GENERIC_CLOCKEVENTS
889 select ARCH_REQUIRE_GPIOLIB
890 select NO_MACH_MEMORY_H
892 Support for the Nomadik platform by ST-Ericsson
896 select GENERIC_CLOCKEVENTS
897 select ARCH_REQUIRE_GPIOLIB
901 select GENERIC_ALLOCATOR
902 select GENERIC_IRQ_CHIP
903 select ARCH_HAS_HOLES_MEMORYMODEL
905 Support for TI's DaVinci platform.
910 select ARCH_REQUIRE_GPIOLIB
911 select ARCH_HAS_CPUFREQ
913 select GENERIC_CLOCKEVENTS
914 select HAVE_SCHED_CLOCK
915 select ARCH_HAS_HOLES_MEMORYMODEL
917 Support for TI's OMAP platform (OMAP1/2/3/4).
922 select ARCH_REQUIRE_GPIOLIB
925 select GENERIC_CLOCKEVENTS
927 select NO_MACH_MEMORY_H
929 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
932 bool "VIA/WonderMedia 85xx"
935 select ARCH_HAS_CPUFREQ
936 select GENERIC_CLOCKEVENTS
937 select ARCH_REQUIRE_GPIOLIB
940 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
943 bool "Xilinx Zynq ARM Cortex A9 Platform"
946 select GENERIC_CLOCKEVENTS
953 Support for Xilinx Zynq ARM Cortex A9 Platform
957 # This is sorted alphabetically by mach-* pathname. However, plat-*
958 # Kconfigs may be included either alphabetically (according to the
959 # plat- suffix) or along side the corresponding mach-* source.
961 source "arch/arm/mach-at91/Kconfig"
963 source "arch/arm/mach-bcmring/Kconfig"
965 source "arch/arm/mach-clps711x/Kconfig"
967 source "arch/arm/mach-cns3xxx/Kconfig"
969 source "arch/arm/mach-davinci/Kconfig"
971 source "arch/arm/mach-dove/Kconfig"
973 source "arch/arm/mach-ep93xx/Kconfig"
975 source "arch/arm/mach-footbridge/Kconfig"
977 source "arch/arm/mach-gemini/Kconfig"
979 source "arch/arm/mach-h720x/Kconfig"
981 source "arch/arm/mach-integrator/Kconfig"
983 source "arch/arm/mach-iop32x/Kconfig"
985 source "arch/arm/mach-iop33x/Kconfig"
987 source "arch/arm/mach-iop13xx/Kconfig"
989 source "arch/arm/mach-ixp4xx/Kconfig"
991 source "arch/arm/mach-ixp2000/Kconfig"
993 source "arch/arm/mach-ixp23xx/Kconfig"
995 source "arch/arm/mach-kirkwood/Kconfig"
997 source "arch/arm/mach-ks8695/Kconfig"
999 source "arch/arm/mach-lpc32xx/Kconfig"
1001 source "arch/arm/mach-msm/Kconfig"
1003 source "arch/arm/mach-mv78xx0/Kconfig"
1005 source "arch/arm/plat-mxc/Kconfig"
1007 source "arch/arm/mach-mxs/Kconfig"
1009 source "arch/arm/mach-netx/Kconfig"
1011 source "arch/arm/mach-nomadik/Kconfig"
1012 source "arch/arm/plat-nomadik/Kconfig"
1014 source "arch/arm/mach-nuc93x/Kconfig"
1016 source "arch/arm/plat-omap/Kconfig"
1018 source "arch/arm/mach-omap1/Kconfig"
1020 source "arch/arm/mach-omap2/Kconfig"
1022 source "arch/arm/mach-orion5x/Kconfig"
1024 source "arch/arm/mach-pxa/Kconfig"
1025 source "arch/arm/plat-pxa/Kconfig"
1027 source "arch/arm/mach-mmp/Kconfig"
1029 source "arch/arm/mach-realview/Kconfig"
1031 source "arch/arm/mach-sa1100/Kconfig"
1033 source "arch/arm/plat-samsung/Kconfig"
1034 source "arch/arm/plat-s3c24xx/Kconfig"
1035 source "arch/arm/plat-s5p/Kconfig"
1037 source "arch/arm/plat-spear/Kconfig"
1039 source "arch/arm/plat-tcc/Kconfig"
1042 source "arch/arm/mach-s3c2410/Kconfig"
1043 source "arch/arm/mach-s3c2412/Kconfig"
1044 source "arch/arm/mach-s3c2416/Kconfig"
1045 source "arch/arm/mach-s3c2440/Kconfig"
1046 source "arch/arm/mach-s3c2443/Kconfig"
1050 source "arch/arm/mach-s3c64xx/Kconfig"
1053 source "arch/arm/mach-s5p64x0/Kconfig"
1055 source "arch/arm/mach-s5pc100/Kconfig"
1057 source "arch/arm/mach-s5pv210/Kconfig"
1059 source "arch/arm/mach-exynos4/Kconfig"
1061 source "arch/arm/mach-shmobile/Kconfig"
1063 source "arch/arm/mach-tegra/Kconfig"
1065 source "arch/arm/mach-u300/Kconfig"
1067 source "arch/arm/mach-ux500/Kconfig"
1069 source "arch/arm/mach-versatile/Kconfig"
1071 source "arch/arm/mach-vexpress/Kconfig"
1072 source "arch/arm/plat-versatile/Kconfig"
1074 source "arch/arm/mach-vt8500/Kconfig"
1076 source "arch/arm/mach-w90x900/Kconfig"
1078 # Definitions to make life easier
1084 select GENERIC_CLOCKEVENTS
1085 select HAVE_SCHED_CLOCK
1090 select GENERIC_IRQ_CHIP
1091 select HAVE_SCHED_CLOCK
1096 config PLAT_VERSATILE
1099 config ARM_TIMER_SP804
1103 source arch/arm/mm/Kconfig
1106 bool "Enable iWMMXt support"
1107 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1108 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1110 Enable support for iWMMXt context switching at run time if
1111 running on a CPU that supports it.
1113 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1116 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1120 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1121 (!ARCH_OMAP3 || OMAP3_EMU)
1125 config MULTI_IRQ_HANDLER
1128 Allow each machine to specify it's own IRQ handler at run time.
1131 source "arch/arm/Kconfig-nommu"
1134 config ARM_ERRATA_411920
1135 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1136 depends on CPU_V6 || CPU_V6K
1138 Invalidation of the Instruction Cache operation can
1139 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1140 It does not affect the MPCore. This option enables the ARM Ltd.
1141 recommended workaround.
1143 config ARM_ERRATA_430973
1144 bool "ARM errata: Stale prediction on replaced interworking branch"
1147 This option enables the workaround for the 430973 Cortex-A8
1148 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1149 interworking branch is replaced with another code sequence at the
1150 same virtual address, whether due to self-modifying code or virtual
1151 to physical address re-mapping, Cortex-A8 does not recover from the
1152 stale interworking branch prediction. This results in Cortex-A8
1153 executing the new code sequence in the incorrect ARM or Thumb state.
1154 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1155 and also flushes the branch target cache at every context switch.
1156 Note that setting specific bits in the ACTLR register may not be
1157 available in non-secure mode.
1159 config ARM_ERRATA_458693
1160 bool "ARM errata: Processor deadlock when a false hazard is created"
1163 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1164 erratum. For very specific sequences of memory operations, it is
1165 possible for a hazard condition intended for a cache line to instead
1166 be incorrectly associated with a different cache line. This false
1167 hazard might then cause a processor deadlock. The workaround enables
1168 the L1 caching of the NEON accesses and disables the PLD instruction
1169 in the ACTLR register. Note that setting specific bits in the ACTLR
1170 register may not be available in non-secure mode.
1172 config ARM_ERRATA_460075
1173 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1176 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1177 erratum. Any asynchronous access to the L2 cache may encounter a
1178 situation in which recent store transactions to the L2 cache are lost
1179 and overwritten with stale memory contents from external memory. The
1180 workaround disables the write-allocate mode for the L2 cache via the
1181 ACTLR register. Note that setting specific bits in the ACTLR register
1182 may not be available in non-secure mode.
1184 config ARM_ERRATA_742230
1185 bool "ARM errata: DMB operation may be faulty"
1186 depends on CPU_V7 && SMP
1188 This option enables the workaround for the 742230 Cortex-A9
1189 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1190 between two write operations may not ensure the correct visibility
1191 ordering of the two writes. This workaround sets a specific bit in
1192 the diagnostic register of the Cortex-A9 which causes the DMB
1193 instruction to behave as a DSB, ensuring the correct behaviour of
1196 config ARM_ERRATA_742231
1197 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1198 depends on CPU_V7 && SMP
1200 This option enables the workaround for the 742231 Cortex-A9
1201 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1202 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1203 accessing some data located in the same cache line, may get corrupted
1204 data due to bad handling of the address hazard when the line gets
1205 replaced from one of the CPUs at the same time as another CPU is
1206 accessing it. This workaround sets specific bits in the diagnostic
1207 register of the Cortex-A9 which reduces the linefill issuing
1208 capabilities of the processor.
1210 config PL310_ERRATA_588369
1211 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1212 depends on CACHE_L2X0
1214 The PL310 L2 cache controller implements three types of Clean &
1215 Invalidate maintenance operations: by Physical Address
1216 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1217 They are architecturally defined to behave as the execution of a
1218 clean operation followed immediately by an invalidate operation,
1219 both performing to the same memory location. This functionality
1220 is not correctly implemented in PL310 as clean lines are not
1221 invalidated as a result of these operations.
1223 config ARM_ERRATA_720789
1224 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1225 depends on CPU_V7 && SMP
1227 This option enables the workaround for the 720789 Cortex-A9 (prior to
1228 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1229 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1230 As a consequence of this erratum, some TLB entries which should be
1231 invalidated are not, resulting in an incoherency in the system page
1232 tables. The workaround changes the TLB flushing routines to invalidate
1233 entries regardless of the ASID.
1235 config PL310_ERRATA_727915
1236 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1237 depends on CACHE_L2X0
1239 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1240 operation (offset 0x7FC). This operation runs in background so that
1241 PL310 can handle normal accesses while it is in progress. Under very
1242 rare circumstances, due to this erratum, write data can be lost when
1243 PL310 treats a cacheable write transaction during a Clean &
1244 Invalidate by Way operation.
1246 config ARM_ERRATA_743622
1247 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1250 This option enables the workaround for the 743622 Cortex-A9
1251 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1252 optimisation in the Cortex-A9 Store Buffer may lead to data
1253 corruption. This workaround sets a specific bit in the diagnostic
1254 register of the Cortex-A9 which disables the Store Buffer
1255 optimisation, preventing the defect from occurring. This has no
1256 visible impact on the overall performance or power consumption of the
1259 config ARM_ERRATA_751472
1260 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1261 depends on CPU_V7 && SMP
1263 This option enables the workaround for the 751472 Cortex-A9 (prior
1264 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1265 completion of a following broadcasted operation if the second
1266 operation is received by a CPU before the ICIALLUIS has completed,
1267 potentially leading to corrupted entries in the cache or TLB.
1269 config ARM_ERRATA_753970
1270 bool "ARM errata: cache sync operation may be faulty"
1271 depends on CACHE_PL310
1273 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1275 Under some condition the effect of cache sync operation on
1276 the store buffer still remains when the operation completes.
1277 This means that the store buffer is always asked to drain and
1278 this prevents it from merging any further writes. The workaround
1279 is to replace the normal offset of cache sync operation (0x730)
1280 by another offset targeting an unmapped PL310 register 0x740.
1281 This has the same effect as the cache sync operation: store buffer
1282 drain and waiting for all buffers empty.
1284 config ARM_ERRATA_754322
1285 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1288 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1289 r3p*) erratum. A speculative memory access may cause a page table walk
1290 which starts prior to an ASID switch but completes afterwards. This
1291 can populate the micro-TLB with a stale entry which may be hit with
1292 the new ASID. This workaround places two dsb instructions in the mm
1293 switching code so that no page table walks can cross the ASID switch.
1295 config ARM_ERRATA_754327
1296 bool "ARM errata: no automatic Store Buffer drain"
1297 depends on CPU_V7 && SMP
1299 This option enables the workaround for the 754327 Cortex-A9 (prior to
1300 r2p0) erratum. The Store Buffer does not have any automatic draining
1301 mechanism and therefore a livelock may occur if an external agent
1302 continuously polls a memory location waiting to observe an update.
1303 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1304 written polling loops from denying visibility of updates to memory.
1308 source "arch/arm/common/Kconfig"
1318 Find out whether you have ISA slots on your motherboard. ISA is the
1319 name of a bus system, i.e. the way the CPU talks to the other stuff
1320 inside your box. Other bus systems are PCI, EISA, MicroChannel
1321 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1322 newer boards don't support it. If you have ISA, say Y, otherwise N.
1324 # Select ISA DMA controller support
1329 # Select ISA DMA interface
1334 bool "PCI support" if MIGHT_HAVE_PCI
1336 Find out whether you have a PCI motherboard. PCI is the name of a
1337 bus system, i.e. the way the CPU talks to the other stuff inside
1338 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1339 VESA. If you have PCI, say Y, otherwise N.
1345 config PCI_NANOENGINE
1346 bool "BSE nanoEngine PCI support"
1347 depends on SA1100_NANOENGINE
1349 Enable PCI on the BSE nanoEngine board.
1354 # Select the host bridge type
1355 config PCI_HOST_VIA82C505
1357 depends on PCI && ARCH_SHARK
1360 config PCI_HOST_ITE8152
1362 depends on PCI && MACH_ARMCORE
1366 source "drivers/pci/Kconfig"
1368 source "drivers/pcmcia/Kconfig"
1372 menu "Kernel Features"
1374 source "kernel/time/Kconfig"
1377 bool "Symmetric Multi-Processing"
1378 depends on CPU_V6K || CPU_V7
1379 depends on GENERIC_CLOCKEVENTS
1380 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1381 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1382 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1383 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1384 select USE_GENERIC_SMP_HELPERS
1385 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1387 This enables support for systems with more than one CPU. If you have
1388 a system with only one CPU, like most personal computers, say N. If
1389 you have a system with more than one CPU, say Y.
1391 If you say N here, the kernel will run on single and multiprocessor
1392 machines, but will use only one CPU of a multiprocessor machine. If
1393 you say Y here, the kernel will run on many, but not all, single
1394 processor machines. On a single processor machine, the kernel will
1395 run faster if you say N here.
1397 See also <file:Documentation/i386/IO-APIC.txt>,
1398 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1399 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1401 If you don't know what to do here, say N.
1404 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1405 depends on EXPERIMENTAL
1406 depends on SMP && !XIP_KERNEL
1409 SMP kernels contain instructions which fail on non-SMP processors.
1410 Enabling this option allows the kernel to modify itself to make
1411 these instructions safe. Disabling it allows about 1K of space
1414 If you don't know what to do here, say Y.
1419 This option enables support for the ARM system coherency unit
1426 This options enables support for the ARM timer and watchdog unit
1429 prompt "Memory split"
1432 Select the desired split between kernel and user memory.
1434 If you are not absolutely sure what you are doing, leave this
1438 bool "3G/1G user/kernel split"
1440 bool "2G/2G user/kernel split"
1442 bool "1G/3G user/kernel split"
1447 default 0x40000000 if VMSPLIT_1G
1448 default 0x80000000 if VMSPLIT_2G
1452 int "Maximum number of CPUs (2-32)"
1458 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1459 depends on SMP && HOTPLUG && EXPERIMENTAL
1461 Say Y here to experiment with turning CPUs off and on. CPUs
1462 can be controlled through /sys/devices/system/cpu.
1465 bool "Use local timer interrupts"
1468 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1470 Enable support for local timers on SMP platforms, rather then the
1471 legacy IPI broadcast method. Local timers allows the system
1472 accounting to be spread across the timer interval, preventing a
1473 "thundering herd" at every timer tick.
1475 source kernel/Kconfig.preempt
1479 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1480 ARCH_S5PV210 || ARCH_EXYNOS4
1481 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1482 default AT91_TIMER_HZ if ARCH_AT91
1483 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1486 config THUMB2_KERNEL
1487 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1488 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1490 select ARM_ASM_UNIFIED
1492 By enabling this option, the kernel will be compiled in
1493 Thumb-2 mode. A compiler/assembler that understand the unified
1494 ARM-Thumb syntax is needed.
1498 config THUMB2_AVOID_R_ARM_THM_JUMP11
1499 bool "Work around buggy Thumb-2 short branch relocations in gas"
1500 depends on THUMB2_KERNEL && MODULES
1503 Various binutils versions can resolve Thumb-2 branches to
1504 locally-defined, preemptible global symbols as short-range "b.n"
1505 branch instructions.
1507 This is a problem, because there's no guarantee the final
1508 destination of the symbol, or any candidate locations for a
1509 trampoline, are within range of the branch. For this reason, the
1510 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1511 relocation in modules at all, and it makes little sense to add
1514 The symptom is that the kernel fails with an "unsupported
1515 relocation" error when loading some modules.
1517 Until fixed tools are available, passing
1518 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1519 code which hits this problem, at the cost of a bit of extra runtime
1520 stack usage in some cases.
1522 The problem is described in more detail at:
1523 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1525 Only Thumb-2 kernels are affected.
1527 Unless you are sure your tools don't have this problem, say Y.
1529 config ARM_ASM_UNIFIED
1533 bool "Use the ARM EABI to compile the kernel"
1535 This option allows for the kernel to be compiled using the latest
1536 ARM ABI (aka EABI). This is only useful if you are using a user
1537 space environment that is also compiled with EABI.
1539 Since there are major incompatibilities between the legacy ABI and
1540 EABI, especially with regard to structure member alignment, this
1541 option also changes the kernel syscall calling convention to
1542 disambiguate both ABIs and allow for backward compatibility support
1543 (selected with CONFIG_OABI_COMPAT).
1545 To use this you need GCC version 4.0.0 or later.
1548 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1549 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1552 This option preserves the old syscall interface along with the
1553 new (ARM EABI) one. It also provides a compatibility layer to
1554 intercept syscalls that have structure arguments which layout
1555 in memory differs between the legacy ABI and the new ARM EABI
1556 (only for non "thumb" binaries). This option adds a tiny
1557 overhead to all syscalls and produces a slightly larger kernel.
1558 If you know you'll be using only pure EABI user space then you
1559 can say N here. If this option is not selected and you attempt
1560 to execute a legacy ABI binary then the result will be
1561 UNPREDICTABLE (in fact it can be predicted that it won't work
1562 at all). If in doubt say Y.
1564 config ARCH_HAS_HOLES_MEMORYMODEL
1567 config ARCH_SPARSEMEM_ENABLE
1570 config ARCH_SPARSEMEM_DEFAULT
1571 def_bool ARCH_SPARSEMEM_ENABLE
1573 config ARCH_SELECT_MEMORY_MODEL
1574 def_bool ARCH_SPARSEMEM_ENABLE
1576 config HAVE_ARCH_PFN_VALID
1577 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1580 bool "High Memory Support"
1583 The address space of ARM processors is only 4 Gigabytes large
1584 and it has to accommodate user address space, kernel address
1585 space as well as some memory mapped IO. That means that, if you
1586 have a large amount of physical memory and/or IO, not all of the
1587 memory can be "permanently mapped" by the kernel. The physical
1588 memory that is not permanently mapped is called "high memory".
1590 Depending on the selected kernel/user memory split, minimum
1591 vmalloc space and actual amount of RAM, you may not need this
1592 option which should result in a slightly faster kernel.
1597 bool "Allocate 2nd-level pagetables from highmem"
1600 config HW_PERF_EVENTS
1601 bool "Enable hardware performance counter support for perf events"
1602 depends on PERF_EVENTS && CPU_HAS_PMU
1605 Enable hardware performance counter support for perf events. If
1606 disabled, perf events will use software events only.
1610 config FORCE_MAX_ZONEORDER
1611 int "Maximum zone order" if ARCH_SHMOBILE
1612 range 11 64 if ARCH_SHMOBILE
1613 default "9" if SA1111
1616 The kernel memory allocator divides physically contiguous memory
1617 blocks into "zones", where each zone is a power of two number of
1618 pages. This option selects the largest power of two that the kernel
1619 keeps in the memory allocator. If you need to allocate very large
1620 blocks of physically contiguous memory, then you may need to
1621 increase this value.
1623 This config option is actually maximum order plus one. For example,
1624 a value of 11 means that the largest free memory block is 2^10 pages.
1627 bool "Timer and CPU usage LEDs"
1628 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1629 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1630 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1631 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1632 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1633 ARCH_AT91 || ARCH_DAVINCI || \
1634 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1636 If you say Y here, the LEDs on your machine will be used
1637 to provide useful information about your current system status.
1639 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1640 be able to select which LEDs are active using the options below. If
1641 you are compiling a kernel for the EBSA-110 or the LART however, the
1642 red LED will simply flash regularly to indicate that the system is
1643 still functional. It is safe to say Y here if you have a CATS
1644 system, but the driver will do nothing.
1647 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1648 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1649 || MACH_OMAP_PERSEUS2
1651 depends on !GENERIC_CLOCKEVENTS
1652 default y if ARCH_EBSA110
1654 If you say Y here, one of the system LEDs (the green one on the
1655 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1656 will flash regularly to indicate that the system is still
1657 operational. This is mainly useful to kernel hackers who are
1658 debugging unstable kernels.
1660 The LART uses the same LED for both Timer LED and CPU usage LED
1661 functions. You may choose to use both, but the Timer LED function
1662 will overrule the CPU usage LED.
1665 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1667 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1668 || MACH_OMAP_PERSEUS2
1671 If you say Y here, the red LED will be used to give a good real
1672 time indication of CPU usage, by lighting whenever the idle task
1673 is not currently executing.
1675 The LART uses the same LED for both Timer LED and CPU usage LED
1676 functions. You may choose to use both, but the Timer LED function
1677 will overrule the CPU usage LED.
1679 config ALIGNMENT_TRAP
1681 depends on CPU_CP15_MMU
1682 default y if !ARCH_EBSA110
1683 select HAVE_PROC_CPU if PROC_FS
1685 ARM processors cannot fetch/store information which is not
1686 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1687 address divisible by 4. On 32-bit ARM processors, these non-aligned
1688 fetch/store instructions will be emulated in software if you say
1689 here, which has a severe performance impact. This is necessary for
1690 correct operation of some network protocols. With an IP-only
1691 configuration it is safe to say N, otherwise say Y.
1693 config UACCESS_WITH_MEMCPY
1694 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1695 depends on MMU && EXPERIMENTAL
1696 default y if CPU_FEROCEON
1698 Implement faster copy_to_user and clear_user methods for CPU
1699 cores where a 8-word STM instruction give significantly higher
1700 memory write throughput than a sequence of individual 32bit stores.
1702 A possible side effect is a slight increase in scheduling latency
1703 between threads sharing the same address space if they invoke
1704 such copy operations with large buffers.
1706 However, if the CPU data cache is using a write-allocate mode,
1707 this option is unlikely to provide any performance gain.
1711 prompt "Enable seccomp to safely compute untrusted bytecode"
1713 This kernel feature is useful for number crunching applications
1714 that may need to compute untrusted bytecode during their
1715 execution. By using pipes or other transports made available to
1716 the process as file descriptors supporting the read/write
1717 syscalls, it's possible to isolate those applications in
1718 their own address space using seccomp. Once seccomp is
1719 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1720 and the task is only allowed to execute a few safe syscalls
1721 defined by each seccomp mode.
1723 config CC_STACKPROTECTOR
1724 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1725 depends on EXPERIMENTAL
1727 This option turns on the -fstack-protector GCC feature. This
1728 feature puts, at the beginning of functions, a canary value on
1729 the stack just before the return address, and validates
1730 the value just before actually returning. Stack based buffer
1731 overflows (that need to overwrite this return address) now also
1732 overwrite the canary, which gets detected and the attack is then
1733 neutralized via a kernel panic.
1734 This feature requires gcc version 4.2 or above.
1736 config DEPRECATED_PARAM_STRUCT
1737 bool "Provide old way to pass kernel parameters"
1739 This was deprecated in 2001 and announced to live on for 5 years.
1740 Some old boot loaders still use this way.
1747 bool "Flattened Device Tree support"
1749 select OF_EARLY_FLATTREE
1752 Include support for flattened device tree machine descriptions.
1754 # Compressed boot loader in ROM. Yes, we really want to ask about
1755 # TEXT and BSS so we preserve their values in the config files.
1756 config ZBOOT_ROM_TEXT
1757 hex "Compressed ROM boot loader base address"
1760 The physical address at which the ROM-able zImage is to be
1761 placed in the target. Platforms which normally make use of
1762 ROM-able zImage formats normally set this to a suitable
1763 value in their defconfig file.
1765 If ZBOOT_ROM is not enabled, this has no effect.
1767 config ZBOOT_ROM_BSS
1768 hex "Compressed ROM boot loader BSS address"
1771 The base address of an area of read/write memory in the target
1772 for the ROM-able zImage which must be available while the
1773 decompressor is running. It must be large enough to hold the
1774 entire decompressed kernel plus an additional 128 KiB.
1775 Platforms which normally make use of ROM-able zImage formats
1776 normally set this to a suitable value in their defconfig file.
1778 If ZBOOT_ROM is not enabled, this has no effect.
1781 bool "Compressed boot loader in ROM/flash"
1782 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1784 Say Y here if you intend to execute your compressed kernel image
1785 (zImage) directly from ROM or flash. If unsure, say N.
1788 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1789 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1790 default ZBOOT_ROM_NONE
1792 Include experimental SD/MMC loading code in the ROM-able zImage.
1793 With this enabled it is possible to write the the ROM-able zImage
1794 kernel image to an MMC or SD card and boot the kernel straight
1795 from the reset vector. At reset the processor Mask ROM will load
1796 the first part of the the ROM-able zImage which in turn loads the
1797 rest the kernel image to RAM.
1799 config ZBOOT_ROM_NONE
1800 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1802 Do not load image from SD or MMC
1804 config ZBOOT_ROM_MMCIF
1805 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1807 Load image from MMCIF hardware block.
1809 config ZBOOT_ROM_SH_MOBILE_SDHI
1810 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1812 Load image from SDHI hardware block
1817 string "Default kernel command string"
1820 On some architectures (EBSA110 and CATS), there is currently no way
1821 for the boot loader to pass arguments to the kernel. For these
1822 architectures, you should supply some command-line options at build
1823 time by entering them here. As a minimum, you should specify the
1824 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1827 prompt "Kernel command line type" if CMDLINE != ""
1828 default CMDLINE_FROM_BOOTLOADER
1830 config CMDLINE_FROM_BOOTLOADER
1831 bool "Use bootloader kernel arguments if available"
1833 Uses the command-line options passed by the boot loader. If
1834 the boot loader doesn't provide any, the default kernel command
1835 string provided in CMDLINE will be used.
1837 config CMDLINE_EXTEND
1838 bool "Extend bootloader kernel arguments"
1840 The command-line arguments provided by the boot loader will be
1841 appended to the default kernel command string.
1843 config CMDLINE_FORCE
1844 bool "Always use the default kernel command string"
1846 Always use the default kernel command string, even if the boot
1847 loader passes other arguments to the kernel.
1848 This is useful if you cannot or don't want to change the
1849 command-line options your boot loader passes to the kernel.
1853 bool "Kernel Execute-In-Place from ROM"
1854 depends on !ZBOOT_ROM
1856 Execute-In-Place allows the kernel to run from non-volatile storage
1857 directly addressable by the CPU, such as NOR flash. This saves RAM
1858 space since the text section of the kernel is not loaded from flash
1859 to RAM. Read-write sections, such as the data section and stack,
1860 are still copied to RAM. The XIP kernel is not compressed since
1861 it has to run directly from flash, so it will take more space to
1862 store it. The flash address used to link the kernel object files,
1863 and for storing it, is configuration dependent. Therefore, if you
1864 say Y here, you must know the proper physical address where to
1865 store the kernel image depending on your own flash memory usage.
1867 Also note that the make target becomes "make xipImage" rather than
1868 "make zImage" or "make Image". The final kernel binary to put in
1869 ROM memory will be arch/arm/boot/xipImage.
1873 config XIP_PHYS_ADDR
1874 hex "XIP Kernel Physical Location"
1875 depends on XIP_KERNEL
1876 default "0x00080000"
1878 This is the physical address in your flash memory the kernel will
1879 be linked for and stored to. This address is dependent on your
1883 bool "Kexec system call (EXPERIMENTAL)"
1884 depends on EXPERIMENTAL
1886 kexec is a system call that implements the ability to shutdown your
1887 current kernel, and to start another kernel. It is like a reboot
1888 but it is independent of the system firmware. And like a reboot
1889 you can start any kernel with it, not just Linux.
1891 It is an ongoing process to be certain the hardware in a machine
1892 is properly shutdown, so do not be surprised if this code does not
1893 initially work for you. It may help to enable device hotplugging
1897 bool "Export atags in procfs"
1901 Should the atags used to boot the kernel be exported in an "atags"
1902 file in procfs. Useful with kexec.
1905 bool "Build kdump crash kernel (EXPERIMENTAL)"
1906 depends on EXPERIMENTAL
1908 Generate crash dump after being started by kexec. This should
1909 be normally only set in special crash dump kernels which are
1910 loaded in the main kernel with kexec-tools into a specially
1911 reserved region and then later executed after a crash by
1912 kdump/kexec. The crash dump kernel must be compiled to a
1913 memory address not used by the main kernel
1915 For more details see Documentation/kdump/kdump.txt
1917 config AUTO_ZRELADDR
1918 bool "Auto calculation of the decompressed kernel image address"
1919 depends on !ZBOOT_ROM && !ARCH_U300
1921 ZRELADDR is the physical address where the decompressed kernel
1922 image will be placed. If AUTO_ZRELADDR is selected, the address
1923 will be determined at run-time by masking the current IP with
1924 0xf8000000. This assumes the zImage being placed in the first 128MB
1925 from start of memory.
1929 menu "CPU Power Management"
1933 source "drivers/cpufreq/Kconfig"
1936 tristate "CPUfreq driver for i.MX CPUs"
1937 depends on ARCH_MXC && CPU_FREQ
1939 This enables the CPUfreq driver for i.MX CPUs.
1941 config CPU_FREQ_SA1100
1944 config CPU_FREQ_SA1110
1947 config CPU_FREQ_INTEGRATOR
1948 tristate "CPUfreq driver for ARM Integrator CPUs"
1949 depends on ARCH_INTEGRATOR && CPU_FREQ
1952 This enables the CPUfreq driver for ARM Integrator CPUs.
1954 For details, take a look at <file:Documentation/cpu-freq>.
1960 depends on CPU_FREQ && ARCH_PXA && PXA25x
1962 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1967 Internal configuration node for common cpufreq on Samsung SoC
1969 config CPU_FREQ_S3C24XX
1970 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
1971 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1974 This enables the CPUfreq driver for the Samsung S3C24XX family
1977 For details, take a look at <file:Documentation/cpu-freq>.
1981 config CPU_FREQ_S3C24XX_PLL
1982 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
1983 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
1985 Compile in support for changing the PLL frequency from the
1986 S3C24XX series CPUfreq driver. The PLL takes time to settle
1987 after a frequency change, so by default it is not enabled.
1989 This also means that the PLL tables for the selected CPU(s) will
1990 be built which may increase the size of the kernel image.
1992 config CPU_FREQ_S3C24XX_DEBUG
1993 bool "Debug CPUfreq Samsung driver core"
1994 depends on CPU_FREQ_S3C24XX
1996 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
1998 config CPU_FREQ_S3C24XX_IODEBUG
1999 bool "Debug CPUfreq Samsung driver IO timing"
2000 depends on CPU_FREQ_S3C24XX
2002 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2004 config CPU_FREQ_S3C24XX_DEBUGFS
2005 bool "Export debugfs for CPUFreq"
2006 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2008 Export status information via debugfs.
2012 source "drivers/cpuidle/Kconfig"
2016 menu "Floating point emulation"
2018 comment "At least one emulation must be selected"
2021 bool "NWFPE math emulation"
2022 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2024 Say Y to include the NWFPE floating point emulator in the kernel.
2025 This is necessary to run most binaries. Linux does not currently
2026 support floating point hardware so you need to say Y here even if
2027 your machine has an FPA or floating point co-processor podule.
2029 You may say N here if you are going to load the Acorn FPEmulator
2030 early in the bootup.
2033 bool "Support extended precision"
2034 depends on FPE_NWFPE
2036 Say Y to include 80-bit support in the kernel floating-point
2037 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2038 Note that gcc does not generate 80-bit operations by default,
2039 so in most cases this option only enlarges the size of the
2040 floating point emulator without any good reason.
2042 You almost surely want to say N here.
2045 bool "FastFPE math emulation (EXPERIMENTAL)"
2046 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2048 Say Y here to include the FAST floating point emulator in the kernel.
2049 This is an experimental much faster emulator which now also has full
2050 precision for the mantissa. It does not support any exceptions.
2051 It is very simple, and approximately 3-6 times faster than NWFPE.
2053 It should be sufficient for most programs. It may be not suitable
2054 for scientific calculations, but you have to check this for yourself.
2055 If you do not feel you need a faster FP emulation you should better
2059 bool "VFP-format floating point maths"
2060 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2062 Say Y to include VFP support code in the kernel. This is needed
2063 if your hardware includes a VFP unit.
2065 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2066 release notes and additional status information.
2068 Say N if your target does not have VFP hardware.
2076 bool "Advanced SIMD (NEON) Extension support"
2077 depends on VFPv3 && CPU_V7
2079 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2084 menu "Userspace binary formats"
2086 source "fs/Kconfig.binfmt"
2089 tristate "RISC OS personality"
2092 Say Y here to include the kernel code necessary if you want to run
2093 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2094 experimental; if this sounds frightening, say N and sleep in peace.
2095 You can also say M here to compile this support as a module (which
2096 will be called arthur).
2100 menu "Power management options"
2102 source "kernel/power/Kconfig"
2104 config ARCH_SUSPEND_POSSIBLE
2105 depends on !ARCH_S5P64X0 && !ARCH_S5PC100
2106 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2107 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2112 source "net/Kconfig"
2114 source "drivers/Kconfig"
2118 source "arch/arm/Kconfig.debug"
2120 source "security/Kconfig"
2122 source "crypto/Kconfig"
2124 source "lib/Kconfig"