4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
5 select ARCH_HAS_ELF_RANDOMIZE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_MIGHT_HAVE_PC_PARPORT
10 select ARCH_SUPPORTS_ATOMIC_RMW
11 select ARCH_USE_BUILTIN_BSWAP
12 select ARCH_USE_CMPXCHG_LOCKREF
13 select ARCH_WANT_IPC_PARSE_VERSION
14 select BUILDTIME_EXTABLE_SORT if MMU
15 select CLONE_BACKWARDS
16 select CPU_PM if (SUSPEND || CPU_IDLE)
17 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
19 select EDAC_ATOMIC_SCRUB
20 select GENERIC_ALLOCATOR
21 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
22 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
23 select GENERIC_IDLE_POLL_SETUP
24 select GENERIC_IRQ_PROBE
25 select GENERIC_IRQ_SHOW
26 select GENERIC_IRQ_SHOW_LEVEL
27 select GENERIC_PCI_IOMAP
28 select GENERIC_SCHED_CLOCK
29 select GENERIC_SMP_IDLE_THREAD
30 select GENERIC_STRNCPY_FROM_USER
31 select GENERIC_STRNLEN_USER
32 select HANDLE_DOMAIN_IRQ
33 select HARDIRQS_SW_RESEND
34 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
35 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
36 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32
37 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32
38 select HAVE_ARCH_MMAP_RND_BITS if MMU
39 select HAVE_ARCH_HARDENED_USERCOPY
40 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
41 select HAVE_ARCH_TRACEHOOK
43 select HAVE_CC_STACKPROTECTOR
44 select HAVE_CONTEXT_TRACKING
45 select HAVE_C_RECORDMCOUNT
46 select HAVE_DEBUG_KMEMLEAK
47 select HAVE_DMA_API_DEBUG
49 select HAVE_DMA_CONTIGUOUS if MMU
50 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32
51 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
52 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
53 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
54 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
55 select HAVE_GENERIC_DMA_COHERENT
56 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
57 select HAVE_IDE if PCI || ISA || PCMCIA
58 select HAVE_IRQ_TIME_ACCOUNTING
59 select HAVE_KERNEL_GZIP
60 select HAVE_KERNEL_LZ4
61 select HAVE_KERNEL_LZMA
62 select HAVE_KERNEL_LZO
64 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
65 select HAVE_KRETPROBES if (HAVE_KPROBES)
67 select HAVE_MOD_ARCH_SPECIFIC
68 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
69 select HAVE_OPTPROBES if !THUMB2_KERNEL
70 select HAVE_PERF_EVENTS
72 select HAVE_PERF_USER_STACK_DUMP
73 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
74 select HAVE_REGS_AND_STACK_ACCESS_API
75 select HAVE_SYSCALL_TRACEPOINTS
77 select HAVE_VIRT_CPU_ACCOUNTING_GEN
78 select IRQ_FORCED_THREADING
79 select MODULES_USE_ELF_REL
81 select OF_EARLY_FLATTREE if OF
82 select OF_RESERVED_MEM if OF
84 select OLD_SIGSUSPEND3
85 select PERF_USE_VMALLOC
87 select SYS_SUPPORTS_APM_EMULATION
88 # Above selects are sorted alphabetically; please add new ones
89 # according to that. Thanks.
91 The ARM series is a line of low-power-consumption RISC chip designs
92 licensed by ARM Ltd and targeted at embedded applications and
93 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
94 manufactured, but legacy ARM-based PC hardware remains popular in
95 Europe. There is an ARM Linux project with a web page at
96 <http://www.arm.linux.org.uk/>.
98 config ARM_HAS_SG_CHAIN
99 select ARCH_HAS_SG_CHAIN
102 config NEED_SG_DMA_LENGTH
105 config ARM_DMA_USE_IOMMU
107 select ARM_HAS_SG_CHAIN
108 select NEED_SG_DMA_LENGTH
112 config ARM_DMA_IOMMU_ALIGNMENT
113 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
117 DMA mapping framework by default aligns all buffers to the smallest
118 PAGE_SIZE order which is greater than or equal to the requested buffer
119 size. This works well for buffers up to a few hundreds kilobytes, but
120 for larger buffers it just a waste of address space. Drivers which has
121 relatively small addressing window (like 64Mib) might run out of
122 virtual space with just a few allocations.
124 With this parameter you can specify the maximum PAGE_SIZE order for
125 DMA IOMMU buffers. Larger buffers will be aligned only to this
126 specified order. The order is expressed as a power of two multiplied
131 config MIGHT_HAVE_PCI
134 config SYS_SUPPORTS_APM_EMULATION
139 select GENERIC_ALLOCATOR
150 The Extended Industry Standard Architecture (EISA) bus was
151 developed as an open alternative to the IBM MicroChannel bus.
153 The EISA bus provided some of the features of the IBM MicroChannel
154 bus while maintaining backward compatibility with cards made for
155 the older ISA bus. The EISA bus saw limited use between 1988 and
156 1995 when it was made obsolete by the PCI bus.
158 Say Y here if you are building a kernel for an EISA-based machine.
165 config STACKTRACE_SUPPORT
169 config HAVE_LATENCYTOP_SUPPORT
174 config LOCKDEP_SUPPORT
178 config TRACE_IRQFLAGS_SUPPORT
182 config RWSEM_XCHGADD_ALGORITHM
186 config ARCH_HAS_ILOG2_U32
189 config ARCH_HAS_ILOG2_U64
192 config ARCH_HAS_BANDGAP
195 config FIX_EARLYCON_MEM
198 config GENERIC_HWEIGHT
202 config GENERIC_CALIBRATE_DELAY
206 config ARCH_MAY_HAVE_PC_FDC
212 config NEED_DMA_MAP_STATE
215 config ARCH_SUPPORTS_UPROBES
218 config ARCH_HAS_DMA_SET_COHERENT_MASK
221 config GENERIC_ISA_DMA
227 config NEED_RET_TO_USER
235 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
236 default DRAM_BASE if REMAP_VECTORS_TO_RAM
239 The base address of exception vectors. This must be two pages
242 config ARM_PATCH_PHYS_VIRT
243 bool "Patch physical to virtual translations at runtime" if EMBEDDED
245 depends on !XIP_KERNEL && MMU
246 depends on !ARCH_REALVIEW || !SPARSEMEM
248 Patch phys-to-virt and virt-to-phys translation functions at
249 boot and module load time according to the position of the
250 kernel in system memory.
252 This can only be used with non-XIP MMU kernels where the base
253 of physical memory is at a 16MB boundary.
255 Only disable this option if you know that you do not require
256 this feature (eg, building a kernel for a single machine) and
257 you need to shrink the kernel to the minimal size.
259 config NEED_MACH_IO_H
262 Select this when mach/io.h is required to provide special
263 definitions for this platform. The need for mach/io.h should
264 be avoided when possible.
266 config NEED_MACH_MEMORY_H
269 Select this when mach/memory.h is required to provide special
270 definitions for this platform. The need for mach/memory.h should
271 be avoided when possible.
274 hex "Physical address of main memory" if MMU
275 depends on !ARM_PATCH_PHYS_VIRT
276 default DRAM_BASE if !MMU
277 default 0x00000000 if ARCH_EBSA110 || \
282 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
283 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
284 default 0x20000000 if ARCH_S5PV210
285 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
286 default 0xc0000000 if ARCH_SA1100
288 Please provide the physical address corresponding to the
289 location of main memory in your system.
295 config PGTABLE_LEVELS
297 default 3 if ARM_LPAE
300 source "init/Kconfig"
302 source "kernel/Kconfig.freezer"
307 bool "MMU-based Paged Memory Management Support"
310 Select if you want MMU-based virtualised addressing space
311 support by paged memory management. If unsure, say 'Y'.
313 config ARCH_MMAP_RND_BITS_MIN
316 config ARCH_MMAP_RND_BITS_MAX
317 default 14 if PAGE_OFFSET=0x40000000
318 default 15 if PAGE_OFFSET=0x80000000
322 # The "ARM system type" choice list is ordered alphabetically by option
323 # text. Please add new entries in the option alphabetic order.
326 prompt "ARM system type"
327 default ARCH_VERSATILE if !MMU
328 default ARCH_MULTIPLATFORM if MMU
330 config ARCH_MULTIPLATFORM
331 bool "Allow multiple platforms to be selected"
333 select ARCH_WANT_OPTIONAL_GPIOLIB
334 select ARM_HAS_SG_CHAIN
335 select ARM_PATCH_PHYS_VIRT
339 select GENERIC_CLOCKEVENTS
340 select MIGHT_HAVE_PCI
341 select MULTI_IRQ_HANDLER
345 config ARM_SINGLE_ARMV7M
346 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
348 select ARCH_WANT_OPTIONAL_GPIOLIB
354 select GENERIC_CLOCKEVENTS
360 bool "ARM Ltd. RealView family"
361 select ARCH_WANT_OPTIONAL_GPIOLIB
363 select ARM_TIMER_SP804
365 select COMMON_CLK_VERSATILE
366 select GENERIC_CLOCKEVENTS
367 select GPIO_PL061 if GPIOLIB
369 select NEED_MACH_MEMORY_H
370 select PLAT_VERSATILE
371 select PLAT_VERSATILE_SCHED_CLOCK
373 This enables support for ARM Ltd RealView boards.
375 config ARCH_VERSATILE
376 bool "ARM Ltd. Versatile family"
377 select ARCH_WANT_OPTIONAL_GPIOLIB
379 select ARM_TIMER_SP804
382 select GENERIC_CLOCKEVENTS
383 select HAVE_MACH_CLKDEV
385 select PLAT_VERSATILE
386 select PLAT_VERSATILE_CLOCK
387 select PLAT_VERSATILE_SCHED_CLOCK
388 select VERSATILE_FPGA_IRQ
390 This enables support for ARM Ltd Versatile board.
393 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
394 select ARCH_REQUIRE_GPIOLIB
399 select GENERIC_CLOCKEVENTS
403 Support for Cirrus Logic 711x/721x/731x based boards.
406 bool "Cortina Systems Gemini"
407 select ARCH_REQUIRE_GPIOLIB
410 select GENERIC_CLOCKEVENTS
412 Support for the Cortina Systems Gemini family SoCs
416 select ARCH_USES_GETTIMEOFFSET
419 select NEED_MACH_IO_H
420 select NEED_MACH_MEMORY_H
423 This is an evaluation board for the StrongARM processor available
424 from Digital. It has limited hardware on-board, including an
425 Ethernet interface, two PCMCIA sockets, two serial ports and a
430 select ARCH_HAS_HOLES_MEMORYMODEL
431 select ARCH_REQUIRE_GPIOLIB
433 select ARM_PATCH_PHYS_VIRT
439 select GENERIC_CLOCKEVENTS
441 This enables support for the Cirrus EP93xx series of CPUs.
443 config ARCH_FOOTBRIDGE
447 select GENERIC_CLOCKEVENTS
449 select NEED_MACH_IO_H if !MMU
450 select NEED_MACH_MEMORY_H
452 Support for systems based on the DC21285 companion chip
453 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
456 bool "Hilscher NetX based"
460 select GENERIC_CLOCKEVENTS
462 This enables support for systems based on the Hilscher NetX Soc
468 select NEED_MACH_MEMORY_H
469 select NEED_RET_TO_USER
475 Support for Intel's IOP13XX (XScale) family of processors.
480 select ARCH_REQUIRE_GPIOLIB
483 select NEED_RET_TO_USER
487 Support for Intel's 80219 and IOP32X (XScale) family of
493 select ARCH_REQUIRE_GPIOLIB
496 select NEED_RET_TO_USER
500 Support for Intel's IOP33X (XScale) family of processors.
505 select ARCH_HAS_DMA_SET_COHERENT_MASK
506 select ARCH_REQUIRE_GPIOLIB
507 select ARCH_SUPPORTS_BIG_ENDIAN
510 select DMABOUNCE if PCI
511 select GENERIC_CLOCKEVENTS
512 select MIGHT_HAVE_PCI
513 select NEED_MACH_IO_H
514 select USB_EHCI_BIG_ENDIAN_DESC
515 select USB_EHCI_BIG_ENDIAN_MMIO
517 Support for Intel's IXP4XX (XScale) family of processors.
521 select ARCH_REQUIRE_GPIOLIB
523 select GENERIC_CLOCKEVENTS
524 select MIGHT_HAVE_PCI
528 select PLAT_ORION_LEGACY
530 Support for the Marvell Dove SoC 88AP510
533 bool "Marvell MV78xx0"
534 select ARCH_REQUIRE_GPIOLIB
536 select GENERIC_CLOCKEVENTS
539 select PLAT_ORION_LEGACY
541 Support for the following Marvell MV78xx0 series SoCs:
547 select ARCH_REQUIRE_GPIOLIB
549 select GENERIC_CLOCKEVENTS
552 select PLAT_ORION_LEGACY
553 select MULTI_IRQ_HANDLER
555 Support for the following Marvell Orion 5x series SoCs:
556 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
557 Orion-2 (5281), Orion-1-90 (6183).
560 bool "Marvell PXA168/910/MMP2"
562 select ARCH_REQUIRE_GPIOLIB
564 select GENERIC_ALLOCATOR
565 select GENERIC_CLOCKEVENTS
568 select MULTI_IRQ_HANDLER
573 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
576 bool "Micrel/Kendin KS8695"
577 select ARCH_REQUIRE_GPIOLIB
580 select GENERIC_CLOCKEVENTS
581 select NEED_MACH_MEMORY_H
583 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
584 System-on-Chip devices.
587 bool "Nuvoton W90X900 CPU"
588 select ARCH_REQUIRE_GPIOLIB
592 select GENERIC_CLOCKEVENTS
594 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
595 At present, the w90x900 has been renamed nuc900, regarding
596 the ARM series product line, you can login the following
597 link address to know more.
599 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
600 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
604 select ARCH_REQUIRE_GPIOLIB
609 select GENERIC_CLOCKEVENTS
613 Support for the NXP LPC32XX family of processors
616 bool "PXA2xx/PXA3xx-based"
619 select ARCH_REQUIRE_GPIOLIB
620 select ARM_CPU_SUSPEND if PM
626 select GENERIC_CLOCKEVENTS
630 select MULTI_IRQ_HANDLER
634 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
640 select ARCH_MAY_HAVE_PC_FDC
641 select ARCH_SPARSEMEM_ENABLE
642 select ARCH_USES_GETTIMEOFFSET
646 select HAVE_PATA_PLATFORM
648 select NEED_MACH_IO_H
649 select NEED_MACH_MEMORY_H
653 On the Acorn Risc-PC, Linux can support the internal IDE disk and
654 CD-ROM interface, serial and parallel port, and the floppy drive.
659 select ARCH_REQUIRE_GPIOLIB
660 select ARCH_SPARSEMEM_ENABLE
665 select GENERIC_CLOCKEVENTS
669 select MULTI_IRQ_HANDLER
670 select NEED_MACH_MEMORY_H
673 Support for StrongARM 11x0 based boards.
676 bool "Samsung S3C24XX SoCs"
677 select ARCH_REQUIRE_GPIOLIB
680 select CLKSRC_SAMSUNG_PWM
681 select GENERIC_CLOCKEVENTS
683 select HAVE_S3C2410_I2C if I2C
684 select HAVE_S3C2410_WATCHDOG if WATCHDOG
685 select HAVE_S3C_RTC if RTC_CLASS
686 select MULTI_IRQ_HANDLER
687 select NEED_MACH_IO_H
690 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
691 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
692 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
693 Samsung SMDK2410 development board (and derivatives).
696 bool "Samsung S3C64XX"
697 select ARCH_REQUIRE_GPIOLIB
702 select CLKSRC_SAMSUNG_PWM
703 select COMMON_CLK_SAMSUNG
705 select GENERIC_CLOCKEVENTS
707 select HAVE_S3C2410_I2C if I2C
708 select HAVE_S3C2410_WATCHDOG if WATCHDOG
712 select PM_GENERIC_DOMAINS if PM
714 select S3C_GPIO_TRACK
716 select SAMSUNG_WAKEMASK
717 select SAMSUNG_WDT_RESET
719 Samsung S3C64XX series based systems
723 select ARCH_HAS_HOLES_MEMORYMODEL
724 select ARCH_REQUIRE_GPIOLIB
726 select GENERIC_ALLOCATOR
727 select GENERIC_CLOCKEVENTS
728 select GENERIC_IRQ_CHIP
733 Support for TI's DaVinci platform.
738 select ARCH_HAS_HOLES_MEMORYMODEL
740 select ARCH_REQUIRE_GPIOLIB
743 select GENERIC_CLOCKEVENTS
744 select GENERIC_IRQ_CHIP
747 select MULTI_IRQ_HANDLER
748 select NEED_MACH_IO_H if PCCARD
749 select NEED_MACH_MEMORY_H
752 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
756 menu "Multiple platform selection"
757 depends on ARCH_MULTIPLATFORM
759 comment "CPU Core family selection"
762 bool "ARMv4 based platforms (FA526)"
763 depends on !ARCH_MULTI_V6_V7
764 select ARCH_MULTI_V4_V5
767 config ARCH_MULTI_V4T
768 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
769 depends on !ARCH_MULTI_V6_V7
770 select ARCH_MULTI_V4_V5
771 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
772 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
773 CPU_ARM925T || CPU_ARM940T)
776 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
777 depends on !ARCH_MULTI_V6_V7
778 select ARCH_MULTI_V4_V5
779 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
780 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
781 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
783 config ARCH_MULTI_V4_V5
787 bool "ARMv6 based platforms (ARM11)"
788 select ARCH_MULTI_V6_V7
792 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
794 select ARCH_MULTI_V6_V7
798 config ARCH_MULTI_V6_V7
800 select MIGHT_HAVE_CACHE_L2X0
802 config ARCH_MULTI_CPU_AUTO
803 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
809 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
814 select HAVE_ARM_ARCH_TIMER
817 # This is sorted alphabetically by mach-* pathname. However, plat-*
818 # Kconfigs may be included either alphabetically (according to the
819 # plat- suffix) or along side the corresponding mach-* source.
821 source "arch/arm/mach-mvebu/Kconfig"
823 source "arch/arm/mach-alpine/Kconfig"
825 source "arch/arm/mach-asm9260/Kconfig"
827 source "arch/arm/mach-at91/Kconfig"
829 source "arch/arm/mach-axxia/Kconfig"
831 source "arch/arm/mach-bcm/Kconfig"
833 source "arch/arm/mach-berlin/Kconfig"
835 source "arch/arm/mach-clps711x/Kconfig"
837 source "arch/arm/mach-cns3xxx/Kconfig"
839 source "arch/arm/mach-davinci/Kconfig"
841 source "arch/arm/mach-digicolor/Kconfig"
843 source "arch/arm/mach-dove/Kconfig"
845 source "arch/arm/mach-ep93xx/Kconfig"
847 source "arch/arm/mach-footbridge/Kconfig"
849 source "arch/arm/mach-gemini/Kconfig"
851 source "arch/arm/mach-highbank/Kconfig"
853 source "arch/arm/mach-hisi/Kconfig"
855 source "arch/arm/mach-integrator/Kconfig"
857 source "arch/arm/mach-iop32x/Kconfig"
859 source "arch/arm/mach-iop33x/Kconfig"
861 source "arch/arm/mach-iop13xx/Kconfig"
863 source "arch/arm/mach-ixp4xx/Kconfig"
865 source "arch/arm/mach-keystone/Kconfig"
867 source "arch/arm/mach-ks8695/Kconfig"
869 source "arch/arm/mach-meson/Kconfig"
871 source "arch/arm/mach-moxart/Kconfig"
873 source "arch/arm/mach-mv78xx0/Kconfig"
875 source "arch/arm/mach-imx/Kconfig"
877 source "arch/arm/mach-mediatek/Kconfig"
879 source "arch/arm/mach-mxs/Kconfig"
881 source "arch/arm/mach-netx/Kconfig"
883 source "arch/arm/mach-nomadik/Kconfig"
885 source "arch/arm/mach-nspire/Kconfig"
887 source "arch/arm/plat-omap/Kconfig"
889 source "arch/arm/mach-omap1/Kconfig"
891 source "arch/arm/mach-omap2/Kconfig"
893 source "arch/arm/mach-orion5x/Kconfig"
895 source "arch/arm/mach-picoxcell/Kconfig"
897 source "arch/arm/mach-pxa/Kconfig"
898 source "arch/arm/plat-pxa/Kconfig"
900 source "arch/arm/mach-mmp/Kconfig"
902 source "arch/arm/mach-qcom/Kconfig"
904 source "arch/arm/mach-realview/Kconfig"
906 source "arch/arm/mach-rockchip/Kconfig"
908 source "arch/arm/mach-sa1100/Kconfig"
910 source "arch/arm/mach-socfpga/Kconfig"
912 source "arch/arm/mach-spear/Kconfig"
914 source "arch/arm/mach-sti/Kconfig"
916 source "arch/arm/mach-s3c24xx/Kconfig"
918 source "arch/arm/mach-s3c64xx/Kconfig"
920 source "arch/arm/mach-s5pv210/Kconfig"
922 source "arch/arm/mach-exynos/Kconfig"
923 source "arch/arm/plat-samsung/Kconfig"
925 source "arch/arm/mach-shmobile/Kconfig"
927 source "arch/arm/mach-sunxi/Kconfig"
929 source "arch/arm/mach-prima2/Kconfig"
931 source "arch/arm/mach-tegra/Kconfig"
933 source "arch/arm/mach-u300/Kconfig"
935 source "arch/arm/mach-uniphier/Kconfig"
937 source "arch/arm/mach-ux500/Kconfig"
939 source "arch/arm/mach-versatile/Kconfig"
941 source "arch/arm/mach-vexpress/Kconfig"
942 source "arch/arm/plat-versatile/Kconfig"
944 source "arch/arm/mach-vt8500/Kconfig"
946 source "arch/arm/mach-w90x900/Kconfig"
948 source "arch/arm/mach-zx/Kconfig"
950 source "arch/arm/mach-zynq/Kconfig"
952 # ARMv7-M architecture
954 bool "Energy Micro efm32"
955 depends on ARM_SINGLE_ARMV7M
956 select ARCH_REQUIRE_GPIOLIB
958 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
962 bool "NXP LPC18xx/LPC43xx"
963 depends on ARM_SINGLE_ARMV7M
964 select ARCH_HAS_RESET_CONTROLLER
966 select CLKSRC_LPC32XX
969 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
970 high performance microcontrollers.
973 bool "STMicrolectronics STM32"
974 depends on ARM_SINGLE_ARMV7M
975 select ARCH_HAS_RESET_CONTROLLER
976 select ARMV7M_SYSTICK
978 select RESET_CONTROLLER
980 Support for STMicroelectronics STM32 processors.
982 # Definitions to make life easier
988 select GENERIC_CLOCKEVENTS
994 select GENERIC_IRQ_CHIP
997 config PLAT_ORION_LEGACY
1004 config PLAT_VERSATILE
1007 source "arch/arm/firmware/Kconfig"
1009 source arch/arm/mm/Kconfig
1012 bool "Enable iWMMXt support"
1013 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1014 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1016 Enable support for iWMMXt context switching at run time if
1017 running on a CPU that supports it.
1019 config MULTI_IRQ_HANDLER
1022 Allow each machine to specify it's own IRQ handler at run time.
1025 source "arch/arm/Kconfig-nommu"
1028 config PJ4B_ERRATA_4742
1029 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1030 depends on CPU_PJ4B && MACH_ARMADA_370
1033 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1034 Event (WFE) IDLE states, a specific timing sensitivity exists between
1035 the retiring WFI/WFE instructions and the newly issued subsequent
1036 instructions. This sensitivity can result in a CPU hang scenario.
1038 The software must insert either a Data Synchronization Barrier (DSB)
1039 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1042 config ARM_ERRATA_326103
1043 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1046 Executing a SWP instruction to read-only memory does not set bit 11
1047 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1048 treat the access as a read, preventing a COW from occurring and
1049 causing the faulting task to livelock.
1051 config ARM_ERRATA_411920
1052 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1053 depends on CPU_V6 || CPU_V6K
1055 Invalidation of the Instruction Cache operation can
1056 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1057 It does not affect the MPCore. This option enables the ARM Ltd.
1058 recommended workaround.
1060 config ARM_ERRATA_430973
1061 bool "ARM errata: Stale prediction on replaced interworking branch"
1064 This option enables the workaround for the 430973 Cortex-A8
1065 r1p* erratum. If a code sequence containing an ARM/Thumb
1066 interworking branch is replaced with another code sequence at the
1067 same virtual address, whether due to self-modifying code or virtual
1068 to physical address re-mapping, Cortex-A8 does not recover from the
1069 stale interworking branch prediction. This results in Cortex-A8
1070 executing the new code sequence in the incorrect ARM or Thumb state.
1071 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1072 and also flushes the branch target cache at every context switch.
1073 Note that setting specific bits in the ACTLR register may not be
1074 available in non-secure mode.
1076 config ARM_ERRATA_458693
1077 bool "ARM errata: Processor deadlock when a false hazard is created"
1079 depends on !ARCH_MULTIPLATFORM
1081 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1082 erratum. For very specific sequences of memory operations, it is
1083 possible for a hazard condition intended for a cache line to instead
1084 be incorrectly associated with a different cache line. This false
1085 hazard might then cause a processor deadlock. The workaround enables
1086 the L1 caching of the NEON accesses and disables the PLD instruction
1087 in the ACTLR register. Note that setting specific bits in the ACTLR
1088 register may not be available in non-secure mode.
1090 config ARM_ERRATA_460075
1091 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1093 depends on !ARCH_MULTIPLATFORM
1095 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1096 erratum. Any asynchronous access to the L2 cache may encounter a
1097 situation in which recent store transactions to the L2 cache are lost
1098 and overwritten with stale memory contents from external memory. The
1099 workaround disables the write-allocate mode for the L2 cache via the
1100 ACTLR register. Note that setting specific bits in the ACTLR register
1101 may not be available in non-secure mode.
1103 config ARM_ERRATA_742230
1104 bool "ARM errata: DMB operation may be faulty"
1105 depends on CPU_V7 && SMP
1106 depends on !ARCH_MULTIPLATFORM
1108 This option enables the workaround for the 742230 Cortex-A9
1109 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1110 between two write operations may not ensure the correct visibility
1111 ordering of the two writes. This workaround sets a specific bit in
1112 the diagnostic register of the Cortex-A9 which causes the DMB
1113 instruction to behave as a DSB, ensuring the correct behaviour of
1116 config ARM_ERRATA_742231
1117 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1118 depends on CPU_V7 && SMP
1119 depends on !ARCH_MULTIPLATFORM
1121 This option enables the workaround for the 742231 Cortex-A9
1122 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1123 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1124 accessing some data located in the same cache line, may get corrupted
1125 data due to bad handling of the address hazard when the line gets
1126 replaced from one of the CPUs at the same time as another CPU is
1127 accessing it. This workaround sets specific bits in the diagnostic
1128 register of the Cortex-A9 which reduces the linefill issuing
1129 capabilities of the processor.
1131 config ARM_ERRATA_643719
1132 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1133 depends on CPU_V7 && SMP
1136 This option enables the workaround for the 643719 Cortex-A9 (prior to
1137 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1138 register returns zero when it should return one. The workaround
1139 corrects this value, ensuring cache maintenance operations which use
1140 it behave as intended and avoiding data corruption.
1142 config ARM_ERRATA_720789
1143 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1146 This option enables the workaround for the 720789 Cortex-A9 (prior to
1147 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1148 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1149 As a consequence of this erratum, some TLB entries which should be
1150 invalidated are not, resulting in an incoherency in the system page
1151 tables. The workaround changes the TLB flushing routines to invalidate
1152 entries regardless of the ASID.
1154 config ARM_ERRATA_743622
1155 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1157 depends on !ARCH_MULTIPLATFORM
1159 This option enables the workaround for the 743622 Cortex-A9
1160 (r2p*) erratum. Under very rare conditions, a faulty
1161 optimisation in the Cortex-A9 Store Buffer may lead to data
1162 corruption. This workaround sets a specific bit in the diagnostic
1163 register of the Cortex-A9 which disables the Store Buffer
1164 optimisation, preventing the defect from occurring. This has no
1165 visible impact on the overall performance or power consumption of the
1168 config ARM_ERRATA_751472
1169 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1171 depends on !ARCH_MULTIPLATFORM
1173 This option enables the workaround for the 751472 Cortex-A9 (prior
1174 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1175 completion of a following broadcasted operation if the second
1176 operation is received by a CPU before the ICIALLUIS has completed,
1177 potentially leading to corrupted entries in the cache or TLB.
1179 config ARM_ERRATA_754322
1180 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1183 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1184 r3p*) erratum. A speculative memory access may cause a page table walk
1185 which starts prior to an ASID switch but completes afterwards. This
1186 can populate the micro-TLB with a stale entry which may be hit with
1187 the new ASID. This workaround places two dsb instructions in the mm
1188 switching code so that no page table walks can cross the ASID switch.
1190 config ARM_ERRATA_754327
1191 bool "ARM errata: no automatic Store Buffer drain"
1192 depends on CPU_V7 && SMP
1194 This option enables the workaround for the 754327 Cortex-A9 (prior to
1195 r2p0) erratum. The Store Buffer does not have any automatic draining
1196 mechanism and therefore a livelock may occur if an external agent
1197 continuously polls a memory location waiting to observe an update.
1198 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1199 written polling loops from denying visibility of updates to memory.
1201 config ARM_ERRATA_364296
1202 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1205 This options enables the workaround for the 364296 ARM1136
1206 r0p2 erratum (possible cache data corruption with
1207 hit-under-miss enabled). It sets the undocumented bit 31 in
1208 the auxiliary control register and the FI bit in the control
1209 register, thus disabling hit-under-miss without putting the
1210 processor into full low interrupt latency mode. ARM11MPCore
1213 config ARM_ERRATA_764369
1214 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1215 depends on CPU_V7 && SMP
1217 This option enables the workaround for erratum 764369
1218 affecting Cortex-A9 MPCore with two or more processors (all
1219 current revisions). Under certain timing circumstances, a data
1220 cache line maintenance operation by MVA targeting an Inner
1221 Shareable memory region may fail to proceed up to either the
1222 Point of Coherency or to the Point of Unification of the
1223 system. This workaround adds a DSB instruction before the
1224 relevant cache maintenance functions and sets a specific bit
1225 in the diagnostic control register of the SCU.
1227 config ARM_ERRATA_775420
1228 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1231 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1232 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1233 operation aborts with MMU exception, it might cause the processor
1234 to deadlock. This workaround puts DSB before executing ISB if
1235 an abort may occur on cache maintenance.
1237 config ARM_ERRATA_798181
1238 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1239 depends on CPU_V7 && SMP
1241 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1242 adequately shooting down all use of the old entries. This
1243 option enables the Linux kernel workaround for this erratum
1244 which sends an IPI to the CPUs that are running the same ASID
1245 as the one being invalidated.
1247 config ARM_ERRATA_773022
1248 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1251 This option enables the workaround for the 773022 Cortex-A15
1252 (up to r0p4) erratum. In certain rare sequences of code, the
1253 loop buffer may deliver incorrect instructions. This
1254 workaround disables the loop buffer to avoid the erratum.
1258 source "arch/arm/common/Kconfig"
1265 Find out whether you have ISA slots on your motherboard. ISA is the
1266 name of a bus system, i.e. the way the CPU talks to the other stuff
1267 inside your box. Other bus systems are PCI, EISA, MicroChannel
1268 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1269 newer boards don't support it. If you have ISA, say Y, otherwise N.
1271 # Select ISA DMA controller support
1276 # Select ISA DMA interface
1281 bool "PCI support" if MIGHT_HAVE_PCI
1283 Find out whether you have a PCI motherboard. PCI is the name of a
1284 bus system, i.e. the way the CPU talks to the other stuff inside
1285 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1286 VESA. If you have PCI, say Y, otherwise N.
1292 config PCI_DOMAINS_GENERIC
1293 def_bool PCI_DOMAINS
1295 config PCI_NANOENGINE
1296 bool "BSE nanoEngine PCI support"
1297 depends on SA1100_NANOENGINE
1299 Enable PCI on the BSE nanoEngine board.
1304 config PCI_HOST_ITE8152
1306 depends on PCI && MACH_ARMCORE
1310 source "drivers/pci/Kconfig"
1311 source "drivers/pci/pcie/Kconfig"
1313 source "drivers/pcmcia/Kconfig"
1317 menu "Kernel Features"
1322 This option should be selected by machines which have an SMP-
1325 The only effect of this option is to make the SMP-related
1326 options available to the user for configuration.
1329 bool "Symmetric Multi-Processing"
1330 depends on CPU_V6K || CPU_V7
1331 depends on GENERIC_CLOCKEVENTS
1333 depends on MMU || ARM_MPU
1336 This enables support for systems with more than one CPU. If you have
1337 a system with only one CPU, say N. If you have a system with more
1338 than one CPU, say Y.
1340 If you say N here, the kernel will run on uni- and multiprocessor
1341 machines, but will use only one CPU of a multiprocessor machine. If
1342 you say Y here, the kernel will run on many, but not all,
1343 uniprocessor machines. On a uniprocessor machine, the kernel
1344 will run faster if you say N here.
1346 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1347 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1348 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1350 If you don't know what to do here, say N.
1353 bool "Allow booting SMP kernel on uniprocessor systems"
1354 depends on SMP && !XIP_KERNEL && MMU
1357 SMP kernels contain instructions which fail on non-SMP processors.
1358 Enabling this option allows the kernel to modify itself to make
1359 these instructions safe. Disabling it allows about 1K of space
1362 If you don't know what to do here, say Y.
1364 config ARM_CPU_TOPOLOGY
1365 bool "Support cpu topology definition"
1366 depends on SMP && CPU_V7
1369 Support ARM cpu topology definition. The MPIDR register defines
1370 affinity between processors which is then used to describe the cpu
1371 topology of an ARM System.
1374 bool "Multi-core scheduler support"
1375 depends on ARM_CPU_TOPOLOGY
1377 Multi-core scheduler support improves the CPU scheduler's decision
1378 making when dealing with multi-core CPU chips at a cost of slightly
1379 increased overhead in some places. If unsure say N here.
1382 bool "SMT scheduler support"
1383 depends on ARM_CPU_TOPOLOGY
1385 Improves the CPU scheduler's decision making when dealing with
1386 MultiThreading at a cost of slightly increased overhead in some
1387 places. If unsure say N here.
1392 This option enables support for the ARM system coherency unit
1394 config HAVE_ARM_ARCH_TIMER
1395 bool "Architected timer support"
1397 select ARM_ARCH_TIMER
1398 select GENERIC_CLOCKEVENTS
1400 This option enables support for the ARM architected timer
1404 select CLKSRC_OF if OF
1406 This options enables support for the ARM timer and watchdog unit
1409 bool "Multi-Cluster Power Management"
1410 depends on CPU_V7 && SMP
1412 This option provides the common power management infrastructure
1413 for (multi-)cluster based systems, such as big.LITTLE based
1416 config MCPM_QUAD_CLUSTER
1420 To avoid wasting resources unnecessarily, MCPM only supports up
1421 to 2 clusters by default.
1422 Platforms with 3 or 4 clusters that use MCPM must select this
1423 option to allow the additional clusters to be managed.
1426 bool "big.LITTLE support (Experimental)"
1427 depends on CPU_V7 && SMP
1430 This option enables support selections for the big.LITTLE
1431 system architecture.
1434 bool "big.LITTLE switcher support"
1435 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1436 select ARM_CPU_SUSPEND
1439 The big.LITTLE "switcher" provides the core functionality to
1440 transparently handle transition between a cluster of A15's
1441 and a cluster of A7's in a big.LITTLE system.
1443 config BL_SWITCHER_DUMMY_IF
1444 tristate "Simple big.LITTLE switcher user interface"
1445 depends on BL_SWITCHER && DEBUG_KERNEL
1447 This is a simple and dummy char dev interface to control
1448 the big.LITTLE switcher core code. It is meant for
1449 debugging purposes only.
1452 prompt "Memory split"
1456 Select the desired split between kernel and user memory.
1458 If you are not absolutely sure what you are doing, leave this
1462 bool "3G/1G user/kernel split"
1463 config VMSPLIT_3G_OPT
1464 bool "3G/1G user/kernel split (for full 1G low memory)"
1466 bool "2G/2G user/kernel split"
1468 bool "1G/3G user/kernel split"
1473 default PHYS_OFFSET if !MMU
1474 default 0x40000000 if VMSPLIT_1G
1475 default 0x80000000 if VMSPLIT_2G
1476 default 0xB0000000 if VMSPLIT_3G_OPT
1480 int "Maximum number of CPUs (2-32)"
1486 bool "Support for hot-pluggable CPUs"
1489 Say Y here to experiment with turning CPUs off and on. CPUs
1490 can be controlled through /sys/devices/system/cpu.
1493 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1497 Say Y here if you want Linux to communicate with system firmware
1498 implementing the PSCI specification for CPU-centric power
1499 management operations described in ARM document number ARM DEN
1500 0022A ("Power State Coordination Interface System Software on
1503 # The GPIO number here must be sorted by descending number. In case of
1504 # a multiplatform kernel, we just want the highest value required by the
1505 # selected platforms.
1508 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1510 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1511 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1512 default 416 if ARCH_SUNXI
1513 default 392 if ARCH_U8500
1514 default 352 if ARCH_VT8500
1515 default 288 if ARCH_ROCKCHIP
1516 default 264 if MACH_H4700
1519 Maximum number of GPIOs in the system.
1521 If unsure, leave the default value.
1523 source kernel/Kconfig.preempt
1527 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1528 ARCH_S5PV210 || ARCH_EXYNOS4
1529 default 128 if SOC_AT91RM9200
1533 depends on HZ_FIXED = 0
1534 prompt "Timer frequency"
1558 default HZ_FIXED if HZ_FIXED != 0
1559 default 100 if HZ_100
1560 default 200 if HZ_200
1561 default 250 if HZ_250
1562 default 300 if HZ_300
1563 default 500 if HZ_500
1567 def_bool HIGH_RES_TIMERS
1569 config THUMB2_KERNEL
1570 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1571 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1572 default y if CPU_THUMBONLY
1574 select ARM_ASM_UNIFIED
1577 By enabling this option, the kernel will be compiled in
1578 Thumb-2 mode. A compiler/assembler that understand the unified
1579 ARM-Thumb syntax is needed.
1583 config THUMB2_AVOID_R_ARM_THM_JUMP11
1584 bool "Work around buggy Thumb-2 short branch relocations in gas"
1585 depends on THUMB2_KERNEL && MODULES
1588 Various binutils versions can resolve Thumb-2 branches to
1589 locally-defined, preemptible global symbols as short-range "b.n"
1590 branch instructions.
1592 This is a problem, because there's no guarantee the final
1593 destination of the symbol, or any candidate locations for a
1594 trampoline, are within range of the branch. For this reason, the
1595 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1596 relocation in modules at all, and it makes little sense to add
1599 The symptom is that the kernel fails with an "unsupported
1600 relocation" error when loading some modules.
1602 Until fixed tools are available, passing
1603 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1604 code which hits this problem, at the cost of a bit of extra runtime
1605 stack usage in some cases.
1607 The problem is described in more detail at:
1608 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1610 Only Thumb-2 kernels are affected.
1612 Unless you are sure your tools don't have this problem, say Y.
1614 config ARM_ASM_UNIFIED
1618 bool "Use the ARM EABI to compile the kernel"
1620 This option allows for the kernel to be compiled using the latest
1621 ARM ABI (aka EABI). This is only useful if you are using a user
1622 space environment that is also compiled with EABI.
1624 Since there are major incompatibilities between the legacy ABI and
1625 EABI, especially with regard to structure member alignment, this
1626 option also changes the kernel syscall calling convention to
1627 disambiguate both ABIs and allow for backward compatibility support
1628 (selected with CONFIG_OABI_COMPAT).
1630 To use this you need GCC version 4.0.0 or later.
1633 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1634 depends on AEABI && !THUMB2_KERNEL
1636 This option preserves the old syscall interface along with the
1637 new (ARM EABI) one. It also provides a compatibility layer to
1638 intercept syscalls that have structure arguments which layout
1639 in memory differs between the legacy ABI and the new ARM EABI
1640 (only for non "thumb" binaries). This option adds a tiny
1641 overhead to all syscalls and produces a slightly larger kernel.
1643 The seccomp filter system will not be available when this is
1644 selected, since there is no way yet to sensibly distinguish
1645 between calling conventions during filtering.
1647 If you know you'll be using only pure EABI user space then you
1648 can say N here. If this option is not selected and you attempt
1649 to execute a legacy ABI binary then the result will be
1650 UNPREDICTABLE (in fact it can be predicted that it won't work
1651 at all). If in doubt say N.
1653 config ARCH_HAS_HOLES_MEMORYMODEL
1656 config ARCH_SPARSEMEM_ENABLE
1659 config ARCH_SPARSEMEM_DEFAULT
1660 def_bool ARCH_SPARSEMEM_ENABLE
1662 config ARCH_SELECT_MEMORY_MODEL
1663 def_bool ARCH_SPARSEMEM_ENABLE
1665 config HAVE_ARCH_PFN_VALID
1666 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1668 config HAVE_GENERIC_RCU_GUP
1673 bool "High Memory Support"
1676 The address space of ARM processors is only 4 Gigabytes large
1677 and it has to accommodate user address space, kernel address
1678 space as well as some memory mapped IO. That means that, if you
1679 have a large amount of physical memory and/or IO, not all of the
1680 memory can be "permanently mapped" by the kernel. The physical
1681 memory that is not permanently mapped is called "high memory".
1683 Depending on the selected kernel/user memory split, minimum
1684 vmalloc space and actual amount of RAM, you may not need this
1685 option which should result in a slightly faster kernel.
1690 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1694 The VM uses one page of physical memory for each page table.
1695 For systems with a lot of processes, this can use a lot of
1696 precious low memory, eventually leading to low memory being
1697 consumed by page tables. Setting this option will allow
1698 user-space 2nd level page tables to reside in high memory.
1700 config CPU_SW_DOMAIN_PAN
1701 bool "Enable use of CPU domains to implement privileged no-access"
1702 depends on MMU && !ARM_LPAE
1705 Increase kernel security by ensuring that normal kernel accesses
1706 are unable to access userspace addresses. This can help prevent
1707 use-after-free bugs becoming an exploitable privilege escalation
1708 by ensuring that magic values (such as LIST_POISON) will always
1709 fault when dereferenced.
1711 CPUs with low-vector mappings use a best-efforts implementation.
1712 Their lower 1MB needs to remain accessible for the vectors, but
1713 the remainder of userspace will become appropriately inaccessible.
1715 config HW_PERF_EVENTS
1719 config SYS_SUPPORTS_HUGETLBFS
1723 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1727 config ARCH_WANT_GENERAL_HUGETLB
1730 config ARM_MODULE_PLTS
1731 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1734 Allocate PLTs when loading modules so that jumps and calls whose
1735 targets are too far away for their relative offsets to be encoded
1736 in the instructions themselves can be bounced via veneers in the
1737 module's PLT. This allows modules to be allocated in the generic
1738 vmalloc area after the dedicated module memory area has been
1739 exhausted. The modules will use slightly more memory, but after
1740 rounding up to page size, the actual memory footprint is usually
1743 Say y if you are getting out of memory errors while loading modules
1747 config FORCE_MAX_ZONEORDER
1748 int "Maximum zone order"
1749 default "12" if SOC_AM33XX
1750 default "9" if SA1111 || ARCH_EFM32
1753 The kernel memory allocator divides physically contiguous memory
1754 blocks into "zones", where each zone is a power of two number of
1755 pages. This option selects the largest power of two that the kernel
1756 keeps in the memory allocator. If you need to allocate very large
1757 blocks of physically contiguous memory, then you may need to
1758 increase this value.
1760 This config option is actually maximum order plus one. For example,
1761 a value of 11 means that the largest free memory block is 2^10 pages.
1763 config ALIGNMENT_TRAP
1765 depends on CPU_CP15_MMU
1766 default y if !ARCH_EBSA110
1767 select HAVE_PROC_CPU if PROC_FS
1769 ARM processors cannot fetch/store information which is not
1770 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1771 address divisible by 4. On 32-bit ARM processors, these non-aligned
1772 fetch/store instructions will be emulated in software if you say
1773 here, which has a severe performance impact. This is necessary for
1774 correct operation of some network protocols. With an IP-only
1775 configuration it is safe to say N, otherwise say Y.
1777 config UACCESS_WITH_MEMCPY
1778 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1780 default y if CPU_FEROCEON
1782 Implement faster copy_to_user and clear_user methods for CPU
1783 cores where a 8-word STM instruction give significantly higher
1784 memory write throughput than a sequence of individual 32bit stores.
1786 A possible side effect is a slight increase in scheduling latency
1787 between threads sharing the same address space if they invoke
1788 such copy operations with large buffers.
1790 However, if the CPU data cache is using a write-allocate mode,
1791 this option is unlikely to provide any performance gain.
1795 prompt "Enable seccomp to safely compute untrusted bytecode"
1797 This kernel feature is useful for number crunching applications
1798 that may need to compute untrusted bytecode during their
1799 execution. By using pipes or other transports made available to
1800 the process as file descriptors supporting the read/write
1801 syscalls, it's possible to isolate those applications in
1802 their own address space using seccomp. Once seccomp is
1803 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1804 and the task is only allowed to execute a few safe syscalls
1805 defined by each seccomp mode.
1818 bool "Xen guest support on ARM"
1819 depends on ARM && AEABI && OF
1820 depends on CPU_V7 && !CPU_V6
1821 depends on !GENERIC_ATOMIC64
1823 select ARCH_DMA_ADDR_T_64BIT
1827 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1829 config ARM_FLUSH_CONSOLE_ON_RESTART
1830 bool "Force flush the console on restart"
1832 If the console is locked while the system is rebooted, the messages
1833 in the temporary logbuffer would not have propogated to all the
1834 console drivers. This option forces the console lock to be
1835 released if it failed to be acquired, which will cause all the
1836 pending messages to be flushed.
1843 bool "Flattened Device Tree support"
1847 Include support for flattened device tree machine descriptions.
1850 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1853 This is the traditional way of passing data to the kernel at boot
1854 time. If you are solely relying on the flattened device tree (or
1855 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1856 to remove ATAGS support from your kernel binary. If unsure,
1859 config DEPRECATED_PARAM_STRUCT
1860 bool "Provide old way to pass kernel parameters"
1863 This was deprecated in 2001 and announced to live on for 5 years.
1864 Some old boot loaders still use this way.
1866 config BUILD_ARM_APPENDED_DTB_IMAGE
1867 bool "Build a concatenated zImage/dtb by default"
1870 Enabling this option will cause a concatenated zImage and list of
1871 DTBs to be built by default (instead of a standalone zImage.)
1872 The image will built in arch/arm/boot/zImage-dtb
1874 config BUILD_ARM_APPENDED_DTB_IMAGE_NAMES
1875 string "Default dtb names"
1876 depends on BUILD_ARM_APPENDED_DTB_IMAGE
1878 Space separated list of names of dtbs to append when
1879 building a concatenated zImage-dtb.
1881 # Compressed boot loader in ROM. Yes, we really want to ask about
1882 # TEXT and BSS so we preserve their values in the config files.
1883 config ZBOOT_ROM_TEXT
1884 hex "Compressed ROM boot loader base address"
1887 The physical address at which the ROM-able zImage is to be
1888 placed in the target. Platforms which normally make use of
1889 ROM-able zImage formats normally set this to a suitable
1890 value in their defconfig file.
1892 If ZBOOT_ROM is not enabled, this has no effect.
1894 config ZBOOT_ROM_BSS
1895 hex "Compressed ROM boot loader BSS address"
1898 The base address of an area of read/write memory in the target
1899 for the ROM-able zImage which must be available while the
1900 decompressor is running. It must be large enough to hold the
1901 entire decompressed kernel plus an additional 128 KiB.
1902 Platforms which normally make use of ROM-able zImage formats
1903 normally set this to a suitable value in their defconfig file.
1905 If ZBOOT_ROM is not enabled, this has no effect.
1908 bool "Compressed boot loader in ROM/flash"
1909 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1910 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1912 Say Y here if you intend to execute your compressed kernel image
1913 (zImage) directly from ROM or flash. If unsure, say N.
1915 config ARM_APPENDED_DTB
1916 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1919 With this option, the boot code will look for a device tree binary
1920 (DTB) appended to zImage
1921 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1923 This is meant as a backward compatibility convenience for those
1924 systems with a bootloader that can't be upgraded to accommodate
1925 the documented boot protocol using a device tree.
1927 Beware that there is very little in terms of protection against
1928 this option being confused by leftover garbage in memory that might
1929 look like a DTB header after a reboot if no actual DTB is appended
1930 to zImage. Do not leave this option active in a production kernel
1931 if you don't intend to always append a DTB. Proper passing of the
1932 location into r2 of a bootloader provided DTB is always preferable
1935 config ARM_ATAG_DTB_COMPAT
1936 bool "Supplement the appended DTB with traditional ATAG information"
1937 depends on ARM_APPENDED_DTB
1939 Some old bootloaders can't be updated to a DTB capable one, yet
1940 they provide ATAGs with memory configuration, the ramdisk address,
1941 the kernel cmdline string, etc. Such information is dynamically
1942 provided by the bootloader and can't always be stored in a static
1943 DTB. To allow a device tree enabled kernel to be used with such
1944 bootloaders, this option allows zImage to extract the information
1945 from the ATAG list and store it at run time into the appended DTB.
1948 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1949 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1951 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1952 bool "Use bootloader kernel arguments if available"
1954 Uses the command-line options passed by the boot loader instead of
1955 the device tree bootargs property. If the boot loader doesn't provide
1956 any, the device tree bootargs property will be used.
1958 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1959 bool "Extend with bootloader kernel arguments"
1961 The command-line arguments provided by the boot loader will be
1962 appended to the the device tree bootargs property.
1967 string "Default kernel command string"
1970 On some architectures (EBSA110 and CATS), there is currently no way
1971 for the boot loader to pass arguments to the kernel. For these
1972 architectures, you should supply some command-line options at build
1973 time by entering them here. As a minimum, you should specify the
1974 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1977 prompt "Kernel command line type" if CMDLINE != ""
1978 default CMDLINE_FROM_BOOTLOADER
1981 config CMDLINE_FROM_BOOTLOADER
1982 bool "Use bootloader kernel arguments if available"
1984 Uses the command-line options passed by the boot loader. If
1985 the boot loader doesn't provide any, the default kernel command
1986 string provided in CMDLINE will be used.
1988 config CMDLINE_EXTEND
1989 bool "Extend bootloader kernel arguments"
1991 The command-line arguments provided by the boot loader will be
1992 appended to the default kernel command string.
1994 config CMDLINE_FORCE
1995 bool "Always use the default kernel command string"
1997 Always use the default kernel command string, even if the boot
1998 loader passes other arguments to the kernel.
1999 This is useful if you cannot or don't want to change the
2000 command-line options your boot loader passes to the kernel.
2004 bool "Kernel Execute-In-Place from ROM"
2005 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
2007 Execute-In-Place allows the kernel to run from non-volatile storage
2008 directly addressable by the CPU, such as NOR flash. This saves RAM
2009 space since the text section of the kernel is not loaded from flash
2010 to RAM. Read-write sections, such as the data section and stack,
2011 are still copied to RAM. The XIP kernel is not compressed since
2012 it has to run directly from flash, so it will take more space to
2013 store it. The flash address used to link the kernel object files,
2014 and for storing it, is configuration dependent. Therefore, if you
2015 say Y here, you must know the proper physical address where to
2016 store the kernel image depending on your own flash memory usage.
2018 Also note that the make target becomes "make xipImage" rather than
2019 "make zImage" or "make Image". The final kernel binary to put in
2020 ROM memory will be arch/arm/boot/xipImage.
2024 config XIP_PHYS_ADDR
2025 hex "XIP Kernel Physical Location"
2026 depends on XIP_KERNEL
2027 default "0x00080000"
2029 This is the physical address in your flash memory the kernel will
2030 be linked for and stored to. This address is dependent on your
2034 bool "Kexec system call (EXPERIMENTAL)"
2035 depends on (!SMP || PM_SLEEP_SMP)
2039 kexec is a system call that implements the ability to shutdown your
2040 current kernel, and to start another kernel. It is like a reboot
2041 but it is independent of the system firmware. And like a reboot
2042 you can start any kernel with it, not just Linux.
2044 It is an ongoing process to be certain the hardware in a machine
2045 is properly shutdown, so do not be surprised if this code does not
2046 initially work for you.
2049 bool "Export atags in procfs"
2050 depends on ATAGS && KEXEC
2053 Should the atags used to boot the kernel be exported in an "atags"
2054 file in procfs. Useful with kexec.
2057 bool "Build kdump crash kernel (EXPERIMENTAL)"
2059 Generate crash dump after being started by kexec. This should
2060 be normally only set in special crash dump kernels which are
2061 loaded in the main kernel with kexec-tools into a specially
2062 reserved region and then later executed after a crash by
2063 kdump/kexec. The crash dump kernel must be compiled to a
2064 memory address not used by the main kernel
2066 For more details see Documentation/kdump/kdump.txt
2068 config AUTO_ZRELADDR
2069 bool "Auto calculation of the decompressed kernel image address"
2071 ZRELADDR is the physical address where the decompressed kernel
2072 image will be placed. If AUTO_ZRELADDR is selected, the address
2073 will be determined at run-time by masking the current IP with
2074 0xf8000000. This assumes the zImage being placed in the first 128MB
2075 from start of memory.
2079 menu "CPU Power Management"
2081 source "drivers/cpufreq/Kconfig"
2083 source "drivers/cpuidle/Kconfig"
2087 menu "Floating point emulation"
2089 comment "At least one emulation must be selected"
2092 bool "NWFPE math emulation"
2093 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2095 Say Y to include the NWFPE floating point emulator in the kernel.
2096 This is necessary to run most binaries. Linux does not currently
2097 support floating point hardware so you need to say Y here even if
2098 your machine has an FPA or floating point co-processor podule.
2100 You may say N here if you are going to load the Acorn FPEmulator
2101 early in the bootup.
2104 bool "Support extended precision"
2105 depends on FPE_NWFPE
2107 Say Y to include 80-bit support in the kernel floating-point
2108 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2109 Note that gcc does not generate 80-bit operations by default,
2110 so in most cases this option only enlarges the size of the
2111 floating point emulator without any good reason.
2113 You almost surely want to say N here.
2116 bool "FastFPE math emulation (EXPERIMENTAL)"
2117 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2119 Say Y here to include the FAST floating point emulator in the kernel.
2120 This is an experimental much faster emulator which now also has full
2121 precision for the mantissa. It does not support any exceptions.
2122 It is very simple, and approximately 3-6 times faster than NWFPE.
2124 It should be sufficient for most programs. It may be not suitable
2125 for scientific calculations, but you have to check this for yourself.
2126 If you do not feel you need a faster FP emulation you should better
2130 bool "VFP-format floating point maths"
2131 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2133 Say Y to include VFP support code in the kernel. This is needed
2134 if your hardware includes a VFP unit.
2136 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2137 release notes and additional status information.
2139 Say N if your target does not have VFP hardware.
2147 bool "Advanced SIMD (NEON) Extension support"
2148 depends on VFPv3 && CPU_V7
2150 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2153 config KERNEL_MODE_NEON
2154 bool "Support for NEON in kernel mode"
2155 depends on NEON && AEABI
2157 Say Y to include support for NEON in kernel mode.
2161 menu "Userspace binary formats"
2163 source "fs/Kconfig.binfmt"
2167 menu "Power management options"
2169 source "kernel/power/Kconfig"
2171 config ARCH_SUSPEND_POSSIBLE
2172 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2173 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2176 config ARM_CPU_SUSPEND
2179 config ARCH_HIBERNATION_POSSIBLE
2182 default y if ARCH_SUSPEND_POSSIBLE
2186 source "net/Kconfig"
2188 source "drivers/Kconfig"
2190 source "drivers/firmware/Kconfig"
2194 source "arch/arm/Kconfig.debug"
2196 source "security/Kconfig"
2198 source "crypto/Kconfig"
2200 source "arch/arm/crypto/Kconfig"
2203 source "lib/Kconfig"
2205 source "arch/arm/kvm/Kconfig"