4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
5 select ARCH_HAS_ELF_RANDOMIZE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_MIGHT_HAVE_PC_PARPORT
10 select ARCH_SUPPORTS_ATOMIC_RMW
11 select ARCH_USE_BUILTIN_BSWAP
12 select ARCH_USE_CMPXCHG_LOCKREF
13 select ARCH_WANT_IPC_PARSE_VERSION
14 select BUILDTIME_EXTABLE_SORT if MMU
15 select CLONE_BACKWARDS
16 select CPU_PM if (SUSPEND || CPU_IDLE)
17 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
19 select EDAC_ATOMIC_SCRUB
20 select GENERIC_ALLOCATOR
21 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
22 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
23 select GENERIC_IDLE_POLL_SETUP
24 select GENERIC_IRQ_PROBE
25 select GENERIC_IRQ_SHOW
26 select GENERIC_IRQ_SHOW_LEVEL
27 select GENERIC_PCI_IOMAP
28 select GENERIC_SCHED_CLOCK
29 select GENERIC_SMP_IDLE_THREAD
30 select GENERIC_STRNCPY_FROM_USER
31 select GENERIC_STRNLEN_USER
32 select HANDLE_DOMAIN_IRQ
33 select HARDIRQS_SW_RESEND
34 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
35 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
36 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32
37 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32
38 select HAVE_ARCH_HARDENED_USERCOPY
39 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
40 select HAVE_ARCH_TRACEHOOK
41 select HAVE_ARM_SMCCC if CPU_V7
43 select HAVE_CC_STACKPROTECTOR
44 select HAVE_CONTEXT_TRACKING
45 select HAVE_C_RECORDMCOUNT
46 select HAVE_DEBUG_KMEMLEAK
47 select HAVE_DMA_API_DEBUG
49 select HAVE_DMA_CONTIGUOUS if MMU
50 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32
51 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
52 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
53 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
54 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
55 select HAVE_GENERIC_DMA_COHERENT
56 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
57 select HAVE_IDE if PCI || ISA || PCMCIA
58 select HAVE_IRQ_TIME_ACCOUNTING
59 select HAVE_KERNEL_GZIP
60 select HAVE_KERNEL_LZ4
61 select HAVE_KERNEL_LZMA
62 select HAVE_KERNEL_LZO
64 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
65 select HAVE_KRETPROBES if (HAVE_KPROBES)
67 select HAVE_MOD_ARCH_SPECIFIC
68 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
69 select HAVE_OPTPROBES if !THUMB2_KERNEL
70 select HAVE_PERF_EVENTS
72 select HAVE_PERF_USER_STACK_DUMP
73 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
74 select HAVE_REGS_AND_STACK_ACCESS_API
75 select HAVE_SYSCALL_TRACEPOINTS
77 select HAVE_VIRT_CPU_ACCOUNTING_GEN
78 select IRQ_FORCED_THREADING
79 select MODULES_USE_ELF_REL
81 select OF_EARLY_FLATTREE if OF
82 select OF_RESERVED_MEM if OF
84 select OLD_SIGSUSPEND3
85 select PERF_USE_VMALLOC
87 select SYS_SUPPORTS_APM_EMULATION
88 # Above selects are sorted alphabetically; please add new ones
89 # according to that. Thanks.
91 The ARM series is a line of low-power-consumption RISC chip designs
92 licensed by ARM Ltd and targeted at embedded applications and
93 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
94 manufactured, but legacy ARM-based PC hardware remains popular in
95 Europe. There is an ARM Linux project with a web page at
96 <http://www.arm.linux.org.uk/>.
98 config ARM_HAS_SG_CHAIN
99 select ARCH_HAS_SG_CHAIN
102 config NEED_SG_DMA_LENGTH
105 config ARM_DMA_USE_IOMMU
107 select ARM_HAS_SG_CHAIN
108 select NEED_SG_DMA_LENGTH
112 config ARM_DMA_IOMMU_ALIGNMENT
113 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
117 DMA mapping framework by default aligns all buffers to the smallest
118 PAGE_SIZE order which is greater than or equal to the requested buffer
119 size. This works well for buffers up to a few hundreds kilobytes, but
120 for larger buffers it just a waste of address space. Drivers which has
121 relatively small addressing window (like 64Mib) might run out of
122 virtual space with just a few allocations.
124 With this parameter you can specify the maximum PAGE_SIZE order for
125 DMA IOMMU buffers. Larger buffers will be aligned only to this
126 specified order. The order is expressed as a power of two multiplied
131 config MIGHT_HAVE_PCI
134 config SYS_SUPPORTS_APM_EMULATION
139 select GENERIC_ALLOCATOR
150 The Extended Industry Standard Architecture (EISA) bus was
151 developed as an open alternative to the IBM MicroChannel bus.
153 The EISA bus provided some of the features of the IBM MicroChannel
154 bus while maintaining backward compatibility with cards made for
155 the older ISA bus. The EISA bus saw limited use between 1988 and
156 1995 when it was made obsolete by the PCI bus.
158 Say Y here if you are building a kernel for an EISA-based machine.
165 config STACKTRACE_SUPPORT
169 config HAVE_LATENCYTOP_SUPPORT
174 config LOCKDEP_SUPPORT
178 config TRACE_IRQFLAGS_SUPPORT
182 config RWSEM_XCHGADD_ALGORITHM
186 config ARCH_HAS_ILOG2_U32
189 config ARCH_HAS_ILOG2_U64
192 config ARCH_HAS_BANDGAP
195 config FIX_EARLYCON_MEM
198 config GENERIC_HWEIGHT
202 config GENERIC_CALIBRATE_DELAY
206 config ARCH_MAY_HAVE_PC_FDC
212 config NEED_DMA_MAP_STATE
215 config ARCH_SUPPORTS_UPROBES
218 config ARCH_HAS_DMA_SET_COHERENT_MASK
221 config GENERIC_ISA_DMA
227 config NEED_RET_TO_USER
235 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
236 default DRAM_BASE if REMAP_VECTORS_TO_RAM
239 The base address of exception vectors. This must be two pages
242 config ARM_PATCH_PHYS_VIRT
243 bool "Patch physical to virtual translations at runtime" if EMBEDDED
245 depends on !XIP_KERNEL && MMU
246 depends on !ARCH_REALVIEW || !SPARSEMEM
248 Patch phys-to-virt and virt-to-phys translation functions at
249 boot and module load time according to the position of the
250 kernel in system memory.
252 This can only be used with non-XIP MMU kernels where the base
253 of physical memory is at a 16MB boundary.
255 Only disable this option if you know that you do not require
256 this feature (eg, building a kernel for a single machine) and
257 you need to shrink the kernel to the minimal size.
259 config NEED_MACH_IO_H
262 Select this when mach/io.h is required to provide special
263 definitions for this platform. The need for mach/io.h should
264 be avoided when possible.
266 config NEED_MACH_MEMORY_H
269 Select this when mach/memory.h is required to provide special
270 definitions for this platform. The need for mach/memory.h should
271 be avoided when possible.
274 hex "Physical address of main memory" if MMU
275 depends on !ARM_PATCH_PHYS_VIRT
276 default DRAM_BASE if !MMU
277 default 0x00000000 if ARCH_EBSA110 || \
282 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
283 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
284 default 0x20000000 if ARCH_S5PV210
285 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
286 default 0xc0000000 if ARCH_SA1100
288 Please provide the physical address corresponding to the
289 location of main memory in your system.
295 config PGTABLE_LEVELS
297 default 3 if ARM_LPAE
300 source "init/Kconfig"
302 source "kernel/Kconfig.freezer"
307 bool "MMU-based Paged Memory Management Support"
310 Select if you want MMU-based virtualised addressing space
311 support by paged memory management. If unsure, say 'Y'.
314 # The "ARM system type" choice list is ordered alphabetically by option
315 # text. Please add new entries in the option alphabetic order.
318 prompt "ARM system type"
319 default ARCH_VERSATILE if !MMU
320 default ARCH_MULTIPLATFORM if MMU
322 config ARCH_MULTIPLATFORM
323 bool "Allow multiple platforms to be selected"
325 select ARCH_WANT_OPTIONAL_GPIOLIB
326 select ARM_HAS_SG_CHAIN
327 select ARM_PATCH_PHYS_VIRT
331 select GENERIC_CLOCKEVENTS
332 select MIGHT_HAVE_PCI
333 select MULTI_IRQ_HANDLER
337 config ARM_SINGLE_ARMV7M
338 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
340 select ARCH_WANT_OPTIONAL_GPIOLIB
346 select GENERIC_CLOCKEVENTS
352 bool "ARM Ltd. RealView family"
353 select ARCH_WANT_OPTIONAL_GPIOLIB
355 select ARM_TIMER_SP804
357 select COMMON_CLK_VERSATILE
358 select GENERIC_CLOCKEVENTS
359 select GPIO_PL061 if GPIOLIB
361 select NEED_MACH_MEMORY_H
362 select PLAT_VERSATILE
363 select PLAT_VERSATILE_SCHED_CLOCK
365 This enables support for ARM Ltd RealView boards.
367 config ARCH_VERSATILE
368 bool "ARM Ltd. Versatile family"
369 select ARCH_WANT_OPTIONAL_GPIOLIB
371 select ARM_TIMER_SP804
374 select GENERIC_CLOCKEVENTS
375 select HAVE_MACH_CLKDEV
377 select PLAT_VERSATILE
378 select PLAT_VERSATILE_CLOCK
379 select PLAT_VERSATILE_SCHED_CLOCK
380 select VERSATILE_FPGA_IRQ
382 This enables support for ARM Ltd Versatile board.
385 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
386 select ARCH_REQUIRE_GPIOLIB
391 select GENERIC_CLOCKEVENTS
395 Support for Cirrus Logic 711x/721x/731x based boards.
398 bool "Cortina Systems Gemini"
399 select ARCH_REQUIRE_GPIOLIB
402 select GENERIC_CLOCKEVENTS
404 Support for the Cortina Systems Gemini family SoCs
408 select ARCH_USES_GETTIMEOFFSET
411 select NEED_MACH_IO_H
412 select NEED_MACH_MEMORY_H
415 This is an evaluation board for the StrongARM processor available
416 from Digital. It has limited hardware on-board, including an
417 Ethernet interface, two PCMCIA sockets, two serial ports and a
422 select ARCH_HAS_HOLES_MEMORYMODEL
423 select ARCH_REQUIRE_GPIOLIB
425 select ARM_PATCH_PHYS_VIRT
431 select GENERIC_CLOCKEVENTS
433 This enables support for the Cirrus EP93xx series of CPUs.
435 config ARCH_FOOTBRIDGE
439 select GENERIC_CLOCKEVENTS
441 select NEED_MACH_IO_H if !MMU
442 select NEED_MACH_MEMORY_H
444 Support for systems based on the DC21285 companion chip
445 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
448 bool "Hilscher NetX based"
452 select GENERIC_CLOCKEVENTS
454 This enables support for systems based on the Hilscher NetX Soc
460 select NEED_MACH_MEMORY_H
461 select NEED_RET_TO_USER
467 Support for Intel's IOP13XX (XScale) family of processors.
472 select ARCH_REQUIRE_GPIOLIB
475 select NEED_RET_TO_USER
479 Support for Intel's 80219 and IOP32X (XScale) family of
485 select ARCH_REQUIRE_GPIOLIB
488 select NEED_RET_TO_USER
492 Support for Intel's IOP33X (XScale) family of processors.
497 select ARCH_HAS_DMA_SET_COHERENT_MASK
498 select ARCH_REQUIRE_GPIOLIB
499 select ARCH_SUPPORTS_BIG_ENDIAN
502 select DMABOUNCE if PCI
503 select GENERIC_CLOCKEVENTS
504 select MIGHT_HAVE_PCI
505 select NEED_MACH_IO_H
506 select USB_EHCI_BIG_ENDIAN_DESC
507 select USB_EHCI_BIG_ENDIAN_MMIO
509 Support for Intel's IXP4XX (XScale) family of processors.
513 select ARCH_REQUIRE_GPIOLIB
515 select GENERIC_CLOCKEVENTS
516 select MIGHT_HAVE_PCI
520 select PLAT_ORION_LEGACY
522 Support for the Marvell Dove SoC 88AP510
525 bool "Marvell MV78xx0"
526 select ARCH_REQUIRE_GPIOLIB
528 select GENERIC_CLOCKEVENTS
531 select PLAT_ORION_LEGACY
533 Support for the following Marvell MV78xx0 series SoCs:
539 select ARCH_REQUIRE_GPIOLIB
541 select GENERIC_CLOCKEVENTS
544 select PLAT_ORION_LEGACY
545 select MULTI_IRQ_HANDLER
547 Support for the following Marvell Orion 5x series SoCs:
548 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
549 Orion-2 (5281), Orion-1-90 (6183).
552 bool "Marvell PXA168/910/MMP2"
554 select ARCH_REQUIRE_GPIOLIB
556 select GENERIC_ALLOCATOR
557 select GENERIC_CLOCKEVENTS
560 select MULTI_IRQ_HANDLER
565 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
568 bool "Micrel/Kendin KS8695"
569 select ARCH_REQUIRE_GPIOLIB
572 select GENERIC_CLOCKEVENTS
573 select NEED_MACH_MEMORY_H
575 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
576 System-on-Chip devices.
579 bool "Nuvoton W90X900 CPU"
580 select ARCH_REQUIRE_GPIOLIB
584 select GENERIC_CLOCKEVENTS
586 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
587 At present, the w90x900 has been renamed nuc900, regarding
588 the ARM series product line, you can login the following
589 link address to know more.
591 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
592 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
596 select ARCH_REQUIRE_GPIOLIB
601 select GENERIC_CLOCKEVENTS
605 Support for the NXP LPC32XX family of processors
608 bool "PXA2xx/PXA3xx-based"
611 select ARCH_REQUIRE_GPIOLIB
612 select ARM_CPU_SUSPEND if PM
618 select GENERIC_CLOCKEVENTS
622 select MULTI_IRQ_HANDLER
626 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
632 select ARCH_MAY_HAVE_PC_FDC
633 select ARCH_SPARSEMEM_ENABLE
634 select ARCH_USES_GETTIMEOFFSET
638 select HAVE_PATA_PLATFORM
640 select NEED_MACH_IO_H
641 select NEED_MACH_MEMORY_H
645 On the Acorn Risc-PC, Linux can support the internal IDE disk and
646 CD-ROM interface, serial and parallel port, and the floppy drive.
651 select ARCH_REQUIRE_GPIOLIB
652 select ARCH_SPARSEMEM_ENABLE
657 select GENERIC_CLOCKEVENTS
661 select MULTI_IRQ_HANDLER
662 select NEED_MACH_MEMORY_H
665 Support for StrongARM 11x0 based boards.
668 bool "Samsung S3C24XX SoCs"
669 select ARCH_REQUIRE_GPIOLIB
672 select CLKSRC_SAMSUNG_PWM
673 select GENERIC_CLOCKEVENTS
675 select HAVE_S3C2410_I2C if I2C
676 select HAVE_S3C2410_WATCHDOG if WATCHDOG
677 select HAVE_S3C_RTC if RTC_CLASS
678 select MULTI_IRQ_HANDLER
679 select NEED_MACH_IO_H
682 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
683 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
684 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
685 Samsung SMDK2410 development board (and derivatives).
688 bool "Samsung S3C64XX"
689 select ARCH_REQUIRE_GPIOLIB
694 select CLKSRC_SAMSUNG_PWM
695 select COMMON_CLK_SAMSUNG
697 select GENERIC_CLOCKEVENTS
699 select HAVE_S3C2410_I2C if I2C
700 select HAVE_S3C2410_WATCHDOG if WATCHDOG
704 select PM_GENERIC_DOMAINS if PM
706 select S3C_GPIO_TRACK
708 select SAMSUNG_WAKEMASK
709 select SAMSUNG_WDT_RESET
711 Samsung S3C64XX series based systems
715 select ARCH_HAS_HOLES_MEMORYMODEL
716 select ARCH_REQUIRE_GPIOLIB
718 select GENERIC_ALLOCATOR
719 select GENERIC_CLOCKEVENTS
720 select GENERIC_IRQ_CHIP
725 Support for TI's DaVinci platform.
730 select ARCH_HAS_HOLES_MEMORYMODEL
732 select ARCH_REQUIRE_GPIOLIB
735 select GENERIC_CLOCKEVENTS
736 select GENERIC_IRQ_CHIP
739 select MULTI_IRQ_HANDLER
740 select NEED_MACH_IO_H if PCCARD
741 select NEED_MACH_MEMORY_H
744 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
748 menu "Multiple platform selection"
749 depends on ARCH_MULTIPLATFORM
751 comment "CPU Core family selection"
754 bool "ARMv4 based platforms (FA526)"
755 depends on !ARCH_MULTI_V6_V7
756 select ARCH_MULTI_V4_V5
759 config ARCH_MULTI_V4T
760 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
761 depends on !ARCH_MULTI_V6_V7
762 select ARCH_MULTI_V4_V5
763 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
764 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
765 CPU_ARM925T || CPU_ARM940T)
768 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
769 depends on !ARCH_MULTI_V6_V7
770 select ARCH_MULTI_V4_V5
771 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
772 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
773 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
775 config ARCH_MULTI_V4_V5
779 bool "ARMv6 based platforms (ARM11)"
780 select ARCH_MULTI_V6_V7
784 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
786 select ARCH_MULTI_V6_V7
790 config ARCH_MULTI_V6_V7
792 select MIGHT_HAVE_CACHE_L2X0
794 config ARCH_MULTI_CPU_AUTO
795 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
801 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
806 select HAVE_ARM_ARCH_TIMER
809 # This is sorted alphabetically by mach-* pathname. However, plat-*
810 # Kconfigs may be included either alphabetically (according to the
811 # plat- suffix) or along side the corresponding mach-* source.
813 source "arch/arm/mach-mvebu/Kconfig"
815 source "arch/arm/mach-alpine/Kconfig"
817 source "arch/arm/mach-asm9260/Kconfig"
819 source "arch/arm/mach-at91/Kconfig"
821 source "arch/arm/mach-axxia/Kconfig"
823 source "arch/arm/mach-bcm/Kconfig"
825 source "arch/arm/mach-berlin/Kconfig"
827 source "arch/arm/mach-clps711x/Kconfig"
829 source "arch/arm/mach-cns3xxx/Kconfig"
831 source "arch/arm/mach-davinci/Kconfig"
833 source "arch/arm/mach-digicolor/Kconfig"
835 source "arch/arm/mach-dove/Kconfig"
837 source "arch/arm/mach-ep93xx/Kconfig"
839 source "arch/arm/mach-footbridge/Kconfig"
841 source "arch/arm/mach-gemini/Kconfig"
843 source "arch/arm/mach-highbank/Kconfig"
845 source "arch/arm/mach-hisi/Kconfig"
847 source "arch/arm/mach-integrator/Kconfig"
849 source "arch/arm/mach-iop32x/Kconfig"
851 source "arch/arm/mach-iop33x/Kconfig"
853 source "arch/arm/mach-iop13xx/Kconfig"
855 source "arch/arm/mach-ixp4xx/Kconfig"
857 source "arch/arm/mach-keystone/Kconfig"
859 source "arch/arm/mach-ks8695/Kconfig"
861 source "arch/arm/mach-meson/Kconfig"
863 source "arch/arm/mach-moxart/Kconfig"
865 source "arch/arm/mach-mv78xx0/Kconfig"
867 source "arch/arm/mach-imx/Kconfig"
869 source "arch/arm/mach-mediatek/Kconfig"
871 source "arch/arm/mach-mxs/Kconfig"
873 source "arch/arm/mach-netx/Kconfig"
875 source "arch/arm/mach-nomadik/Kconfig"
877 source "arch/arm/mach-nspire/Kconfig"
879 source "arch/arm/plat-omap/Kconfig"
881 source "arch/arm/mach-omap1/Kconfig"
883 source "arch/arm/mach-omap2/Kconfig"
885 source "arch/arm/mach-orion5x/Kconfig"
887 source "arch/arm/mach-picoxcell/Kconfig"
889 source "arch/arm/mach-pxa/Kconfig"
890 source "arch/arm/plat-pxa/Kconfig"
892 source "arch/arm/mach-mmp/Kconfig"
894 source "arch/arm/mach-qcom/Kconfig"
896 source "arch/arm/mach-realview/Kconfig"
898 source "arch/arm/mach-rockchip/Kconfig"
900 source "arch/arm/mach-sa1100/Kconfig"
902 source "arch/arm/mach-socfpga/Kconfig"
904 source "arch/arm/mach-spear/Kconfig"
906 source "arch/arm/mach-sti/Kconfig"
908 source "arch/arm/mach-s3c24xx/Kconfig"
910 source "arch/arm/mach-s3c64xx/Kconfig"
912 source "arch/arm/mach-s5pv210/Kconfig"
914 source "arch/arm/mach-exynos/Kconfig"
915 source "arch/arm/plat-samsung/Kconfig"
917 source "arch/arm/mach-shmobile/Kconfig"
919 source "arch/arm/mach-sunxi/Kconfig"
921 source "arch/arm/mach-prima2/Kconfig"
923 source "arch/arm/mach-tegra/Kconfig"
925 source "arch/arm/mach-u300/Kconfig"
927 source "arch/arm/mach-uniphier/Kconfig"
929 source "arch/arm/mach-ux500/Kconfig"
931 source "arch/arm/mach-versatile/Kconfig"
933 source "arch/arm/mach-vexpress/Kconfig"
934 source "arch/arm/plat-versatile/Kconfig"
936 source "arch/arm/mach-vt8500/Kconfig"
938 source "arch/arm/mach-w90x900/Kconfig"
940 source "arch/arm/mach-zx/Kconfig"
942 source "arch/arm/mach-zynq/Kconfig"
944 # ARMv7-M architecture
946 bool "Energy Micro efm32"
947 depends on ARM_SINGLE_ARMV7M
948 select ARCH_REQUIRE_GPIOLIB
950 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
954 bool "NXP LPC18xx/LPC43xx"
955 depends on ARM_SINGLE_ARMV7M
956 select ARCH_HAS_RESET_CONTROLLER
958 select CLKSRC_LPC32XX
961 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
962 high performance microcontrollers.
965 bool "STMicrolectronics STM32"
966 depends on ARM_SINGLE_ARMV7M
967 select ARCH_HAS_RESET_CONTROLLER
968 select ARMV7M_SYSTICK
970 select RESET_CONTROLLER
972 Support for STMicroelectronics STM32 processors.
974 # Definitions to make life easier
980 select GENERIC_CLOCKEVENTS
986 select GENERIC_IRQ_CHIP
989 config PLAT_ORION_LEGACY
996 config PLAT_VERSATILE
999 source "arch/arm/firmware/Kconfig"
1001 source arch/arm/mm/Kconfig
1004 bool "Enable iWMMXt support"
1005 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1006 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1008 Enable support for iWMMXt context switching at run time if
1009 running on a CPU that supports it.
1011 config MULTI_IRQ_HANDLER
1014 Allow each machine to specify it's own IRQ handler at run time.
1017 source "arch/arm/Kconfig-nommu"
1020 config PJ4B_ERRATA_4742
1021 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1022 depends on CPU_PJ4B && MACH_ARMADA_370
1025 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1026 Event (WFE) IDLE states, a specific timing sensitivity exists between
1027 the retiring WFI/WFE instructions and the newly issued subsequent
1028 instructions. This sensitivity can result in a CPU hang scenario.
1030 The software must insert either a Data Synchronization Barrier (DSB)
1031 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1034 config ARM_ERRATA_326103
1035 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1038 Executing a SWP instruction to read-only memory does not set bit 11
1039 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1040 treat the access as a read, preventing a COW from occurring and
1041 causing the faulting task to livelock.
1043 config ARM_ERRATA_411920
1044 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1045 depends on CPU_V6 || CPU_V6K
1047 Invalidation of the Instruction Cache operation can
1048 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1049 It does not affect the MPCore. This option enables the ARM Ltd.
1050 recommended workaround.
1052 config ARM_ERRATA_430973
1053 bool "ARM errata: Stale prediction on replaced interworking branch"
1056 This option enables the workaround for the 430973 Cortex-A8
1057 r1p* erratum. If a code sequence containing an ARM/Thumb
1058 interworking branch is replaced with another code sequence at the
1059 same virtual address, whether due to self-modifying code or virtual
1060 to physical address re-mapping, Cortex-A8 does not recover from the
1061 stale interworking branch prediction. This results in Cortex-A8
1062 executing the new code sequence in the incorrect ARM or Thumb state.
1063 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1064 and also flushes the branch target cache at every context switch.
1065 Note that setting specific bits in the ACTLR register may not be
1066 available in non-secure mode.
1068 config ARM_ERRATA_458693
1069 bool "ARM errata: Processor deadlock when a false hazard is created"
1071 depends on !ARCH_MULTIPLATFORM
1073 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1074 erratum. For very specific sequences of memory operations, it is
1075 possible for a hazard condition intended for a cache line to instead
1076 be incorrectly associated with a different cache line. This false
1077 hazard might then cause a processor deadlock. The workaround enables
1078 the L1 caching of the NEON accesses and disables the PLD instruction
1079 in the ACTLR register. Note that setting specific bits in the ACTLR
1080 register may not be available in non-secure mode.
1082 config ARM_ERRATA_460075
1083 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1085 depends on !ARCH_MULTIPLATFORM
1087 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1088 erratum. Any asynchronous access to the L2 cache may encounter a
1089 situation in which recent store transactions to the L2 cache are lost
1090 and overwritten with stale memory contents from external memory. The
1091 workaround disables the write-allocate mode for the L2 cache via the
1092 ACTLR register. Note that setting specific bits in the ACTLR register
1093 may not be available in non-secure mode.
1095 config ARM_ERRATA_742230
1096 bool "ARM errata: DMB operation may be faulty"
1097 depends on CPU_V7 && SMP
1098 depends on !ARCH_MULTIPLATFORM
1100 This option enables the workaround for the 742230 Cortex-A9
1101 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1102 between two write operations may not ensure the correct visibility
1103 ordering of the two writes. This workaround sets a specific bit in
1104 the diagnostic register of the Cortex-A9 which causes the DMB
1105 instruction to behave as a DSB, ensuring the correct behaviour of
1108 config ARM_ERRATA_742231
1109 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1110 depends on CPU_V7 && SMP
1111 depends on !ARCH_MULTIPLATFORM
1113 This option enables the workaround for the 742231 Cortex-A9
1114 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1115 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1116 accessing some data located in the same cache line, may get corrupted
1117 data due to bad handling of the address hazard when the line gets
1118 replaced from one of the CPUs at the same time as another CPU is
1119 accessing it. This workaround sets specific bits in the diagnostic
1120 register of the Cortex-A9 which reduces the linefill issuing
1121 capabilities of the processor.
1123 config ARM_ERRATA_643719
1124 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1125 depends on CPU_V7 && SMP
1128 This option enables the workaround for the 643719 Cortex-A9 (prior to
1129 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1130 register returns zero when it should return one. The workaround
1131 corrects this value, ensuring cache maintenance operations which use
1132 it behave as intended and avoiding data corruption.
1134 config ARM_ERRATA_720789
1135 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1138 This option enables the workaround for the 720789 Cortex-A9 (prior to
1139 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1140 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1141 As a consequence of this erratum, some TLB entries which should be
1142 invalidated are not, resulting in an incoherency in the system page
1143 tables. The workaround changes the TLB flushing routines to invalidate
1144 entries regardless of the ASID.
1146 config ARM_ERRATA_743622
1147 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1149 depends on !ARCH_MULTIPLATFORM
1151 This option enables the workaround for the 743622 Cortex-A9
1152 (r2p*) erratum. Under very rare conditions, a faulty
1153 optimisation in the Cortex-A9 Store Buffer may lead to data
1154 corruption. This workaround sets a specific bit in the diagnostic
1155 register of the Cortex-A9 which disables the Store Buffer
1156 optimisation, preventing the defect from occurring. This has no
1157 visible impact on the overall performance or power consumption of the
1160 config ARM_ERRATA_751472
1161 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1163 depends on !ARCH_MULTIPLATFORM
1165 This option enables the workaround for the 751472 Cortex-A9 (prior
1166 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1167 completion of a following broadcasted operation if the second
1168 operation is received by a CPU before the ICIALLUIS has completed,
1169 potentially leading to corrupted entries in the cache or TLB.
1171 config ARM_ERRATA_754322
1172 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1175 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1176 r3p*) erratum. A speculative memory access may cause a page table walk
1177 which starts prior to an ASID switch but completes afterwards. This
1178 can populate the micro-TLB with a stale entry which may be hit with
1179 the new ASID. This workaround places two dsb instructions in the mm
1180 switching code so that no page table walks can cross the ASID switch.
1182 config ARM_ERRATA_754327
1183 bool "ARM errata: no automatic Store Buffer drain"
1184 depends on CPU_V7 && SMP
1186 This option enables the workaround for the 754327 Cortex-A9 (prior to
1187 r2p0) erratum. The Store Buffer does not have any automatic draining
1188 mechanism and therefore a livelock may occur if an external agent
1189 continuously polls a memory location waiting to observe an update.
1190 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1191 written polling loops from denying visibility of updates to memory.
1193 config ARM_ERRATA_364296
1194 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1197 This options enables the workaround for the 364296 ARM1136
1198 r0p2 erratum (possible cache data corruption with
1199 hit-under-miss enabled). It sets the undocumented bit 31 in
1200 the auxiliary control register and the FI bit in the control
1201 register, thus disabling hit-under-miss without putting the
1202 processor into full low interrupt latency mode. ARM11MPCore
1205 config ARM_ERRATA_764369
1206 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1207 depends on CPU_V7 && SMP
1209 This option enables the workaround for erratum 764369
1210 affecting Cortex-A9 MPCore with two or more processors (all
1211 current revisions). Under certain timing circumstances, a data
1212 cache line maintenance operation by MVA targeting an Inner
1213 Shareable memory region may fail to proceed up to either the
1214 Point of Coherency or to the Point of Unification of the
1215 system. This workaround adds a DSB instruction before the
1216 relevant cache maintenance functions and sets a specific bit
1217 in the diagnostic control register of the SCU.
1219 config ARM_ERRATA_775420
1220 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1223 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1224 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1225 operation aborts with MMU exception, it might cause the processor
1226 to deadlock. This workaround puts DSB before executing ISB if
1227 an abort may occur on cache maintenance.
1229 config ARM_ERRATA_798181
1230 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1231 depends on CPU_V7 && SMP
1233 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1234 adequately shooting down all use of the old entries. This
1235 option enables the Linux kernel workaround for this erratum
1236 which sends an IPI to the CPUs that are running the same ASID
1237 as the one being invalidated.
1239 config ARM_ERRATA_773022
1240 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1243 This option enables the workaround for the 773022 Cortex-A15
1244 (up to r0p4) erratum. In certain rare sequences of code, the
1245 loop buffer may deliver incorrect instructions. This
1246 workaround disables the loop buffer to avoid the erratum.
1250 source "arch/arm/common/Kconfig"
1257 Find out whether you have ISA slots on your motherboard. ISA is the
1258 name of a bus system, i.e. the way the CPU talks to the other stuff
1259 inside your box. Other bus systems are PCI, EISA, MicroChannel
1260 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1261 newer boards don't support it. If you have ISA, say Y, otherwise N.
1263 # Select ISA DMA controller support
1268 # Select ISA DMA interface
1273 bool "PCI support" if MIGHT_HAVE_PCI
1275 Find out whether you have a PCI motherboard. PCI is the name of a
1276 bus system, i.e. the way the CPU talks to the other stuff inside
1277 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1278 VESA. If you have PCI, say Y, otherwise N.
1284 config PCI_DOMAINS_GENERIC
1285 def_bool PCI_DOMAINS
1287 config PCI_NANOENGINE
1288 bool "BSE nanoEngine PCI support"
1289 depends on SA1100_NANOENGINE
1291 Enable PCI on the BSE nanoEngine board.
1296 config PCI_HOST_ITE8152
1298 depends on PCI && MACH_ARMCORE
1302 source "drivers/pci/Kconfig"
1303 source "drivers/pci/pcie/Kconfig"
1305 source "drivers/pcmcia/Kconfig"
1309 menu "Kernel Features"
1314 This option should be selected by machines which have an SMP-
1317 The only effect of this option is to make the SMP-related
1318 options available to the user for configuration.
1321 bool "Symmetric Multi-Processing"
1322 depends on CPU_V6K || CPU_V7
1323 depends on GENERIC_CLOCKEVENTS
1325 depends on MMU || ARM_MPU
1328 This enables support for systems with more than one CPU. If you have
1329 a system with only one CPU, say N. If you have a system with more
1330 than one CPU, say Y.
1332 If you say N here, the kernel will run on uni- and multiprocessor
1333 machines, but will use only one CPU of a multiprocessor machine. If
1334 you say Y here, the kernel will run on many, but not all,
1335 uniprocessor machines. On a uniprocessor machine, the kernel
1336 will run faster if you say N here.
1338 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1339 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1340 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1342 If you don't know what to do here, say N.
1345 bool "Allow booting SMP kernel on uniprocessor systems"
1346 depends on SMP && !XIP_KERNEL && MMU
1349 SMP kernels contain instructions which fail on non-SMP processors.
1350 Enabling this option allows the kernel to modify itself to make
1351 these instructions safe. Disabling it allows about 1K of space
1354 If you don't know what to do here, say Y.
1356 config ARM_CPU_TOPOLOGY
1357 bool "Support cpu topology definition"
1358 depends on SMP && CPU_V7
1361 Support ARM cpu topology definition. The MPIDR register defines
1362 affinity between processors which is then used to describe the cpu
1363 topology of an ARM System.
1366 bool "Multi-core scheduler support"
1367 depends on ARM_CPU_TOPOLOGY
1369 Multi-core scheduler support improves the CPU scheduler's decision
1370 making when dealing with multi-core CPU chips at a cost of slightly
1371 increased overhead in some places. If unsure say N here.
1374 bool "SMT scheduler support"
1375 depends on ARM_CPU_TOPOLOGY
1377 Improves the CPU scheduler's decision making when dealing with
1378 MultiThreading at a cost of slightly increased overhead in some
1379 places. If unsure say N here.
1384 This option enables support for the ARM system coherency unit
1386 config HAVE_ARM_ARCH_TIMER
1387 bool "Architected timer support"
1389 select ARM_ARCH_TIMER
1390 select GENERIC_CLOCKEVENTS
1392 This option enables support for the ARM architected timer
1396 select CLKSRC_OF if OF
1398 This options enables support for the ARM timer and watchdog unit
1401 bool "Multi-Cluster Power Management"
1402 depends on CPU_V7 && SMP
1404 This option provides the common power management infrastructure
1405 for (multi-)cluster based systems, such as big.LITTLE based
1408 config MCPM_QUAD_CLUSTER
1412 To avoid wasting resources unnecessarily, MCPM only supports up
1413 to 2 clusters by default.
1414 Platforms with 3 or 4 clusters that use MCPM must select this
1415 option to allow the additional clusters to be managed.
1418 bool "big.LITTLE support (Experimental)"
1419 depends on CPU_V7 && SMP
1422 This option enables support selections for the big.LITTLE
1423 system architecture.
1426 bool "big.LITTLE switcher support"
1427 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1430 The big.LITTLE "switcher" provides the core functionality to
1431 transparently handle transition between a cluster of A15's
1432 and a cluster of A7's in a big.LITTLE system.
1434 config BL_SWITCHER_DUMMY_IF
1435 tristate "Simple big.LITTLE switcher user interface"
1436 depends on BL_SWITCHER && DEBUG_KERNEL
1438 This is a simple and dummy char dev interface to control
1439 the big.LITTLE switcher core code. It is meant for
1440 debugging purposes only.
1443 prompt "Memory split"
1447 Select the desired split between kernel and user memory.
1449 If you are not absolutely sure what you are doing, leave this
1453 bool "3G/1G user/kernel split"
1454 config VMSPLIT_3G_OPT
1455 bool "3G/1G user/kernel split (for full 1G low memory)"
1457 bool "2G/2G user/kernel split"
1459 bool "1G/3G user/kernel split"
1464 default PHYS_OFFSET if !MMU
1465 default 0x40000000 if VMSPLIT_1G
1466 default 0x80000000 if VMSPLIT_2G
1467 default 0xB0000000 if VMSPLIT_3G_OPT
1471 int "Maximum number of CPUs (2-32)"
1477 bool "Support for hot-pluggable CPUs"
1480 Say Y here to experiment with turning CPUs off and on. CPUs
1481 can be controlled through /sys/devices/system/cpu.
1484 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1485 depends on HAVE_ARM_SMCCC
1488 Say Y here if you want Linux to communicate with system firmware
1489 implementing the PSCI specification for CPU-centric power
1490 management operations described in ARM document number ARM DEN
1491 0022A ("Power State Coordination Interface System Software on
1494 # The GPIO number here must be sorted by descending number. In case of
1495 # a multiplatform kernel, we just want the highest value required by the
1496 # selected platforms.
1499 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1501 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1502 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1503 default 416 if ARCH_SUNXI
1504 default 392 if ARCH_U8500
1505 default 352 if ARCH_VT8500
1506 default 288 if ARCH_ROCKCHIP
1507 default 264 if MACH_H4700
1510 Maximum number of GPIOs in the system.
1512 If unsure, leave the default value.
1514 source kernel/Kconfig.preempt
1518 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1519 ARCH_S5PV210 || ARCH_EXYNOS4
1520 default 128 if SOC_AT91RM9200
1524 depends on HZ_FIXED = 0
1525 prompt "Timer frequency"
1549 default HZ_FIXED if HZ_FIXED != 0
1550 default 100 if HZ_100
1551 default 200 if HZ_200
1552 default 250 if HZ_250
1553 default 300 if HZ_300
1554 default 500 if HZ_500
1558 def_bool HIGH_RES_TIMERS
1560 config THUMB2_KERNEL
1561 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1562 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1563 default y if CPU_THUMBONLY
1565 select ARM_ASM_UNIFIED
1568 By enabling this option, the kernel will be compiled in
1569 Thumb-2 mode. A compiler/assembler that understand the unified
1570 ARM-Thumb syntax is needed.
1574 config THUMB2_AVOID_R_ARM_THM_JUMP11
1575 bool "Work around buggy Thumb-2 short branch relocations in gas"
1576 depends on THUMB2_KERNEL && MODULES
1579 Various binutils versions can resolve Thumb-2 branches to
1580 locally-defined, preemptible global symbols as short-range "b.n"
1581 branch instructions.
1583 This is a problem, because there's no guarantee the final
1584 destination of the symbol, or any candidate locations for a
1585 trampoline, are within range of the branch. For this reason, the
1586 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1587 relocation in modules at all, and it makes little sense to add
1590 The symptom is that the kernel fails with an "unsupported
1591 relocation" error when loading some modules.
1593 Until fixed tools are available, passing
1594 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1595 code which hits this problem, at the cost of a bit of extra runtime
1596 stack usage in some cases.
1598 The problem is described in more detail at:
1599 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1601 Only Thumb-2 kernels are affected.
1603 Unless you are sure your tools don't have this problem, say Y.
1605 config ARM_ASM_UNIFIED
1609 bool "Use the ARM EABI to compile the kernel"
1611 This option allows for the kernel to be compiled using the latest
1612 ARM ABI (aka EABI). This is only useful if you are using a user
1613 space environment that is also compiled with EABI.
1615 Since there are major incompatibilities between the legacy ABI and
1616 EABI, especially with regard to structure member alignment, this
1617 option also changes the kernel syscall calling convention to
1618 disambiguate both ABIs and allow for backward compatibility support
1619 (selected with CONFIG_OABI_COMPAT).
1621 To use this you need GCC version 4.0.0 or later.
1624 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1625 depends on AEABI && !THUMB2_KERNEL
1627 This option preserves the old syscall interface along with the
1628 new (ARM EABI) one. It also provides a compatibility layer to
1629 intercept syscalls that have structure arguments which layout
1630 in memory differs between the legacy ABI and the new ARM EABI
1631 (only for non "thumb" binaries). This option adds a tiny
1632 overhead to all syscalls and produces a slightly larger kernel.
1634 The seccomp filter system will not be available when this is
1635 selected, since there is no way yet to sensibly distinguish
1636 between calling conventions during filtering.
1638 If you know you'll be using only pure EABI user space then you
1639 can say N here. If this option is not selected and you attempt
1640 to execute a legacy ABI binary then the result will be
1641 UNPREDICTABLE (in fact it can be predicted that it won't work
1642 at all). If in doubt say N.
1644 config ARCH_HAS_HOLES_MEMORYMODEL
1647 config ARCH_SPARSEMEM_ENABLE
1650 config ARCH_SPARSEMEM_DEFAULT
1651 def_bool ARCH_SPARSEMEM_ENABLE
1653 config ARCH_SELECT_MEMORY_MODEL
1654 def_bool ARCH_SPARSEMEM_ENABLE
1656 config HAVE_ARCH_PFN_VALID
1657 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1659 config HAVE_GENERIC_RCU_GUP
1664 bool "High Memory Support"
1667 The address space of ARM processors is only 4 Gigabytes large
1668 and it has to accommodate user address space, kernel address
1669 space as well as some memory mapped IO. That means that, if you
1670 have a large amount of physical memory and/or IO, not all of the
1671 memory can be "permanently mapped" by the kernel. The physical
1672 memory that is not permanently mapped is called "high memory".
1674 Depending on the selected kernel/user memory split, minimum
1675 vmalloc space and actual amount of RAM, you may not need this
1676 option which should result in a slightly faster kernel.
1681 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1685 The VM uses one page of physical memory for each page table.
1686 For systems with a lot of processes, this can use a lot of
1687 precious low memory, eventually leading to low memory being
1688 consumed by page tables. Setting this option will allow
1689 user-space 2nd level page tables to reside in high memory.
1691 config CPU_SW_DOMAIN_PAN
1692 bool "Enable use of CPU domains to implement privileged no-access"
1693 depends on MMU && !ARM_LPAE
1696 Increase kernel security by ensuring that normal kernel accesses
1697 are unable to access userspace addresses. This can help prevent
1698 use-after-free bugs becoming an exploitable privilege escalation
1699 by ensuring that magic values (such as LIST_POISON) will always
1700 fault when dereferenced.
1702 CPUs with low-vector mappings use a best-efforts implementation.
1703 Their lower 1MB needs to remain accessible for the vectors, but
1704 the remainder of userspace will become appropriately inaccessible.
1706 config HW_PERF_EVENTS
1710 config SYS_SUPPORTS_HUGETLBFS
1714 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1718 config ARCH_WANT_GENERAL_HUGETLB
1721 config ARM_MODULE_PLTS
1722 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1725 Allocate PLTs when loading modules so that jumps and calls whose
1726 targets are too far away for their relative offsets to be encoded
1727 in the instructions themselves can be bounced via veneers in the
1728 module's PLT. This allows modules to be allocated in the generic
1729 vmalloc area after the dedicated module memory area has been
1730 exhausted. The modules will use slightly more memory, but after
1731 rounding up to page size, the actual memory footprint is usually
1734 Say y if you are getting out of memory errors while loading modules
1738 config FORCE_MAX_ZONEORDER
1739 int "Maximum zone order"
1740 default "12" if SOC_AM33XX
1741 default "9" if SA1111 || ARCH_EFM32
1744 The kernel memory allocator divides physically contiguous memory
1745 blocks into "zones", where each zone is a power of two number of
1746 pages. This option selects the largest power of two that the kernel
1747 keeps in the memory allocator. If you need to allocate very large
1748 blocks of physically contiguous memory, then you may need to
1749 increase this value.
1751 This config option is actually maximum order plus one. For example,
1752 a value of 11 means that the largest free memory block is 2^10 pages.
1754 config ALIGNMENT_TRAP
1756 depends on CPU_CP15_MMU
1757 default y if !ARCH_EBSA110
1758 select HAVE_PROC_CPU if PROC_FS
1760 ARM processors cannot fetch/store information which is not
1761 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1762 address divisible by 4. On 32-bit ARM processors, these non-aligned
1763 fetch/store instructions will be emulated in software if you say
1764 here, which has a severe performance impact. This is necessary for
1765 correct operation of some network protocols. With an IP-only
1766 configuration it is safe to say N, otherwise say Y.
1768 config UACCESS_WITH_MEMCPY
1769 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1771 default y if CPU_FEROCEON
1773 Implement faster copy_to_user and clear_user methods for CPU
1774 cores where a 8-word STM instruction give significantly higher
1775 memory write throughput than a sequence of individual 32bit stores.
1777 A possible side effect is a slight increase in scheduling latency
1778 between threads sharing the same address space if they invoke
1779 such copy operations with large buffers.
1781 However, if the CPU data cache is using a write-allocate mode,
1782 this option is unlikely to provide any performance gain.
1786 prompt "Enable seccomp to safely compute untrusted bytecode"
1788 This kernel feature is useful for number crunching applications
1789 that may need to compute untrusted bytecode during their
1790 execution. By using pipes or other transports made available to
1791 the process as file descriptors supporting the read/write
1792 syscalls, it's possible to isolate those applications in
1793 their own address space using seccomp. Once seccomp is
1794 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1795 and the task is only allowed to execute a few safe syscalls
1796 defined by each seccomp mode.
1809 bool "Xen guest support on ARM"
1810 depends on ARM && AEABI && OF
1811 depends on CPU_V7 && !CPU_V6
1812 depends on !GENERIC_ATOMIC64
1814 select ARCH_DMA_ADDR_T_64BIT
1818 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1825 bool "Flattened Device Tree support"
1829 Include support for flattened device tree machine descriptions.
1832 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1835 This is the traditional way of passing data to the kernel at boot
1836 time. If you are solely relying on the flattened device tree (or
1837 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1838 to remove ATAGS support from your kernel binary. If unsure,
1841 config DEPRECATED_PARAM_STRUCT
1842 bool "Provide old way to pass kernel parameters"
1845 This was deprecated in 2001 and announced to live on for 5 years.
1846 Some old boot loaders still use this way.
1848 # Compressed boot loader in ROM. Yes, we really want to ask about
1849 # TEXT and BSS so we preserve their values in the config files.
1850 config ZBOOT_ROM_TEXT
1851 hex "Compressed ROM boot loader base address"
1854 The physical address at which the ROM-able zImage is to be
1855 placed in the target. Platforms which normally make use of
1856 ROM-able zImage formats normally set this to a suitable
1857 value in their defconfig file.
1859 If ZBOOT_ROM is not enabled, this has no effect.
1861 config ZBOOT_ROM_BSS
1862 hex "Compressed ROM boot loader BSS address"
1865 The base address of an area of read/write memory in the target
1866 for the ROM-able zImage which must be available while the
1867 decompressor is running. It must be large enough to hold the
1868 entire decompressed kernel plus an additional 128 KiB.
1869 Platforms which normally make use of ROM-able zImage formats
1870 normally set this to a suitable value in their defconfig file.
1872 If ZBOOT_ROM is not enabled, this has no effect.
1875 bool "Compressed boot loader in ROM/flash"
1876 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1877 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1879 Say Y here if you intend to execute your compressed kernel image
1880 (zImage) directly from ROM or flash. If unsure, say N.
1882 config ARM_APPENDED_DTB
1883 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1886 With this option, the boot code will look for a device tree binary
1887 (DTB) appended to zImage
1888 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1890 This is meant as a backward compatibility convenience for those
1891 systems with a bootloader that can't be upgraded to accommodate
1892 the documented boot protocol using a device tree.
1894 Beware that there is very little in terms of protection against
1895 this option being confused by leftover garbage in memory that might
1896 look like a DTB header after a reboot if no actual DTB is appended
1897 to zImage. Do not leave this option active in a production kernel
1898 if you don't intend to always append a DTB. Proper passing of the
1899 location into r2 of a bootloader provided DTB is always preferable
1902 config ARM_ATAG_DTB_COMPAT
1903 bool "Supplement the appended DTB with traditional ATAG information"
1904 depends on ARM_APPENDED_DTB
1906 Some old bootloaders can't be updated to a DTB capable one, yet
1907 they provide ATAGs with memory configuration, the ramdisk address,
1908 the kernel cmdline string, etc. Such information is dynamically
1909 provided by the bootloader and can't always be stored in a static
1910 DTB. To allow a device tree enabled kernel to be used with such
1911 bootloaders, this option allows zImage to extract the information
1912 from the ATAG list and store it at run time into the appended DTB.
1915 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1916 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1918 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1919 bool "Use bootloader kernel arguments if available"
1921 Uses the command-line options passed by the boot loader instead of
1922 the device tree bootargs property. If the boot loader doesn't provide
1923 any, the device tree bootargs property will be used.
1925 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1926 bool "Extend with bootloader kernel arguments"
1928 The command-line arguments provided by the boot loader will be
1929 appended to the the device tree bootargs property.
1934 string "Default kernel command string"
1937 On some architectures (EBSA110 and CATS), there is currently no way
1938 for the boot loader to pass arguments to the kernel. For these
1939 architectures, you should supply some command-line options at build
1940 time by entering them here. As a minimum, you should specify the
1941 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1944 prompt "Kernel command line type" if CMDLINE != ""
1945 default CMDLINE_FROM_BOOTLOADER
1948 config CMDLINE_FROM_BOOTLOADER
1949 bool "Use bootloader kernel arguments if available"
1951 Uses the command-line options passed by the boot loader. If
1952 the boot loader doesn't provide any, the default kernel command
1953 string provided in CMDLINE will be used.
1955 config CMDLINE_EXTEND
1956 bool "Extend bootloader kernel arguments"
1958 The command-line arguments provided by the boot loader will be
1959 appended to the default kernel command string.
1961 config CMDLINE_FORCE
1962 bool "Always use the default kernel command string"
1964 Always use the default kernel command string, even if the boot
1965 loader passes other arguments to the kernel.
1966 This is useful if you cannot or don't want to change the
1967 command-line options your boot loader passes to the kernel.
1971 bool "Kernel Execute-In-Place from ROM"
1972 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1974 Execute-In-Place allows the kernel to run from non-volatile storage
1975 directly addressable by the CPU, such as NOR flash. This saves RAM
1976 space since the text section of the kernel is not loaded from flash
1977 to RAM. Read-write sections, such as the data section and stack,
1978 are still copied to RAM. The XIP kernel is not compressed since
1979 it has to run directly from flash, so it will take more space to
1980 store it. The flash address used to link the kernel object files,
1981 and for storing it, is configuration dependent. Therefore, if you
1982 say Y here, you must know the proper physical address where to
1983 store the kernel image depending on your own flash memory usage.
1985 Also note that the make target becomes "make xipImage" rather than
1986 "make zImage" or "make Image". The final kernel binary to put in
1987 ROM memory will be arch/arm/boot/xipImage.
1991 config XIP_PHYS_ADDR
1992 hex "XIP Kernel Physical Location"
1993 depends on XIP_KERNEL
1994 default "0x00080000"
1996 This is the physical address in your flash memory the kernel will
1997 be linked for and stored to. This address is dependent on your
2001 bool "Kexec system call (EXPERIMENTAL)"
2002 depends on (!SMP || PM_SLEEP_SMP)
2006 kexec is a system call that implements the ability to shutdown your
2007 current kernel, and to start another kernel. It is like a reboot
2008 but it is independent of the system firmware. And like a reboot
2009 you can start any kernel with it, not just Linux.
2011 It is an ongoing process to be certain the hardware in a machine
2012 is properly shutdown, so do not be surprised if this code does not
2013 initially work for you.
2016 bool "Export atags in procfs"
2017 depends on ATAGS && KEXEC
2020 Should the atags used to boot the kernel be exported in an "atags"
2021 file in procfs. Useful with kexec.
2024 bool "Build kdump crash kernel (EXPERIMENTAL)"
2026 Generate crash dump after being started by kexec. This should
2027 be normally only set in special crash dump kernels which are
2028 loaded in the main kernel with kexec-tools into a specially
2029 reserved region and then later executed after a crash by
2030 kdump/kexec. The crash dump kernel must be compiled to a
2031 memory address not used by the main kernel
2033 For more details see Documentation/kdump/kdump.txt
2035 config AUTO_ZRELADDR
2036 bool "Auto calculation of the decompressed kernel image address"
2038 ZRELADDR is the physical address where the decompressed kernel
2039 image will be placed. If AUTO_ZRELADDR is selected, the address
2040 will be determined at run-time by masking the current IP with
2041 0xf8000000. This assumes the zImage being placed in the first 128MB
2042 from start of memory.
2046 menu "CPU Power Management"
2048 source "drivers/cpufreq/Kconfig"
2050 source "drivers/cpuidle/Kconfig"
2054 menu "Floating point emulation"
2056 comment "At least one emulation must be selected"
2059 bool "NWFPE math emulation"
2060 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2062 Say Y to include the NWFPE floating point emulator in the kernel.
2063 This is necessary to run most binaries. Linux does not currently
2064 support floating point hardware so you need to say Y here even if
2065 your machine has an FPA or floating point co-processor podule.
2067 You may say N here if you are going to load the Acorn FPEmulator
2068 early in the bootup.
2071 bool "Support extended precision"
2072 depends on FPE_NWFPE
2074 Say Y to include 80-bit support in the kernel floating-point
2075 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2076 Note that gcc does not generate 80-bit operations by default,
2077 so in most cases this option only enlarges the size of the
2078 floating point emulator without any good reason.
2080 You almost surely want to say N here.
2083 bool "FastFPE math emulation (EXPERIMENTAL)"
2084 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2086 Say Y here to include the FAST floating point emulator in the kernel.
2087 This is an experimental much faster emulator which now also has full
2088 precision for the mantissa. It does not support any exceptions.
2089 It is very simple, and approximately 3-6 times faster than NWFPE.
2091 It should be sufficient for most programs. It may be not suitable
2092 for scientific calculations, but you have to check this for yourself.
2093 If you do not feel you need a faster FP emulation you should better
2097 bool "VFP-format floating point maths"
2098 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2100 Say Y to include VFP support code in the kernel. This is needed
2101 if your hardware includes a VFP unit.
2103 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2104 release notes and additional status information.
2106 Say N if your target does not have VFP hardware.
2114 bool "Advanced SIMD (NEON) Extension support"
2115 depends on VFPv3 && CPU_V7
2117 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2120 config KERNEL_MODE_NEON
2121 bool "Support for NEON in kernel mode"
2122 depends on NEON && AEABI
2124 Say Y to include support for NEON in kernel mode.
2128 menu "Userspace binary formats"
2130 source "fs/Kconfig.binfmt"
2134 menu "Power management options"
2136 source "kernel/power/Kconfig"
2138 config ARCH_SUSPEND_POSSIBLE
2139 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2140 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2143 config ARM_CPU_SUSPEND
2144 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2145 depends on ARCH_SUSPEND_POSSIBLE
2147 config ARCH_HIBERNATION_POSSIBLE
2150 default y if ARCH_SUSPEND_POSSIBLE
2154 source "net/Kconfig"
2156 source "drivers/Kconfig"
2158 source "drivers/firmware/Kconfig"
2162 source "arch/arm/Kconfig.debug"
2164 source "security/Kconfig"
2166 source "crypto/Kconfig"
2168 source "arch/arm/crypto/Kconfig"
2171 source "lib/Kconfig"
2173 source "arch/arm/kvm/Kconfig"