4 select ARCH_HAVE_CUSTOM_GPIO_H
6 select HAVE_DMA_API_DEBUG
7 select HAVE_IDE if PCI || ISA || PCMCIA
9 select HAVE_DMA_CONTIGUOUS if (CPU_V6 || CPU_V6K || CPU_V7)
12 select SYS_SUPPORTS_APM_EMULATION
13 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
14 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
15 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
17 select HAVE_ARCH_TRACEHOOK
18 select HAVE_KPROBES if !XIP_KERNEL
19 select HAVE_KRETPROBES if (HAVE_KPROBES)
20 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
21 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
22 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
23 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
24 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
25 select HAVE_GENERIC_DMA_COHERENT
26 select HAVE_KERNEL_GZIP
27 select HAVE_KERNEL_LZO
28 select HAVE_KERNEL_LZMA
31 select HAVE_PERF_EVENTS
32 select PERF_USE_VMALLOC
33 select HAVE_REGS_AND_STACK_ACCESS_API
34 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
35 select HAVE_C_RECORDMCOUNT
36 select HAVE_GENERIC_HARDIRQS
37 select HARDIRQS_SW_RESEND
38 select GENERIC_IRQ_PROBE
39 select GENERIC_IRQ_SHOW
40 select GENERIC_IRQ_PROBE
41 select HARDIRQS_SW_RESEND
42 select CPU_PM if (SUSPEND || CPU_IDLE)
43 select GENERIC_PCI_IOMAP
45 select GENERIC_SMP_IDLE_THREAD
47 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
49 The ARM series is a line of low-power-consumption RISC chip designs
50 licensed by ARM Ltd and targeted at embedded applications and
51 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
52 manufactured, but legacy ARM-based PC hardware remains popular in
53 Europe. There is an ARM Linux project with a web page at
54 <http://www.arm.linux.org.uk/>.
56 config ARM_HAS_SG_CHAIN
59 config NEED_SG_DMA_LENGTH
62 config ARM_DMA_USE_IOMMU
63 select NEED_SG_DMA_LENGTH
64 select ARM_HAS_SG_CHAIN
73 config SYS_SUPPORTS_APM_EMULATION
81 select GENERIC_ALLOCATOR
92 The Extended Industry Standard Architecture (EISA) bus was
93 developed as an open alternative to the IBM MicroChannel bus.
95 The EISA bus provided some of the features of the IBM MicroChannel
96 bus while maintaining backward compatibility with cards made for
97 the older ISA bus. The EISA bus saw limited use between 1988 and
98 1995 when it was made obsolete by the PCI bus.
100 Say Y here if you are building a kernel for an EISA-based machine.
107 config STACKTRACE_SUPPORT
111 config HAVE_LATENCYTOP_SUPPORT
116 config LOCKDEP_SUPPORT
120 config TRACE_IRQFLAGS_SUPPORT
124 config GENERIC_LOCKBREAK
127 depends on SMP && PREEMPT
129 config RWSEM_GENERIC_SPINLOCK
133 config RWSEM_XCHGADD_ALGORITHM
136 config ARCH_HAS_ILOG2_U32
139 config ARCH_HAS_ILOG2_U64
142 config ARCH_HAS_CPUFREQ
145 Internal node to signify that the ARCH has CPUFREQ support
146 and that the relevant menu configurations are displayed for
149 config GENERIC_HWEIGHT
153 config GENERIC_CALIBRATE_DELAY
157 config ARCH_MAY_HAVE_PC_FDC
163 config NEED_DMA_MAP_STATE
166 config ARCH_HAS_DMA_SET_COHERENT_MASK
169 config GENERIC_ISA_DMA
175 config NEED_RET_TO_USER
183 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
184 default DRAM_BASE if REMAP_VECTORS_TO_RAM
187 The base address of exception vectors.
189 config ARM_PATCH_PHYS_VIRT
190 bool "Patch physical to virtual translations at runtime" if EMBEDDED
192 depends on !XIP_KERNEL && MMU
193 depends on !ARCH_REALVIEW || !SPARSEMEM
195 Patch phys-to-virt and virt-to-phys translation functions at
196 boot and module load time according to the position of the
197 kernel in system memory.
199 This can only be used with non-XIP MMU kernels where the base
200 of physical memory is at a 16MB boundary.
202 Only disable this option if you know that you do not require
203 this feature (eg, building a kernel for a single machine) and
204 you need to shrink the kernel to the minimal size.
206 config NEED_MACH_IO_H
209 Select this when mach/io.h is required to provide special
210 definitions for this platform. The need for mach/io.h should
211 be avoided when possible.
213 config NEED_MACH_MEMORY_H
216 Select this when mach/memory.h is required to provide special
217 definitions for this platform. The need for mach/memory.h should
218 be avoided when possible.
221 hex "Physical address of main memory" if MMU
222 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
223 default DRAM_BASE if !MMU
225 Please provide the physical address corresponding to the
226 location of main memory in your system.
232 source "init/Kconfig"
234 source "kernel/Kconfig.freezer"
239 bool "MMU-based Paged Memory Management Support"
242 Select if you want MMU-based virtualised addressing space
243 support by paged memory management. If unsure, say 'Y'.
246 # The "ARM system type" choice list is ordered alphabetically by option
247 # text. Please add new entries in the option alphabetic order.
250 prompt "ARM system type"
251 default ARCH_VERSATILE
254 bool "Altera SOCFPGA family"
255 select ARCH_WANT_OPTIONAL_GPIOLIB
263 select DW_APB_TIMER_OF
264 select GENERIC_CLOCKEVENTS
265 select GPIO_PL061 if GPIOLIB
270 This enables support for Altera SOCFPGA Cyclone V platform
272 config ARCH_INTEGRATOR
273 bool "ARM Ltd. Integrator family"
275 select ARCH_HAS_CPUFREQ
277 select HAVE_MACH_CLKDEV
280 select GENERIC_CLOCKEVENTS
281 select PLAT_VERSATILE
282 select PLAT_VERSATILE_CLOCK
283 select PLAT_VERSATILE_FPGA_IRQ
284 select NEED_MACH_IO_H
285 select NEED_MACH_MEMORY_H
287 select MULTI_IRQ_HANDLER
289 Support for ARM's Integrator platform.
292 bool "ARM Ltd. RealView family"
295 select HAVE_MACH_CLKDEV
297 select GENERIC_CLOCKEVENTS
298 select ARCH_WANT_OPTIONAL_GPIOLIB
299 select PLAT_VERSATILE
300 select PLAT_VERSATILE_CLOCK
301 select PLAT_VERSATILE_CLCD
302 select ARM_TIMER_SP804
303 select GPIO_PL061 if GPIOLIB
304 select NEED_MACH_MEMORY_H
306 This enables support for ARM Ltd RealView boards.
308 config ARCH_VERSATILE
309 bool "ARM Ltd. Versatile family"
313 select HAVE_MACH_CLKDEV
315 select GENERIC_CLOCKEVENTS
316 select ARCH_WANT_OPTIONAL_GPIOLIB
317 select NEED_MACH_IO_H if PCI
318 select PLAT_VERSATILE
319 select PLAT_VERSATILE_CLOCK
320 select PLAT_VERSATILE_CLCD
321 select PLAT_VERSATILE_FPGA_IRQ
322 select ARM_TIMER_SP804
324 This enables support for ARM Ltd Versatile board.
327 bool "ARM Ltd. Versatile Express family"
328 select ARCH_WANT_OPTIONAL_GPIOLIB
330 select ARM_TIMER_SP804
333 select GENERIC_CLOCKEVENTS
335 select HAVE_PATA_PLATFORM
338 select PLAT_VERSATILE
339 select PLAT_VERSATILE_CLCD
340 select REGULATOR_FIXED_VOLTAGE if REGULATOR
342 This enables support for the ARM Ltd Versatile Express boards.
346 select ARCH_REQUIRE_GPIOLIB
350 select NEED_MACH_IO_H if PCCARD
352 This enables support for systems based on Atmel
353 AT91RM9200 and AT91SAM9* processors.
356 bool "Broadcom BCMRING"
360 select ARM_TIMER_SP804
362 select GENERIC_CLOCKEVENTS
363 select ARCH_WANT_OPTIONAL_GPIOLIB
365 Support for Broadcom's BCMRing platform.
368 bool "Calxeda Highbank-based"
369 select ARCH_WANT_OPTIONAL_GPIOLIB
372 select ARM_TIMER_SP804
376 select GENERIC_CLOCKEVENTS
382 Support for the Calxeda Highbank SoC based boards.
385 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
387 select ARCH_USES_GETTIMEOFFSET
388 select NEED_MACH_MEMORY_H
390 Support for Cirrus Logic 711x/721x/731x based boards.
393 bool "Cavium Networks CNS3XXX family"
395 select GENERIC_CLOCKEVENTS
397 select MIGHT_HAVE_CACHE_L2X0
398 select MIGHT_HAVE_PCI
399 select PCI_DOMAINS if PCI
401 Support for Cavium Networks CNS3XXX platform.
404 bool "Cortina Systems Gemini"
406 select ARCH_REQUIRE_GPIOLIB
407 select ARCH_USES_GETTIMEOFFSET
409 Support for the Cortina Systems Gemini family SoCs
412 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
415 select GENERIC_CLOCKEVENTS
417 select GENERIC_IRQ_CHIP
418 select MIGHT_HAVE_CACHE_L2X0
424 Support for CSR SiRFSoC ARM Cortex A9 Platform
431 select ARCH_USES_GETTIMEOFFSET
432 select NEED_MACH_IO_H
433 select NEED_MACH_MEMORY_H
435 This is an evaluation board for the StrongARM processor available
436 from Digital. It has limited hardware on-board, including an
437 Ethernet interface, two PCMCIA sockets, two serial ports and a
446 select ARCH_REQUIRE_GPIOLIB
447 select ARCH_HAS_HOLES_MEMORYMODEL
448 select ARCH_USES_GETTIMEOFFSET
449 select NEED_MACH_MEMORY_H
451 This enables support for the Cirrus EP93xx series of CPUs.
453 config ARCH_FOOTBRIDGE
457 select GENERIC_CLOCKEVENTS
459 select NEED_MACH_IO_H
460 select NEED_MACH_MEMORY_H
462 Support for systems based on the DC21285 companion chip
463 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
466 bool "Freescale MXC/iMX-based"
467 select GENERIC_CLOCKEVENTS
468 select ARCH_REQUIRE_GPIOLIB
471 select GENERIC_IRQ_CHIP
472 select MULTI_IRQ_HANDLER
474 Support for Freescale MXC/iMX-based family of processors
477 bool "Freescale MXS-based"
478 select GENERIC_CLOCKEVENTS
479 select ARCH_REQUIRE_GPIOLIB
483 select HAVE_CLK_PREPARE
487 Support for Freescale MXS-based family of processors
490 bool "Hilscher NetX based"
494 select GENERIC_CLOCKEVENTS
496 This enables support for systems based on the Hilscher NetX Soc
499 bool "Hynix HMS720x-based"
502 select ARCH_USES_GETTIMEOFFSET
504 This enables support for systems based on the Hynix HMS720x
512 select ARCH_SUPPORTS_MSI
514 select NEED_MACH_IO_H
515 select NEED_MACH_MEMORY_H
516 select NEED_RET_TO_USER
518 Support for Intel's IOP13XX (XScale) family of processors.
524 select NEED_MACH_IO_H
525 select NEED_RET_TO_USER
528 select ARCH_REQUIRE_GPIOLIB
530 Support for Intel's 80219 and IOP32X (XScale) family of
537 select NEED_MACH_IO_H
538 select NEED_RET_TO_USER
541 select ARCH_REQUIRE_GPIOLIB
543 Support for Intel's IOP33X (XScale) family of processors.
548 select ARCH_HAS_DMA_SET_COHERENT_MASK
551 select ARCH_REQUIRE_GPIOLIB
552 select GENERIC_CLOCKEVENTS
553 select MIGHT_HAVE_PCI
554 select NEED_MACH_IO_H
555 select DMABOUNCE if PCI
557 Support for Intel's IXP4XX (XScale) family of processors.
560 bool "Marvell SOCs with Device Tree support"
561 select GENERIC_CLOCKEVENTS
562 select MULTI_IRQ_HANDLER
565 select GENERIC_IRQ_CHIP
569 Support for the Marvell SoC Family with device tree support
575 select ARCH_REQUIRE_GPIOLIB
576 select GENERIC_CLOCKEVENTS
577 select NEED_MACH_IO_H
580 Support for the Marvell Dove SoC 88AP510
583 bool "Marvell Kirkwood"
586 select ARCH_REQUIRE_GPIOLIB
587 select GENERIC_CLOCKEVENTS
588 select NEED_MACH_IO_H
591 Support for the following Marvell Kirkwood series SoCs:
592 88F6180, 88F6192 and 88F6281.
598 select ARCH_REQUIRE_GPIOLIB
601 select USB_ARCH_HAS_OHCI
603 select GENERIC_CLOCKEVENTS
607 Support for the NXP LPC32XX family of processors
610 bool "Marvell MV78xx0"
613 select ARCH_REQUIRE_GPIOLIB
614 select GENERIC_CLOCKEVENTS
615 select NEED_MACH_IO_H
618 Support for the following Marvell MV78xx0 series SoCs:
626 select ARCH_REQUIRE_GPIOLIB
627 select GENERIC_CLOCKEVENTS
628 select NEED_MACH_IO_H
631 Support for the following Marvell Orion 5x series SoCs:
632 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
633 Orion-2 (5281), Orion-1-90 (6183).
636 bool "Marvell PXA168/910/MMP2"
638 select ARCH_REQUIRE_GPIOLIB
640 select GENERIC_CLOCKEVENTS
645 select GENERIC_ALLOCATOR
647 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
650 bool "Micrel/Kendin KS8695"
652 select ARCH_REQUIRE_GPIOLIB
653 select ARCH_USES_GETTIMEOFFSET
654 select NEED_MACH_MEMORY_H
656 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
657 System-on-Chip devices.
660 bool "Nuvoton W90X900 CPU"
662 select ARCH_REQUIRE_GPIOLIB
665 select GENERIC_CLOCKEVENTS
667 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
668 At present, the w90x900 has been renamed nuc900, regarding
669 the ARM series product line, you can login the following
670 link address to know more.
672 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
673 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
679 select GENERIC_CLOCKEVENTS
683 select MIGHT_HAVE_CACHE_L2X0
684 select NEED_MACH_IO_H if PCI
685 select ARCH_HAS_CPUFREQ
688 This enables support for NVIDIA Tegra based systems (Tegra APX,
689 Tegra 6xx and Tegra 2 series).
691 config ARCH_PICOXCELL
692 bool "Picochip picoXcell"
693 select ARCH_REQUIRE_GPIOLIB
694 select ARM_PATCH_PHYS_VIRT
698 select DW_APB_TIMER_OF
699 select GENERIC_CLOCKEVENTS
706 This enables support for systems based on the Picochip picoXcell
707 family of Femtocell devices. The picoxcell support requires device tree
711 bool "Philips Nexperia PNX4008 Mobile"
714 select ARCH_USES_GETTIMEOFFSET
716 This enables support for Philips PNX4008 mobile platform.
719 bool "PXA2xx/PXA3xx-based"
722 select ARCH_HAS_CPUFREQ
725 select ARCH_REQUIRE_GPIOLIB
726 select GENERIC_CLOCKEVENTS
731 select MULTI_IRQ_HANDLER
732 select ARM_CPU_SUSPEND if PM
735 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
740 select GENERIC_CLOCKEVENTS
741 select ARCH_REQUIRE_GPIOLIB
744 Support for Qualcomm MSM/QSD based systems. This runs on the
745 apps processor of the MSM/QSD and depends on a shared memory
746 interface to the modem processor which runs the baseband
747 stack and controls some vital subsystems
748 (clock and power control, etc).
751 bool "Renesas SH-Mobile / R-Mobile"
754 select HAVE_MACH_CLKDEV
756 select GENERIC_CLOCKEVENTS
757 select MIGHT_HAVE_CACHE_L2X0
760 select MULTI_IRQ_HANDLER
761 select PM_GENERIC_DOMAINS if PM
762 select NEED_MACH_MEMORY_H
764 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
770 select ARCH_MAY_HAVE_PC_FDC
771 select HAVE_PATA_PLATFORM
774 select ARCH_SPARSEMEM_ENABLE
775 select ARCH_USES_GETTIMEOFFSET
777 select NEED_MACH_IO_H
778 select NEED_MACH_MEMORY_H
780 On the Acorn Risc-PC, Linux can support the internal IDE disk and
781 CD-ROM interface, serial and parallel port, and the floppy drive.
788 select ARCH_SPARSEMEM_ENABLE
790 select ARCH_HAS_CPUFREQ
792 select GENERIC_CLOCKEVENTS
794 select ARCH_REQUIRE_GPIOLIB
796 select NEED_MACH_MEMORY_H
799 Support for StrongARM 11x0 based boards.
802 bool "Samsung S3C24XX SoCs"
804 select ARCH_HAS_CPUFREQ
807 select ARCH_USES_GETTIMEOFFSET
808 select HAVE_S3C2410_I2C if I2C
809 select HAVE_S3C_RTC if RTC_CLASS
810 select HAVE_S3C2410_WATCHDOG if WATCHDOG
811 select NEED_MACH_IO_H
813 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
814 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
815 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
816 Samsung SMDK2410 development board (and derivatives).
819 bool "Samsung S3C64XX"
827 select ARCH_USES_GETTIMEOFFSET
828 select ARCH_HAS_CPUFREQ
829 select ARCH_REQUIRE_GPIOLIB
830 select SAMSUNG_CLKSRC
831 select SAMSUNG_IRQ_VIC_TIMER
832 select S3C_GPIO_TRACK
834 select USB_ARCH_HAS_OHCI
835 select SAMSUNG_GPIOLIB_4BIT
836 select HAVE_S3C2410_I2C if I2C
837 select HAVE_S3C2410_WATCHDOG if WATCHDOG
839 Samsung S3C64XX series based systems
842 bool "Samsung S5P6440 S5P6450"
848 select HAVE_S3C2410_WATCHDOG if WATCHDOG
849 select GENERIC_CLOCKEVENTS
850 select HAVE_S3C2410_I2C if I2C
851 select HAVE_S3C_RTC if RTC_CLASS
853 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
857 bool "Samsung S5PC100"
862 select ARCH_USES_GETTIMEOFFSET
863 select HAVE_S3C2410_I2C if I2C
864 select HAVE_S3C_RTC if RTC_CLASS
865 select HAVE_S3C2410_WATCHDOG if WATCHDOG
867 Samsung S5PC100 series based systems
870 bool "Samsung S5PV210/S5PC110"
872 select ARCH_SPARSEMEM_ENABLE
873 select ARCH_HAS_HOLES_MEMORYMODEL
878 select ARCH_HAS_CPUFREQ
879 select GENERIC_CLOCKEVENTS
880 select HAVE_S3C2410_I2C if I2C
881 select HAVE_S3C_RTC if RTC_CLASS
882 select HAVE_S3C2410_WATCHDOG if WATCHDOG
883 select NEED_MACH_MEMORY_H
885 Samsung S5PV210/S5PC110 series based systems
888 bool "SAMSUNG EXYNOS"
890 select ARCH_SPARSEMEM_ENABLE
891 select ARCH_HAS_HOLES_MEMORYMODEL
895 select ARCH_HAS_CPUFREQ
896 select GENERIC_CLOCKEVENTS
897 select HAVE_S3C_RTC if RTC_CLASS
898 select HAVE_S3C2410_I2C if I2C
899 select HAVE_S3C2410_WATCHDOG if WATCHDOG
900 select NEED_MACH_MEMORY_H
902 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
911 select ARCH_USES_GETTIMEOFFSET
912 select NEED_MACH_MEMORY_H
913 select NEED_MACH_IO_H
915 Support for the StrongARM based Digital DNARD machine, also known
916 as "Shark" (<http://www.shark-linux.de/shark.html>).
919 bool "ST-Ericsson U300 Series"
925 select ARM_PATCH_PHYS_VIRT
927 select GENERIC_CLOCKEVENTS
929 select HAVE_MACH_CLKDEV
931 select ARCH_REQUIRE_GPIOLIB
933 Support for ST-Ericsson U300 series mobile platforms.
936 bool "ST-Ericsson U8500 Series"
940 select GENERIC_CLOCKEVENTS
942 select ARCH_REQUIRE_GPIOLIB
943 select ARCH_HAS_CPUFREQ
945 select MIGHT_HAVE_CACHE_L2X0
947 Support for ST-Ericsson's Ux500 architecture
950 bool "STMicroelectronics Nomadik"
955 select GENERIC_CLOCKEVENTS
957 select MIGHT_HAVE_CACHE_L2X0
958 select ARCH_REQUIRE_GPIOLIB
960 Support for the Nomadik platform by ST-Ericsson
964 select GENERIC_CLOCKEVENTS
965 select ARCH_REQUIRE_GPIOLIB
969 select GENERIC_ALLOCATOR
970 select GENERIC_IRQ_CHIP
971 select ARCH_HAS_HOLES_MEMORYMODEL
973 Support for TI's DaVinci platform.
979 select ARCH_REQUIRE_GPIOLIB
980 select ARCH_HAS_CPUFREQ
982 select GENERIC_CLOCKEVENTS
983 select ARCH_HAS_HOLES_MEMORYMODEL
985 Support for TI's OMAP platform (OMAP1/2/3/4).
990 select ARCH_REQUIRE_GPIOLIB
994 select GENERIC_CLOCKEVENTS
997 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
1000 bool "VIA/WonderMedia 85xx"
1003 select ARCH_HAS_CPUFREQ
1004 select GENERIC_CLOCKEVENTS
1005 select ARCH_REQUIRE_GPIOLIB
1008 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
1011 bool "Xilinx Zynq ARM Cortex A9 Platform"
1013 select GENERIC_CLOCKEVENTS
1014 select CLKDEV_LOOKUP
1018 select MIGHT_HAVE_CACHE_L2X0
1021 Support for Xilinx Zynq ARM Cortex A9 Platform
1025 # This is sorted alphabetically by mach-* pathname. However, plat-*
1026 # Kconfigs may be included either alphabetically (according to the
1027 # plat- suffix) or along side the corresponding mach-* source.
1029 source "arch/arm/mach-mvebu/Kconfig"
1031 source "arch/arm/mach-at91/Kconfig"
1033 source "arch/arm/mach-bcmring/Kconfig"
1035 source "arch/arm/mach-clps711x/Kconfig"
1037 source "arch/arm/mach-cns3xxx/Kconfig"
1039 source "arch/arm/mach-davinci/Kconfig"
1041 source "arch/arm/mach-dove/Kconfig"
1043 source "arch/arm/mach-ep93xx/Kconfig"
1045 source "arch/arm/mach-footbridge/Kconfig"
1047 source "arch/arm/mach-gemini/Kconfig"
1049 source "arch/arm/mach-h720x/Kconfig"
1051 source "arch/arm/mach-integrator/Kconfig"
1053 source "arch/arm/mach-iop32x/Kconfig"
1055 source "arch/arm/mach-iop33x/Kconfig"
1057 source "arch/arm/mach-iop13xx/Kconfig"
1059 source "arch/arm/mach-ixp4xx/Kconfig"
1061 source "arch/arm/mach-kirkwood/Kconfig"
1063 source "arch/arm/mach-ks8695/Kconfig"
1065 source "arch/arm/mach-msm/Kconfig"
1067 source "arch/arm/mach-mv78xx0/Kconfig"
1069 source "arch/arm/plat-mxc/Kconfig"
1071 source "arch/arm/mach-mxs/Kconfig"
1073 source "arch/arm/mach-netx/Kconfig"
1075 source "arch/arm/mach-nomadik/Kconfig"
1076 source "arch/arm/plat-nomadik/Kconfig"
1078 source "arch/arm/plat-omap/Kconfig"
1080 source "arch/arm/mach-omap1/Kconfig"
1082 source "arch/arm/mach-omap2/Kconfig"
1084 source "arch/arm/mach-orion5x/Kconfig"
1086 source "arch/arm/mach-pxa/Kconfig"
1087 source "arch/arm/plat-pxa/Kconfig"
1089 source "arch/arm/mach-mmp/Kconfig"
1091 source "arch/arm/mach-realview/Kconfig"
1093 source "arch/arm/mach-sa1100/Kconfig"
1095 source "arch/arm/plat-samsung/Kconfig"
1096 source "arch/arm/plat-s3c24xx/Kconfig"
1098 source "arch/arm/plat-spear/Kconfig"
1100 source "arch/arm/mach-s3c24xx/Kconfig"
1102 source "arch/arm/mach-s3c2412/Kconfig"
1103 source "arch/arm/mach-s3c2440/Kconfig"
1107 source "arch/arm/mach-s3c64xx/Kconfig"
1110 source "arch/arm/mach-s5p64x0/Kconfig"
1112 source "arch/arm/mach-s5pc100/Kconfig"
1114 source "arch/arm/mach-s5pv210/Kconfig"
1116 source "arch/arm/mach-exynos/Kconfig"
1118 source "arch/arm/mach-shmobile/Kconfig"
1120 source "arch/arm/mach-tegra/Kconfig"
1122 source "arch/arm/mach-u300/Kconfig"
1124 source "arch/arm/mach-ux500/Kconfig"
1126 source "arch/arm/mach-versatile/Kconfig"
1128 source "arch/arm/mach-vexpress/Kconfig"
1129 source "arch/arm/plat-versatile/Kconfig"
1131 source "arch/arm/mach-vt8500/Kconfig"
1133 source "arch/arm/mach-w90x900/Kconfig"
1135 # Definitions to make life easier
1141 select GENERIC_CLOCKEVENTS
1146 select GENERIC_IRQ_CHIP
1152 config PLAT_VERSATILE
1155 config ARM_TIMER_SP804
1158 select HAVE_SCHED_CLOCK
1160 source arch/arm/mm/Kconfig
1164 default 16 if ARCH_EP93XX
1168 bool "Enable iWMMXt support"
1169 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1170 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1172 Enable support for iWMMXt context switching at run time if
1173 running on a CPU that supports it.
1177 depends on CPU_XSCALE
1181 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1182 (!ARCH_OMAP3 || OMAP3_EMU)
1186 config MULTI_IRQ_HANDLER
1189 Allow each machine to specify it's own IRQ handler at run time.
1192 source "arch/arm/Kconfig-nommu"
1195 config ARM_ERRATA_326103
1196 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1199 Executing a SWP instruction to read-only memory does not set bit 11
1200 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1201 treat the access as a read, preventing a COW from occurring and
1202 causing the faulting task to livelock.
1204 config ARM_ERRATA_411920
1205 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1206 depends on CPU_V6 || CPU_V6K
1208 Invalidation of the Instruction Cache operation can
1209 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1210 It does not affect the MPCore. This option enables the ARM Ltd.
1211 recommended workaround.
1213 config ARM_ERRATA_430973
1214 bool "ARM errata: Stale prediction on replaced interworking branch"
1217 This option enables the workaround for the 430973 Cortex-A8
1218 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1219 interworking branch is replaced with another code sequence at the
1220 same virtual address, whether due to self-modifying code or virtual
1221 to physical address re-mapping, Cortex-A8 does not recover from the
1222 stale interworking branch prediction. This results in Cortex-A8
1223 executing the new code sequence in the incorrect ARM or Thumb state.
1224 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1225 and also flushes the branch target cache at every context switch.
1226 Note that setting specific bits in the ACTLR register may not be
1227 available in non-secure mode.
1229 config ARM_ERRATA_458693
1230 bool "ARM errata: Processor deadlock when a false hazard is created"
1233 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1234 erratum. For very specific sequences of memory operations, it is
1235 possible for a hazard condition intended for a cache line to instead
1236 be incorrectly associated with a different cache line. This false
1237 hazard might then cause a processor deadlock. The workaround enables
1238 the L1 caching of the NEON accesses and disables the PLD instruction
1239 in the ACTLR register. Note that setting specific bits in the ACTLR
1240 register may not be available in non-secure mode.
1242 config ARM_ERRATA_460075
1243 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1246 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1247 erratum. Any asynchronous access to the L2 cache may encounter a
1248 situation in which recent store transactions to the L2 cache are lost
1249 and overwritten with stale memory contents from external memory. The
1250 workaround disables the write-allocate mode for the L2 cache via the
1251 ACTLR register. Note that setting specific bits in the ACTLR register
1252 may not be available in non-secure mode.
1254 config ARM_ERRATA_742230
1255 bool "ARM errata: DMB operation may be faulty"
1256 depends on CPU_V7 && SMP
1258 This option enables the workaround for the 742230 Cortex-A9
1259 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1260 between two write operations may not ensure the correct visibility
1261 ordering of the two writes. This workaround sets a specific bit in
1262 the diagnostic register of the Cortex-A9 which causes the DMB
1263 instruction to behave as a DSB, ensuring the correct behaviour of
1266 config ARM_ERRATA_742231
1267 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1268 depends on CPU_V7 && SMP
1270 This option enables the workaround for the 742231 Cortex-A9
1271 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1272 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1273 accessing some data located in the same cache line, may get corrupted
1274 data due to bad handling of the address hazard when the line gets
1275 replaced from one of the CPUs at the same time as another CPU is
1276 accessing it. This workaround sets specific bits in the diagnostic
1277 register of the Cortex-A9 which reduces the linefill issuing
1278 capabilities of the processor.
1280 config PL310_ERRATA_588369
1281 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1282 depends on CACHE_L2X0
1284 The PL310 L2 cache controller implements three types of Clean &
1285 Invalidate maintenance operations: by Physical Address
1286 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1287 They are architecturally defined to behave as the execution of a
1288 clean operation followed immediately by an invalidate operation,
1289 both performing to the same memory location. This functionality
1290 is not correctly implemented in PL310 as clean lines are not
1291 invalidated as a result of these operations.
1293 config ARM_ERRATA_720789
1294 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1297 This option enables the workaround for the 720789 Cortex-A9 (prior to
1298 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1299 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1300 As a consequence of this erratum, some TLB entries which should be
1301 invalidated are not, resulting in an incoherency in the system page
1302 tables. The workaround changes the TLB flushing routines to invalidate
1303 entries regardless of the ASID.
1305 config PL310_ERRATA_727915
1306 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1307 depends on CACHE_L2X0
1309 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1310 operation (offset 0x7FC). This operation runs in background so that
1311 PL310 can handle normal accesses while it is in progress. Under very
1312 rare circumstances, due to this erratum, write data can be lost when
1313 PL310 treats a cacheable write transaction during a Clean &
1314 Invalidate by Way operation.
1316 config ARM_ERRATA_743622
1317 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1320 This option enables the workaround for the 743622 Cortex-A9
1321 (r2p*) erratum. Under very rare conditions, a faulty
1322 optimisation in the Cortex-A9 Store Buffer may lead to data
1323 corruption. This workaround sets a specific bit in the diagnostic
1324 register of the Cortex-A9 which disables the Store Buffer
1325 optimisation, preventing the defect from occurring. This has no
1326 visible impact on the overall performance or power consumption of the
1329 config ARM_ERRATA_751472
1330 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1333 This option enables the workaround for the 751472 Cortex-A9 (prior
1334 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1335 completion of a following broadcasted operation if the second
1336 operation is received by a CPU before the ICIALLUIS has completed,
1337 potentially leading to corrupted entries in the cache or TLB.
1339 config PL310_ERRATA_753970
1340 bool "PL310 errata: cache sync operation may be faulty"
1341 depends on CACHE_PL310
1343 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1345 Under some condition the effect of cache sync operation on
1346 the store buffer still remains when the operation completes.
1347 This means that the store buffer is always asked to drain and
1348 this prevents it from merging any further writes. The workaround
1349 is to replace the normal offset of cache sync operation (0x730)
1350 by another offset targeting an unmapped PL310 register 0x740.
1351 This has the same effect as the cache sync operation: store buffer
1352 drain and waiting for all buffers empty.
1354 config ARM_ERRATA_754322
1355 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1358 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1359 r3p*) erratum. A speculative memory access may cause a page table walk
1360 which starts prior to an ASID switch but completes afterwards. This
1361 can populate the micro-TLB with a stale entry which may be hit with
1362 the new ASID. This workaround places two dsb instructions in the mm
1363 switching code so that no page table walks can cross the ASID switch.
1365 config ARM_ERRATA_754327
1366 bool "ARM errata: no automatic Store Buffer drain"
1367 depends on CPU_V7 && SMP
1369 This option enables the workaround for the 754327 Cortex-A9 (prior to
1370 r2p0) erratum. The Store Buffer does not have any automatic draining
1371 mechanism and therefore a livelock may occur if an external agent
1372 continuously polls a memory location waiting to observe an update.
1373 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1374 written polling loops from denying visibility of updates to memory.
1376 config ARM_ERRATA_364296
1377 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1378 depends on CPU_V6 && !SMP
1380 This options enables the workaround for the 364296 ARM1136
1381 r0p2 erratum (possible cache data corruption with
1382 hit-under-miss enabled). It sets the undocumented bit 31 in
1383 the auxiliary control register and the FI bit in the control
1384 register, thus disabling hit-under-miss without putting the
1385 processor into full low interrupt latency mode. ARM11MPCore
1388 config ARM_ERRATA_764369
1389 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1390 depends on CPU_V7 && SMP
1392 This option enables the workaround for erratum 764369
1393 affecting Cortex-A9 MPCore with two or more processors (all
1394 current revisions). Under certain timing circumstances, a data
1395 cache line maintenance operation by MVA targeting an Inner
1396 Shareable memory region may fail to proceed up to either the
1397 Point of Coherency or to the Point of Unification of the
1398 system. This workaround adds a DSB instruction before the
1399 relevant cache maintenance functions and sets a specific bit
1400 in the diagnostic control register of the SCU.
1402 config PL310_ERRATA_769419
1403 bool "PL310 errata: no automatic Store Buffer drain"
1404 depends on CACHE_L2X0
1406 On revisions of the PL310 prior to r3p2, the Store Buffer does
1407 not automatically drain. This can cause normal, non-cacheable
1408 writes to be retained when the memory system is idle, leading
1409 to suboptimal I/O performance for drivers using coherent DMA.
1410 This option adds a write barrier to the cpu_idle loop so that,
1411 on systems with an outer cache, the store buffer is drained
1416 source "arch/arm/common/Kconfig"
1426 Find out whether you have ISA slots on your motherboard. ISA is the
1427 name of a bus system, i.e. the way the CPU talks to the other stuff
1428 inside your box. Other bus systems are PCI, EISA, MicroChannel
1429 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1430 newer boards don't support it. If you have ISA, say Y, otherwise N.
1432 # Select ISA DMA controller support
1437 # Select ISA DMA interface
1442 bool "PCI support" if MIGHT_HAVE_PCI
1444 Find out whether you have a PCI motherboard. PCI is the name of a
1445 bus system, i.e. the way the CPU talks to the other stuff inside
1446 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1447 VESA. If you have PCI, say Y, otherwise N.
1453 config PCI_NANOENGINE
1454 bool "BSE nanoEngine PCI support"
1455 depends on SA1100_NANOENGINE
1457 Enable PCI on the BSE nanoEngine board.
1462 # Select the host bridge type
1463 config PCI_HOST_VIA82C505
1465 depends on PCI && ARCH_SHARK
1468 config PCI_HOST_ITE8152
1470 depends on PCI && MACH_ARMCORE
1474 source "drivers/pci/Kconfig"
1476 source "drivers/pcmcia/Kconfig"
1480 menu "Kernel Features"
1485 This option should be selected by machines which have an SMP-
1488 The only effect of this option is to make the SMP-related
1489 options available to the user for configuration.
1492 bool "Symmetric Multi-Processing"
1493 depends on CPU_V6K || CPU_V7
1494 depends on GENERIC_CLOCKEVENTS
1497 select USE_GENERIC_SMP_HELPERS
1498 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1500 This enables support for systems with more than one CPU. If you have
1501 a system with only one CPU, like most personal computers, say N. If
1502 you have a system with more than one CPU, say Y.
1504 If you say N here, the kernel will run on single and multiprocessor
1505 machines, but will use only one CPU of a multiprocessor machine. If
1506 you say Y here, the kernel will run on many, but not all, single
1507 processor machines. On a single processor machine, the kernel will
1508 run faster if you say N here.
1510 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1511 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1512 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1514 If you don't know what to do here, say N.
1517 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1518 depends on EXPERIMENTAL
1519 depends on SMP && !XIP_KERNEL
1522 SMP kernels contain instructions which fail on non-SMP processors.
1523 Enabling this option allows the kernel to modify itself to make
1524 these instructions safe. Disabling it allows about 1K of space
1527 If you don't know what to do here, say Y.
1529 config ARM_CPU_TOPOLOGY
1530 bool "Support cpu topology definition"
1531 depends on SMP && CPU_V7
1534 Support ARM cpu topology definition. The MPIDR register defines
1535 affinity between processors which is then used to describe the cpu
1536 topology of an ARM System.
1539 bool "Multi-core scheduler support"
1540 depends on ARM_CPU_TOPOLOGY
1542 Multi-core scheduler support improves the CPU scheduler's decision
1543 making when dealing with multi-core CPU chips at a cost of slightly
1544 increased overhead in some places. If unsure say N here.
1547 bool "SMT scheduler support"
1548 depends on ARM_CPU_TOPOLOGY
1550 Improves the CPU scheduler's decision making when dealing with
1551 MultiThreading at a cost of slightly increased overhead in some
1552 places. If unsure say N here.
1557 This option enables support for the ARM system coherency unit
1559 config ARM_ARCH_TIMER
1560 bool "Architected timer support"
1563 This option enables support for the ARM architected timer
1569 This options enables support for the ARM timer and watchdog unit
1572 prompt "Memory split"
1575 Select the desired split between kernel and user memory.
1577 If you are not absolutely sure what you are doing, leave this
1581 bool "3G/1G user/kernel split"
1583 bool "2G/2G user/kernel split"
1585 bool "1G/3G user/kernel split"
1590 default 0x40000000 if VMSPLIT_1G
1591 default 0x80000000 if VMSPLIT_2G
1595 int "Maximum number of CPUs (2-32)"
1601 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1602 depends on SMP && HOTPLUG && EXPERIMENTAL
1604 Say Y here to experiment with turning CPUs off and on. CPUs
1605 can be controlled through /sys/devices/system/cpu.
1608 bool "Use local timer interrupts"
1611 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1613 Enable support for local timers on SMP platforms, rather then the
1614 legacy IPI broadcast method. Local timers allows the system
1615 accounting to be spread across the timer interval, preventing a
1616 "thundering herd" at every timer tick.
1620 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1621 default 355 if ARCH_U8500
1622 default 264 if MACH_H4700
1623 default 512 if SOC_OMAP5
1626 Maximum number of GPIOs in the system.
1628 If unsure, leave the default value.
1630 source kernel/Kconfig.preempt
1634 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1635 ARCH_S5PV210 || ARCH_EXYNOS4
1636 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1637 default AT91_TIMER_HZ if ARCH_AT91
1638 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1641 config THUMB2_KERNEL
1642 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1643 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1645 select ARM_ASM_UNIFIED
1648 By enabling this option, the kernel will be compiled in
1649 Thumb-2 mode. A compiler/assembler that understand the unified
1650 ARM-Thumb syntax is needed.
1654 config THUMB2_AVOID_R_ARM_THM_JUMP11
1655 bool "Work around buggy Thumb-2 short branch relocations in gas"
1656 depends on THUMB2_KERNEL && MODULES
1659 Various binutils versions can resolve Thumb-2 branches to
1660 locally-defined, preemptible global symbols as short-range "b.n"
1661 branch instructions.
1663 This is a problem, because there's no guarantee the final
1664 destination of the symbol, or any candidate locations for a
1665 trampoline, are within range of the branch. For this reason, the
1666 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1667 relocation in modules at all, and it makes little sense to add
1670 The symptom is that the kernel fails with an "unsupported
1671 relocation" error when loading some modules.
1673 Until fixed tools are available, passing
1674 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1675 code which hits this problem, at the cost of a bit of extra runtime
1676 stack usage in some cases.
1678 The problem is described in more detail at:
1679 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1681 Only Thumb-2 kernels are affected.
1683 Unless you are sure your tools don't have this problem, say Y.
1685 config ARM_ASM_UNIFIED
1689 bool "Use the ARM EABI to compile the kernel"
1691 This option allows for the kernel to be compiled using the latest
1692 ARM ABI (aka EABI). This is only useful if you are using a user
1693 space environment that is also compiled with EABI.
1695 Since there are major incompatibilities between the legacy ABI and
1696 EABI, especially with regard to structure member alignment, this
1697 option also changes the kernel syscall calling convention to
1698 disambiguate both ABIs and allow for backward compatibility support
1699 (selected with CONFIG_OABI_COMPAT).
1701 To use this you need GCC version 4.0.0 or later.
1704 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1705 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1708 This option preserves the old syscall interface along with the
1709 new (ARM EABI) one. It also provides a compatibility layer to
1710 intercept syscalls that have structure arguments which layout
1711 in memory differs between the legacy ABI and the new ARM EABI
1712 (only for non "thumb" binaries). This option adds a tiny
1713 overhead to all syscalls and produces a slightly larger kernel.
1714 If you know you'll be using only pure EABI user space then you
1715 can say N here. If this option is not selected and you attempt
1716 to execute a legacy ABI binary then the result will be
1717 UNPREDICTABLE (in fact it can be predicted that it won't work
1718 at all). If in doubt say Y.
1720 config ARCH_HAS_HOLES_MEMORYMODEL
1723 config ARCH_SPARSEMEM_ENABLE
1726 config ARCH_SPARSEMEM_DEFAULT
1727 def_bool ARCH_SPARSEMEM_ENABLE
1729 config ARCH_SELECT_MEMORY_MODEL
1730 def_bool ARCH_SPARSEMEM_ENABLE
1732 config HAVE_ARCH_PFN_VALID
1733 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1736 bool "High Memory Support"
1739 The address space of ARM processors is only 4 Gigabytes large
1740 and it has to accommodate user address space, kernel address
1741 space as well as some memory mapped IO. That means that, if you
1742 have a large amount of physical memory and/or IO, not all of the
1743 memory can be "permanently mapped" by the kernel. The physical
1744 memory that is not permanently mapped is called "high memory".
1746 Depending on the selected kernel/user memory split, minimum
1747 vmalloc space and actual amount of RAM, you may not need this
1748 option which should result in a slightly faster kernel.
1753 bool "Allocate 2nd-level pagetables from highmem"
1756 config HW_PERF_EVENTS
1757 bool "Enable hardware performance counter support for perf events"
1758 depends on PERF_EVENTS && CPU_HAS_PMU
1761 Enable hardware performance counter support for perf events. If
1762 disabled, perf events will use software events only.
1766 config FORCE_MAX_ZONEORDER
1767 int "Maximum zone order" if ARCH_SHMOBILE
1768 range 11 64 if ARCH_SHMOBILE
1769 default "9" if SA1111
1772 The kernel memory allocator divides physically contiguous memory
1773 blocks into "zones", where each zone is a power of two number of
1774 pages. This option selects the largest power of two that the kernel
1775 keeps in the memory allocator. If you need to allocate very large
1776 blocks of physically contiguous memory, then you may need to
1777 increase this value.
1779 This config option is actually maximum order plus one. For example,
1780 a value of 11 means that the largest free memory block is 2^10 pages.
1783 bool "Timer and CPU usage LEDs"
1784 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1785 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1786 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1787 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1788 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1789 ARCH_AT91 || ARCH_DAVINCI || \
1790 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1792 If you say Y here, the LEDs on your machine will be used
1793 to provide useful information about your current system status.
1795 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1796 be able to select which LEDs are active using the options below. If
1797 you are compiling a kernel for the EBSA-110 or the LART however, the
1798 red LED will simply flash regularly to indicate that the system is
1799 still functional. It is safe to say Y here if you have a CATS
1800 system, but the driver will do nothing.
1803 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1804 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1805 || MACH_OMAP_PERSEUS2
1807 depends on !GENERIC_CLOCKEVENTS
1808 default y if ARCH_EBSA110
1810 If you say Y here, one of the system LEDs (the green one on the
1811 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1812 will flash regularly to indicate that the system is still
1813 operational. This is mainly useful to kernel hackers who are
1814 debugging unstable kernels.
1816 The LART uses the same LED for both Timer LED and CPU usage LED
1817 functions. You may choose to use both, but the Timer LED function
1818 will overrule the CPU usage LED.
1821 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1823 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1824 || MACH_OMAP_PERSEUS2
1827 If you say Y here, the red LED will be used to give a good real
1828 time indication of CPU usage, by lighting whenever the idle task
1829 is not currently executing.
1831 The LART uses the same LED for both Timer LED and CPU usage LED
1832 functions. You may choose to use both, but the Timer LED function
1833 will overrule the CPU usage LED.
1835 config ALIGNMENT_TRAP
1837 depends on CPU_CP15_MMU
1838 default y if !ARCH_EBSA110
1839 select HAVE_PROC_CPU if PROC_FS
1841 ARM processors cannot fetch/store information which is not
1842 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1843 address divisible by 4. On 32-bit ARM processors, these non-aligned
1844 fetch/store instructions will be emulated in software if you say
1845 here, which has a severe performance impact. This is necessary for
1846 correct operation of some network protocols. With an IP-only
1847 configuration it is safe to say N, otherwise say Y.
1849 config UACCESS_WITH_MEMCPY
1850 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1851 depends on MMU && EXPERIMENTAL
1852 default y if CPU_FEROCEON
1854 Implement faster copy_to_user and clear_user methods for CPU
1855 cores where a 8-word STM instruction give significantly higher
1856 memory write throughput than a sequence of individual 32bit stores.
1858 A possible side effect is a slight increase in scheduling latency
1859 between threads sharing the same address space if they invoke
1860 such copy operations with large buffers.
1862 However, if the CPU data cache is using a write-allocate mode,
1863 this option is unlikely to provide any performance gain.
1867 prompt "Enable seccomp to safely compute untrusted bytecode"
1869 This kernel feature is useful for number crunching applications
1870 that may need to compute untrusted bytecode during their
1871 execution. By using pipes or other transports made available to
1872 the process as file descriptors supporting the read/write
1873 syscalls, it's possible to isolate those applications in
1874 their own address space using seccomp. Once seccomp is
1875 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1876 and the task is only allowed to execute a few safe syscalls
1877 defined by each seccomp mode.
1879 config CC_STACKPROTECTOR
1880 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1881 depends on EXPERIMENTAL
1883 This option turns on the -fstack-protector GCC feature. This
1884 feature puts, at the beginning of functions, a canary value on
1885 the stack just before the return address, and validates
1886 the value just before actually returning. Stack based buffer
1887 overflows (that need to overwrite this return address) now also
1888 overwrite the canary, which gets detected and the attack is then
1889 neutralized via a kernel panic.
1890 This feature requires gcc version 4.2 or above.
1892 config DEPRECATED_PARAM_STRUCT
1893 bool "Provide old way to pass kernel parameters"
1895 This was deprecated in 2001 and announced to live on for 5 years.
1896 Some old boot loaders still use this way.
1903 bool "Flattened Device Tree support"
1905 select OF_EARLY_FLATTREE
1908 Include support for flattened device tree machine descriptions.
1910 # Compressed boot loader in ROM. Yes, we really want to ask about
1911 # TEXT and BSS so we preserve their values in the config files.
1912 config ZBOOT_ROM_TEXT
1913 hex "Compressed ROM boot loader base address"
1916 The physical address at which the ROM-able zImage is to be
1917 placed in the target. Platforms which normally make use of
1918 ROM-able zImage formats normally set this to a suitable
1919 value in their defconfig file.
1921 If ZBOOT_ROM is not enabled, this has no effect.
1923 config ZBOOT_ROM_BSS
1924 hex "Compressed ROM boot loader BSS address"
1927 The base address of an area of read/write memory in the target
1928 for the ROM-able zImage which must be available while the
1929 decompressor is running. It must be large enough to hold the
1930 entire decompressed kernel plus an additional 128 KiB.
1931 Platforms which normally make use of ROM-able zImage formats
1932 normally set this to a suitable value in their defconfig file.
1934 If ZBOOT_ROM is not enabled, this has no effect.
1937 bool "Compressed boot loader in ROM/flash"
1938 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1940 Say Y here if you intend to execute your compressed kernel image
1941 (zImage) directly from ROM or flash. If unsure, say N.
1944 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1945 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1946 default ZBOOT_ROM_NONE
1948 Include experimental SD/MMC loading code in the ROM-able zImage.
1949 With this enabled it is possible to write the ROM-able zImage
1950 kernel image to an MMC or SD card and boot the kernel straight
1951 from the reset vector. At reset the processor Mask ROM will load
1952 the first part of the ROM-able zImage which in turn loads the
1953 rest the kernel image to RAM.
1955 config ZBOOT_ROM_NONE
1956 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1958 Do not load image from SD or MMC
1960 config ZBOOT_ROM_MMCIF
1961 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1963 Load image from MMCIF hardware block.
1965 config ZBOOT_ROM_SH_MOBILE_SDHI
1966 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1968 Load image from SDHI hardware block
1972 config ARM_APPENDED_DTB
1973 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1974 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1976 With this option, the boot code will look for a device tree binary
1977 (DTB) appended to zImage
1978 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1980 This is meant as a backward compatibility convenience for those
1981 systems with a bootloader that can't be upgraded to accommodate
1982 the documented boot protocol using a device tree.
1984 Beware that there is very little in terms of protection against
1985 this option being confused by leftover garbage in memory that might
1986 look like a DTB header after a reboot if no actual DTB is appended
1987 to zImage. Do not leave this option active in a production kernel
1988 if you don't intend to always append a DTB. Proper passing of the
1989 location into r2 of a bootloader provided DTB is always preferable
1992 config ARM_ATAG_DTB_COMPAT
1993 bool "Supplement the appended DTB with traditional ATAG information"
1994 depends on ARM_APPENDED_DTB
1996 Some old bootloaders can't be updated to a DTB capable one, yet
1997 they provide ATAGs with memory configuration, the ramdisk address,
1998 the kernel cmdline string, etc. Such information is dynamically
1999 provided by the bootloader and can't always be stored in a static
2000 DTB. To allow a device tree enabled kernel to be used with such
2001 bootloaders, this option allows zImage to extract the information
2002 from the ATAG list and store it at run time into the appended DTB.
2005 string "Default kernel command string"
2008 On some architectures (EBSA110 and CATS), there is currently no way
2009 for the boot loader to pass arguments to the kernel. For these
2010 architectures, you should supply some command-line options at build
2011 time by entering them here. As a minimum, you should specify the
2012 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2015 prompt "Kernel command line type" if CMDLINE != ""
2016 default CMDLINE_FROM_BOOTLOADER
2018 config CMDLINE_FROM_BOOTLOADER
2019 bool "Use bootloader kernel arguments if available"
2021 Uses the command-line options passed by the boot loader. If
2022 the boot loader doesn't provide any, the default kernel command
2023 string provided in CMDLINE will be used.
2025 config CMDLINE_EXTEND
2026 bool "Extend bootloader kernel arguments"
2028 The command-line arguments provided by the boot loader will be
2029 appended to the default kernel command string.
2031 config CMDLINE_FORCE
2032 bool "Always use the default kernel command string"
2034 Always use the default kernel command string, even if the boot
2035 loader passes other arguments to the kernel.
2036 This is useful if you cannot or don't want to change the
2037 command-line options your boot loader passes to the kernel.
2041 bool "Kernel Execute-In-Place from ROM"
2042 depends on !ZBOOT_ROM && !ARM_LPAE
2044 Execute-In-Place allows the kernel to run from non-volatile storage
2045 directly addressable by the CPU, such as NOR flash. This saves RAM
2046 space since the text section of the kernel is not loaded from flash
2047 to RAM. Read-write sections, such as the data section and stack,
2048 are still copied to RAM. The XIP kernel is not compressed since
2049 it has to run directly from flash, so it will take more space to
2050 store it. The flash address used to link the kernel object files,
2051 and for storing it, is configuration dependent. Therefore, if you
2052 say Y here, you must know the proper physical address where to
2053 store the kernel image depending on your own flash memory usage.
2055 Also note that the make target becomes "make xipImage" rather than
2056 "make zImage" or "make Image". The final kernel binary to put in
2057 ROM memory will be arch/arm/boot/xipImage.
2061 config XIP_PHYS_ADDR
2062 hex "XIP Kernel Physical Location"
2063 depends on XIP_KERNEL
2064 default "0x00080000"
2066 This is the physical address in your flash memory the kernel will
2067 be linked for and stored to. This address is dependent on your
2071 bool "Kexec system call (EXPERIMENTAL)"
2072 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2074 kexec is a system call that implements the ability to shutdown your
2075 current kernel, and to start another kernel. It is like a reboot
2076 but it is independent of the system firmware. And like a reboot
2077 you can start any kernel with it, not just Linux.
2079 It is an ongoing process to be certain the hardware in a machine
2080 is properly shutdown, so do not be surprised if this code does not
2081 initially work for you. It may help to enable device hotplugging
2085 bool "Export atags in procfs"
2089 Should the atags used to boot the kernel be exported in an "atags"
2090 file in procfs. Useful with kexec.
2093 bool "Build kdump crash kernel (EXPERIMENTAL)"
2094 depends on EXPERIMENTAL
2096 Generate crash dump after being started by kexec. This should
2097 be normally only set in special crash dump kernels which are
2098 loaded in the main kernel with kexec-tools into a specially
2099 reserved region and then later executed after a crash by
2100 kdump/kexec. The crash dump kernel must be compiled to a
2101 memory address not used by the main kernel
2103 For more details see Documentation/kdump/kdump.txt
2105 config AUTO_ZRELADDR
2106 bool "Auto calculation of the decompressed kernel image address"
2107 depends on !ZBOOT_ROM && !ARCH_U300
2109 ZRELADDR is the physical address where the decompressed kernel
2110 image will be placed. If AUTO_ZRELADDR is selected, the address
2111 will be determined at run-time by masking the current IP with
2112 0xf8000000. This assumes the zImage being placed in the first 128MB
2113 from start of memory.
2117 menu "CPU Power Management"
2121 source "drivers/cpufreq/Kconfig"
2124 tristate "CPUfreq driver for i.MX CPUs"
2125 depends on ARCH_MXC && CPU_FREQ
2127 This enables the CPUfreq driver for i.MX CPUs.
2129 config CPU_FREQ_SA1100
2132 config CPU_FREQ_SA1110
2135 config CPU_FREQ_INTEGRATOR
2136 tristate "CPUfreq driver for ARM Integrator CPUs"
2137 depends on ARCH_INTEGRATOR && CPU_FREQ
2140 This enables the CPUfreq driver for ARM Integrator CPUs.
2142 For details, take a look at <file:Documentation/cpu-freq>.
2148 depends on CPU_FREQ && ARCH_PXA && PXA25x
2150 select CPU_FREQ_TABLE
2151 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2156 Internal configuration node for common cpufreq on Samsung SoC
2158 config CPU_FREQ_S3C24XX
2159 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2160 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2163 This enables the CPUfreq driver for the Samsung S3C24XX family
2166 For details, take a look at <file:Documentation/cpu-freq>.
2170 config CPU_FREQ_S3C24XX_PLL
2171 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2172 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2174 Compile in support for changing the PLL frequency from the
2175 S3C24XX series CPUfreq driver. The PLL takes time to settle
2176 after a frequency change, so by default it is not enabled.
2178 This also means that the PLL tables for the selected CPU(s) will
2179 be built which may increase the size of the kernel image.
2181 config CPU_FREQ_S3C24XX_DEBUG
2182 bool "Debug CPUfreq Samsung driver core"
2183 depends on CPU_FREQ_S3C24XX
2185 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2187 config CPU_FREQ_S3C24XX_IODEBUG
2188 bool "Debug CPUfreq Samsung driver IO timing"
2189 depends on CPU_FREQ_S3C24XX
2191 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2193 config CPU_FREQ_S3C24XX_DEBUGFS
2194 bool "Export debugfs for CPUFreq"
2195 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2197 Export status information via debugfs.
2201 source "drivers/cpuidle/Kconfig"
2205 menu "Floating point emulation"
2207 comment "At least one emulation must be selected"
2210 bool "NWFPE math emulation"
2211 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2213 Say Y to include the NWFPE floating point emulator in the kernel.
2214 This is necessary to run most binaries. Linux does not currently
2215 support floating point hardware so you need to say Y here even if
2216 your machine has an FPA or floating point co-processor podule.
2218 You may say N here if you are going to load the Acorn FPEmulator
2219 early in the bootup.
2222 bool "Support extended precision"
2223 depends on FPE_NWFPE
2225 Say Y to include 80-bit support in the kernel floating-point
2226 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2227 Note that gcc does not generate 80-bit operations by default,
2228 so in most cases this option only enlarges the size of the
2229 floating point emulator without any good reason.
2231 You almost surely want to say N here.
2234 bool "FastFPE math emulation (EXPERIMENTAL)"
2235 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2237 Say Y here to include the FAST floating point emulator in the kernel.
2238 This is an experimental much faster emulator which now also has full
2239 precision for the mantissa. It does not support any exceptions.
2240 It is very simple, and approximately 3-6 times faster than NWFPE.
2242 It should be sufficient for most programs. It may be not suitable
2243 for scientific calculations, but you have to check this for yourself.
2244 If you do not feel you need a faster FP emulation you should better
2248 bool "VFP-format floating point maths"
2249 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2251 Say Y to include VFP support code in the kernel. This is needed
2252 if your hardware includes a VFP unit.
2254 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2255 release notes and additional status information.
2257 Say N if your target does not have VFP hardware.
2265 bool "Advanced SIMD (NEON) Extension support"
2266 depends on VFPv3 && CPU_V7
2268 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2273 menu "Userspace binary formats"
2275 source "fs/Kconfig.binfmt"
2278 tristate "RISC OS personality"
2281 Say Y here to include the kernel code necessary if you want to run
2282 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2283 experimental; if this sounds frightening, say N and sleep in peace.
2284 You can also say M here to compile this support as a module (which
2285 will be called arthur).
2289 menu "Power management options"
2291 source "kernel/power/Kconfig"
2293 config ARCH_SUSPEND_POSSIBLE
2294 depends on !ARCH_S5PC100 && !ARCH_TEGRA
2295 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2296 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2299 config ARM_CPU_SUSPEND
2304 source "net/Kconfig"
2306 source "drivers/Kconfig"
2310 source "arch/arm/Kconfig.debug"
2312 source "security/Kconfig"
2314 source "crypto/Kconfig"
2316 source "lib/Kconfig"