4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
5 select ARCH_HAS_ELF_RANDOMIZE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_MIGHT_HAVE_PC_PARPORT
10 select ARCH_SUPPORTS_ATOMIC_RMW
11 select ARCH_USE_BUILTIN_BSWAP
12 select ARCH_USE_CMPXCHG_LOCKREF
13 select ARCH_WANT_IPC_PARSE_VERSION
14 select BUILDTIME_EXTABLE_SORT if MMU
15 select CLONE_BACKWARDS
16 select CPU_PM if (SUSPEND || CPU_IDLE)
17 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
19 select EDAC_ATOMIC_SCRUB
20 select GENERIC_ALLOCATOR
21 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
22 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
23 select GENERIC_IDLE_POLL_SETUP
24 select GENERIC_IRQ_PROBE
25 select GENERIC_IRQ_SHOW
26 select GENERIC_IRQ_SHOW_LEVEL
27 select GENERIC_PCI_IOMAP
28 select GENERIC_SCHED_CLOCK
29 select GENERIC_SMP_IDLE_THREAD
30 select GENERIC_STRNCPY_FROM_USER
31 select GENERIC_STRNLEN_USER
32 select HANDLE_DOMAIN_IRQ
33 select HARDIRQS_SW_RESEND
34 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
35 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
36 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32
37 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32
38 select HAVE_ARCH_MMAP_RND_BITS if MMU
39 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
40 select HAVE_ARCH_TRACEHOOK
42 select HAVE_CC_STACKPROTECTOR
43 select HAVE_CONTEXT_TRACKING
44 select HAVE_C_RECORDMCOUNT
45 select HAVE_DEBUG_KMEMLEAK
46 select HAVE_DMA_API_DEBUG
48 select HAVE_DMA_CONTIGUOUS if MMU
49 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32
50 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
51 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
52 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
53 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
54 select HAVE_GENERIC_DMA_COHERENT
55 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
56 select HAVE_IDE if PCI || ISA || PCMCIA
57 select HAVE_IRQ_TIME_ACCOUNTING
58 select HAVE_KERNEL_GZIP
59 select HAVE_KERNEL_LZ4
60 select HAVE_KERNEL_LZMA
61 select HAVE_KERNEL_LZO
63 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
64 select HAVE_KRETPROBES if (HAVE_KPROBES)
66 select HAVE_MOD_ARCH_SPECIFIC
67 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
68 select HAVE_OPTPROBES if !THUMB2_KERNEL
69 select HAVE_PERF_EVENTS
71 select HAVE_PERF_USER_STACK_DUMP
72 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
73 select HAVE_REGS_AND_STACK_ACCESS_API
74 select HAVE_SYSCALL_TRACEPOINTS
76 select HAVE_VIRT_CPU_ACCOUNTING_GEN
77 select IRQ_FORCED_THREADING
78 select MODULES_USE_ELF_REL
80 select OF_EARLY_FLATTREE if OF
81 select OF_RESERVED_MEM if OF
83 select OLD_SIGSUSPEND3
84 select PERF_USE_VMALLOC
86 select SYS_SUPPORTS_APM_EMULATION
87 # Above selects are sorted alphabetically; please add new ones
88 # according to that. Thanks.
90 The ARM series is a line of low-power-consumption RISC chip designs
91 licensed by ARM Ltd and targeted at embedded applications and
92 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
93 manufactured, but legacy ARM-based PC hardware remains popular in
94 Europe. There is an ARM Linux project with a web page at
95 <http://www.arm.linux.org.uk/>.
97 config ARM_HAS_SG_CHAIN
98 select ARCH_HAS_SG_CHAIN
101 config NEED_SG_DMA_LENGTH
104 config ARM_DMA_USE_IOMMU
106 select ARM_HAS_SG_CHAIN
107 select NEED_SG_DMA_LENGTH
111 config ARM_DMA_IOMMU_ALIGNMENT
112 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
116 DMA mapping framework by default aligns all buffers to the smallest
117 PAGE_SIZE order which is greater than or equal to the requested buffer
118 size. This works well for buffers up to a few hundreds kilobytes, but
119 for larger buffers it just a waste of address space. Drivers which has
120 relatively small addressing window (like 64Mib) might run out of
121 virtual space with just a few allocations.
123 With this parameter you can specify the maximum PAGE_SIZE order for
124 DMA IOMMU buffers. Larger buffers will be aligned only to this
125 specified order. The order is expressed as a power of two multiplied
130 config MIGHT_HAVE_PCI
133 config SYS_SUPPORTS_APM_EMULATION
138 select GENERIC_ALLOCATOR
149 The Extended Industry Standard Architecture (EISA) bus was
150 developed as an open alternative to the IBM MicroChannel bus.
152 The EISA bus provided some of the features of the IBM MicroChannel
153 bus while maintaining backward compatibility with cards made for
154 the older ISA bus. The EISA bus saw limited use between 1988 and
155 1995 when it was made obsolete by the PCI bus.
157 Say Y here if you are building a kernel for an EISA-based machine.
164 config STACKTRACE_SUPPORT
168 config HAVE_LATENCYTOP_SUPPORT
173 config LOCKDEP_SUPPORT
177 config TRACE_IRQFLAGS_SUPPORT
181 config RWSEM_XCHGADD_ALGORITHM
185 config ARCH_HAS_ILOG2_U32
188 config ARCH_HAS_ILOG2_U64
191 config ARCH_HAS_BANDGAP
194 config FIX_EARLYCON_MEM
197 config GENERIC_HWEIGHT
201 config GENERIC_CALIBRATE_DELAY
205 config ARCH_MAY_HAVE_PC_FDC
211 config NEED_DMA_MAP_STATE
214 config ARCH_SUPPORTS_UPROBES
217 config ARCH_HAS_DMA_SET_COHERENT_MASK
220 config GENERIC_ISA_DMA
226 config NEED_RET_TO_USER
234 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
235 default DRAM_BASE if REMAP_VECTORS_TO_RAM
238 The base address of exception vectors. This must be two pages
241 config ARM_PATCH_PHYS_VIRT
242 bool "Patch physical to virtual translations at runtime" if EMBEDDED
244 depends on !XIP_KERNEL && MMU
245 depends on !ARCH_REALVIEW || !SPARSEMEM
247 Patch phys-to-virt and virt-to-phys translation functions at
248 boot and module load time according to the position of the
249 kernel in system memory.
251 This can only be used with non-XIP MMU kernels where the base
252 of physical memory is at a 16MB boundary.
254 Only disable this option if you know that you do not require
255 this feature (eg, building a kernel for a single machine) and
256 you need to shrink the kernel to the minimal size.
258 config NEED_MACH_IO_H
261 Select this when mach/io.h is required to provide special
262 definitions for this platform. The need for mach/io.h should
263 be avoided when possible.
265 config NEED_MACH_MEMORY_H
268 Select this when mach/memory.h is required to provide special
269 definitions for this platform. The need for mach/memory.h should
270 be avoided when possible.
273 hex "Physical address of main memory" if MMU
274 depends on !ARM_PATCH_PHYS_VIRT
275 default DRAM_BASE if !MMU
276 default 0x00000000 if ARCH_EBSA110 || \
281 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
282 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
283 default 0x20000000 if ARCH_S5PV210
284 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
285 default 0xc0000000 if ARCH_SA1100
287 Please provide the physical address corresponding to the
288 location of main memory in your system.
294 config PGTABLE_LEVELS
296 default 3 if ARM_LPAE
299 source "init/Kconfig"
301 source "kernel/Kconfig.freezer"
306 bool "MMU-based Paged Memory Management Support"
309 Select if you want MMU-based virtualised addressing space
310 support by paged memory management. If unsure, say 'Y'.
312 config ARCH_MMAP_RND_BITS_MIN
315 config ARCH_MMAP_RND_BITS_MAX
316 default 14 if PAGE_OFFSET=0x40000000
317 default 15 if PAGE_OFFSET=0x80000000
321 # The "ARM system type" choice list is ordered alphabetically by option
322 # text. Please add new entries in the option alphabetic order.
325 prompt "ARM system type"
326 default ARCH_VERSATILE if !MMU
327 default ARCH_MULTIPLATFORM if MMU
329 config ARCH_MULTIPLATFORM
330 bool "Allow multiple platforms to be selected"
332 select ARCH_WANT_OPTIONAL_GPIOLIB
333 select ARM_HAS_SG_CHAIN
334 select ARM_PATCH_PHYS_VIRT
338 select GENERIC_CLOCKEVENTS
339 select MIGHT_HAVE_PCI
340 select MULTI_IRQ_HANDLER
344 config ARM_SINGLE_ARMV7M
345 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
347 select ARCH_WANT_OPTIONAL_GPIOLIB
353 select GENERIC_CLOCKEVENTS
359 bool "ARM Ltd. RealView family"
360 select ARCH_WANT_OPTIONAL_GPIOLIB
362 select ARM_TIMER_SP804
364 select COMMON_CLK_VERSATILE
365 select GENERIC_CLOCKEVENTS
366 select GPIO_PL061 if GPIOLIB
368 select NEED_MACH_MEMORY_H
369 select PLAT_VERSATILE
370 select PLAT_VERSATILE_SCHED_CLOCK
372 This enables support for ARM Ltd RealView boards.
374 config ARCH_VERSATILE
375 bool "ARM Ltd. Versatile family"
376 select ARCH_WANT_OPTIONAL_GPIOLIB
378 select ARM_TIMER_SP804
381 select GENERIC_CLOCKEVENTS
382 select HAVE_MACH_CLKDEV
384 select PLAT_VERSATILE
385 select PLAT_VERSATILE_CLOCK
386 select PLAT_VERSATILE_SCHED_CLOCK
387 select VERSATILE_FPGA_IRQ
389 This enables support for ARM Ltd Versatile board.
392 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
393 select ARCH_REQUIRE_GPIOLIB
398 select GENERIC_CLOCKEVENTS
402 Support for Cirrus Logic 711x/721x/731x based boards.
405 bool "Cortina Systems Gemini"
406 select ARCH_REQUIRE_GPIOLIB
409 select GENERIC_CLOCKEVENTS
411 Support for the Cortina Systems Gemini family SoCs
415 select ARCH_USES_GETTIMEOFFSET
418 select NEED_MACH_IO_H
419 select NEED_MACH_MEMORY_H
422 This is an evaluation board for the StrongARM processor available
423 from Digital. It has limited hardware on-board, including an
424 Ethernet interface, two PCMCIA sockets, two serial ports and a
429 select ARCH_HAS_HOLES_MEMORYMODEL
430 select ARCH_REQUIRE_GPIOLIB
432 select ARM_PATCH_PHYS_VIRT
438 select GENERIC_CLOCKEVENTS
440 This enables support for the Cirrus EP93xx series of CPUs.
442 config ARCH_FOOTBRIDGE
446 select GENERIC_CLOCKEVENTS
448 select NEED_MACH_IO_H if !MMU
449 select NEED_MACH_MEMORY_H
451 Support for systems based on the DC21285 companion chip
452 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
455 bool "Hilscher NetX based"
459 select GENERIC_CLOCKEVENTS
461 This enables support for systems based on the Hilscher NetX Soc
467 select NEED_MACH_MEMORY_H
468 select NEED_RET_TO_USER
474 Support for Intel's IOP13XX (XScale) family of processors.
479 select ARCH_REQUIRE_GPIOLIB
482 select NEED_RET_TO_USER
486 Support for Intel's 80219 and IOP32X (XScale) family of
492 select ARCH_REQUIRE_GPIOLIB
495 select NEED_RET_TO_USER
499 Support for Intel's IOP33X (XScale) family of processors.
504 select ARCH_HAS_DMA_SET_COHERENT_MASK
505 select ARCH_REQUIRE_GPIOLIB
506 select ARCH_SUPPORTS_BIG_ENDIAN
509 select DMABOUNCE if PCI
510 select GENERIC_CLOCKEVENTS
511 select MIGHT_HAVE_PCI
512 select NEED_MACH_IO_H
513 select USB_EHCI_BIG_ENDIAN_DESC
514 select USB_EHCI_BIG_ENDIAN_MMIO
516 Support for Intel's IXP4XX (XScale) family of processors.
520 select ARCH_REQUIRE_GPIOLIB
522 select GENERIC_CLOCKEVENTS
523 select MIGHT_HAVE_PCI
527 select PLAT_ORION_LEGACY
529 Support for the Marvell Dove SoC 88AP510
532 bool "Marvell MV78xx0"
533 select ARCH_REQUIRE_GPIOLIB
535 select GENERIC_CLOCKEVENTS
538 select PLAT_ORION_LEGACY
540 Support for the following Marvell MV78xx0 series SoCs:
546 select ARCH_REQUIRE_GPIOLIB
548 select GENERIC_CLOCKEVENTS
551 select PLAT_ORION_LEGACY
552 select MULTI_IRQ_HANDLER
554 Support for the following Marvell Orion 5x series SoCs:
555 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
556 Orion-2 (5281), Orion-1-90 (6183).
559 bool "Marvell PXA168/910/MMP2"
561 select ARCH_REQUIRE_GPIOLIB
563 select GENERIC_ALLOCATOR
564 select GENERIC_CLOCKEVENTS
567 select MULTI_IRQ_HANDLER
572 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
575 bool "Micrel/Kendin KS8695"
576 select ARCH_REQUIRE_GPIOLIB
579 select GENERIC_CLOCKEVENTS
580 select NEED_MACH_MEMORY_H
582 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
583 System-on-Chip devices.
586 bool "Nuvoton W90X900 CPU"
587 select ARCH_REQUIRE_GPIOLIB
591 select GENERIC_CLOCKEVENTS
593 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
594 At present, the w90x900 has been renamed nuc900, regarding
595 the ARM series product line, you can login the following
596 link address to know more.
598 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
599 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
603 select ARCH_REQUIRE_GPIOLIB
608 select GENERIC_CLOCKEVENTS
612 Support for the NXP LPC32XX family of processors
615 bool "PXA2xx/PXA3xx-based"
618 select ARCH_REQUIRE_GPIOLIB
619 select ARM_CPU_SUSPEND if PM
625 select GENERIC_CLOCKEVENTS
629 select MULTI_IRQ_HANDLER
633 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
639 select ARCH_MAY_HAVE_PC_FDC
640 select ARCH_SPARSEMEM_ENABLE
641 select ARCH_USES_GETTIMEOFFSET
645 select HAVE_PATA_PLATFORM
647 select NEED_MACH_IO_H
648 select NEED_MACH_MEMORY_H
652 On the Acorn Risc-PC, Linux can support the internal IDE disk and
653 CD-ROM interface, serial and parallel port, and the floppy drive.
658 select ARCH_REQUIRE_GPIOLIB
659 select ARCH_SPARSEMEM_ENABLE
664 select GENERIC_CLOCKEVENTS
668 select MULTI_IRQ_HANDLER
669 select NEED_MACH_MEMORY_H
672 Support for StrongARM 11x0 based boards.
675 bool "Samsung S3C24XX SoCs"
676 select ARCH_REQUIRE_GPIOLIB
679 select CLKSRC_SAMSUNG_PWM
680 select GENERIC_CLOCKEVENTS
682 select HAVE_S3C2410_I2C if I2C
683 select HAVE_S3C2410_WATCHDOG if WATCHDOG
684 select HAVE_S3C_RTC if RTC_CLASS
685 select MULTI_IRQ_HANDLER
686 select NEED_MACH_IO_H
689 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
690 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
691 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
692 Samsung SMDK2410 development board (and derivatives).
695 bool "Samsung S3C64XX"
696 select ARCH_REQUIRE_GPIOLIB
701 select CLKSRC_SAMSUNG_PWM
702 select COMMON_CLK_SAMSUNG
704 select GENERIC_CLOCKEVENTS
706 select HAVE_S3C2410_I2C if I2C
707 select HAVE_S3C2410_WATCHDOG if WATCHDOG
711 select PM_GENERIC_DOMAINS if PM
713 select S3C_GPIO_TRACK
715 select SAMSUNG_WAKEMASK
716 select SAMSUNG_WDT_RESET
718 Samsung S3C64XX series based systems
722 select ARCH_HAS_HOLES_MEMORYMODEL
723 select ARCH_REQUIRE_GPIOLIB
725 select GENERIC_ALLOCATOR
726 select GENERIC_CLOCKEVENTS
727 select GENERIC_IRQ_CHIP
732 Support for TI's DaVinci platform.
737 select ARCH_HAS_HOLES_MEMORYMODEL
739 select ARCH_REQUIRE_GPIOLIB
742 select GENERIC_CLOCKEVENTS
743 select GENERIC_IRQ_CHIP
746 select MULTI_IRQ_HANDLER
747 select NEED_MACH_IO_H if PCCARD
748 select NEED_MACH_MEMORY_H
751 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
755 menu "Multiple platform selection"
756 depends on ARCH_MULTIPLATFORM
758 comment "CPU Core family selection"
761 bool "ARMv4 based platforms (FA526)"
762 depends on !ARCH_MULTI_V6_V7
763 select ARCH_MULTI_V4_V5
766 config ARCH_MULTI_V4T
767 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
768 depends on !ARCH_MULTI_V6_V7
769 select ARCH_MULTI_V4_V5
770 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
771 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
772 CPU_ARM925T || CPU_ARM940T)
775 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
776 depends on !ARCH_MULTI_V6_V7
777 select ARCH_MULTI_V4_V5
778 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
779 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
780 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
782 config ARCH_MULTI_V4_V5
786 bool "ARMv6 based platforms (ARM11)"
787 select ARCH_MULTI_V6_V7
791 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
793 select ARCH_MULTI_V6_V7
797 config ARCH_MULTI_V6_V7
799 select MIGHT_HAVE_CACHE_L2X0
801 config ARCH_MULTI_CPU_AUTO
802 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
808 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
813 select HAVE_ARM_ARCH_TIMER
816 # This is sorted alphabetically by mach-* pathname. However, plat-*
817 # Kconfigs may be included either alphabetically (according to the
818 # plat- suffix) or along side the corresponding mach-* source.
820 source "arch/arm/mach-mvebu/Kconfig"
822 source "arch/arm/mach-alpine/Kconfig"
824 source "arch/arm/mach-asm9260/Kconfig"
826 source "arch/arm/mach-at91/Kconfig"
828 source "arch/arm/mach-axxia/Kconfig"
830 source "arch/arm/mach-bcm/Kconfig"
832 source "arch/arm/mach-berlin/Kconfig"
834 source "arch/arm/mach-clps711x/Kconfig"
836 source "arch/arm/mach-cns3xxx/Kconfig"
838 source "arch/arm/mach-davinci/Kconfig"
840 source "arch/arm/mach-digicolor/Kconfig"
842 source "arch/arm/mach-dove/Kconfig"
844 source "arch/arm/mach-ep93xx/Kconfig"
846 source "arch/arm/mach-footbridge/Kconfig"
848 source "arch/arm/mach-gemini/Kconfig"
850 source "arch/arm/mach-highbank/Kconfig"
852 source "arch/arm/mach-hisi/Kconfig"
854 source "arch/arm/mach-integrator/Kconfig"
856 source "arch/arm/mach-iop32x/Kconfig"
858 source "arch/arm/mach-iop33x/Kconfig"
860 source "arch/arm/mach-iop13xx/Kconfig"
862 source "arch/arm/mach-ixp4xx/Kconfig"
864 source "arch/arm/mach-keystone/Kconfig"
866 source "arch/arm/mach-ks8695/Kconfig"
868 source "arch/arm/mach-meson/Kconfig"
870 source "arch/arm/mach-moxart/Kconfig"
872 source "arch/arm/mach-mv78xx0/Kconfig"
874 source "arch/arm/mach-imx/Kconfig"
876 source "arch/arm/mach-mediatek/Kconfig"
878 source "arch/arm/mach-mxs/Kconfig"
880 source "arch/arm/mach-netx/Kconfig"
882 source "arch/arm/mach-nomadik/Kconfig"
884 source "arch/arm/mach-nspire/Kconfig"
886 source "arch/arm/plat-omap/Kconfig"
888 source "arch/arm/mach-omap1/Kconfig"
890 source "arch/arm/mach-omap2/Kconfig"
892 source "arch/arm/mach-orion5x/Kconfig"
894 source "arch/arm/mach-picoxcell/Kconfig"
896 source "arch/arm/mach-pxa/Kconfig"
897 source "arch/arm/plat-pxa/Kconfig"
899 source "arch/arm/mach-mmp/Kconfig"
901 source "arch/arm/mach-qcom/Kconfig"
903 source "arch/arm/mach-realview/Kconfig"
905 source "arch/arm/mach-rockchip/Kconfig"
907 source "arch/arm/mach-sa1100/Kconfig"
909 source "arch/arm/mach-socfpga/Kconfig"
911 source "arch/arm/mach-spear/Kconfig"
913 source "arch/arm/mach-sti/Kconfig"
915 source "arch/arm/mach-s3c24xx/Kconfig"
917 source "arch/arm/mach-s3c64xx/Kconfig"
919 source "arch/arm/mach-s5pv210/Kconfig"
921 source "arch/arm/mach-exynos/Kconfig"
922 source "arch/arm/plat-samsung/Kconfig"
924 source "arch/arm/mach-shmobile/Kconfig"
926 source "arch/arm/mach-sunxi/Kconfig"
928 source "arch/arm/mach-prima2/Kconfig"
930 source "arch/arm/mach-tegra/Kconfig"
932 source "arch/arm/mach-u300/Kconfig"
934 source "arch/arm/mach-uniphier/Kconfig"
936 source "arch/arm/mach-ux500/Kconfig"
938 source "arch/arm/mach-versatile/Kconfig"
940 source "arch/arm/mach-vexpress/Kconfig"
941 source "arch/arm/plat-versatile/Kconfig"
943 source "arch/arm/mach-vt8500/Kconfig"
945 source "arch/arm/mach-w90x900/Kconfig"
947 source "arch/arm/mach-zx/Kconfig"
949 source "arch/arm/mach-zynq/Kconfig"
951 # ARMv7-M architecture
953 bool "Energy Micro efm32"
954 depends on ARM_SINGLE_ARMV7M
955 select ARCH_REQUIRE_GPIOLIB
957 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
961 bool "NXP LPC18xx/LPC43xx"
962 depends on ARM_SINGLE_ARMV7M
963 select ARCH_HAS_RESET_CONTROLLER
965 select CLKSRC_LPC32XX
968 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
969 high performance microcontrollers.
972 bool "STMicrolectronics STM32"
973 depends on ARM_SINGLE_ARMV7M
974 select ARCH_HAS_RESET_CONTROLLER
975 select ARMV7M_SYSTICK
977 select RESET_CONTROLLER
979 Support for STMicroelectronics STM32 processors.
981 # Definitions to make life easier
987 select GENERIC_CLOCKEVENTS
993 select GENERIC_IRQ_CHIP
996 config PLAT_ORION_LEGACY
1003 config PLAT_VERSATILE
1006 source "arch/arm/firmware/Kconfig"
1008 source arch/arm/mm/Kconfig
1011 bool "Enable iWMMXt support"
1012 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1013 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1015 Enable support for iWMMXt context switching at run time if
1016 running on a CPU that supports it.
1018 config MULTI_IRQ_HANDLER
1021 Allow each machine to specify it's own IRQ handler at run time.
1024 source "arch/arm/Kconfig-nommu"
1027 config PJ4B_ERRATA_4742
1028 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1029 depends on CPU_PJ4B && MACH_ARMADA_370
1032 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1033 Event (WFE) IDLE states, a specific timing sensitivity exists between
1034 the retiring WFI/WFE instructions and the newly issued subsequent
1035 instructions. This sensitivity can result in a CPU hang scenario.
1037 The software must insert either a Data Synchronization Barrier (DSB)
1038 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1041 config ARM_ERRATA_326103
1042 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1045 Executing a SWP instruction to read-only memory does not set bit 11
1046 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1047 treat the access as a read, preventing a COW from occurring and
1048 causing the faulting task to livelock.
1050 config ARM_ERRATA_411920
1051 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1052 depends on CPU_V6 || CPU_V6K
1054 Invalidation of the Instruction Cache operation can
1055 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1056 It does not affect the MPCore. This option enables the ARM Ltd.
1057 recommended workaround.
1059 config ARM_ERRATA_430973
1060 bool "ARM errata: Stale prediction on replaced interworking branch"
1063 This option enables the workaround for the 430973 Cortex-A8
1064 r1p* erratum. If a code sequence containing an ARM/Thumb
1065 interworking branch is replaced with another code sequence at the
1066 same virtual address, whether due to self-modifying code or virtual
1067 to physical address re-mapping, Cortex-A8 does not recover from the
1068 stale interworking branch prediction. This results in Cortex-A8
1069 executing the new code sequence in the incorrect ARM or Thumb state.
1070 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1071 and also flushes the branch target cache at every context switch.
1072 Note that setting specific bits in the ACTLR register may not be
1073 available in non-secure mode.
1075 config ARM_ERRATA_458693
1076 bool "ARM errata: Processor deadlock when a false hazard is created"
1078 depends on !ARCH_MULTIPLATFORM
1080 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1081 erratum. For very specific sequences of memory operations, it is
1082 possible for a hazard condition intended for a cache line to instead
1083 be incorrectly associated with a different cache line. This false
1084 hazard might then cause a processor deadlock. The workaround enables
1085 the L1 caching of the NEON accesses and disables the PLD instruction
1086 in the ACTLR register. Note that setting specific bits in the ACTLR
1087 register may not be available in non-secure mode.
1089 config ARM_ERRATA_460075
1090 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1092 depends on !ARCH_MULTIPLATFORM
1094 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1095 erratum. Any asynchronous access to the L2 cache may encounter a
1096 situation in which recent store transactions to the L2 cache are lost
1097 and overwritten with stale memory contents from external memory. The
1098 workaround disables the write-allocate mode for the L2 cache via the
1099 ACTLR register. Note that setting specific bits in the ACTLR register
1100 may not be available in non-secure mode.
1102 config ARM_ERRATA_742230
1103 bool "ARM errata: DMB operation may be faulty"
1104 depends on CPU_V7 && SMP
1105 depends on !ARCH_MULTIPLATFORM
1107 This option enables the workaround for the 742230 Cortex-A9
1108 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1109 between two write operations may not ensure the correct visibility
1110 ordering of the two writes. This workaround sets a specific bit in
1111 the diagnostic register of the Cortex-A9 which causes the DMB
1112 instruction to behave as a DSB, ensuring the correct behaviour of
1115 config ARM_ERRATA_742231
1116 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1117 depends on CPU_V7 && SMP
1118 depends on !ARCH_MULTIPLATFORM
1120 This option enables the workaround for the 742231 Cortex-A9
1121 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1122 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1123 accessing some data located in the same cache line, may get corrupted
1124 data due to bad handling of the address hazard when the line gets
1125 replaced from one of the CPUs at the same time as another CPU is
1126 accessing it. This workaround sets specific bits in the diagnostic
1127 register of the Cortex-A9 which reduces the linefill issuing
1128 capabilities of the processor.
1130 config ARM_ERRATA_643719
1131 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1132 depends on CPU_V7 && SMP
1135 This option enables the workaround for the 643719 Cortex-A9 (prior to
1136 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1137 register returns zero when it should return one. The workaround
1138 corrects this value, ensuring cache maintenance operations which use
1139 it behave as intended and avoiding data corruption.
1141 config ARM_ERRATA_720789
1142 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1145 This option enables the workaround for the 720789 Cortex-A9 (prior to
1146 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1147 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1148 As a consequence of this erratum, some TLB entries which should be
1149 invalidated are not, resulting in an incoherency in the system page
1150 tables. The workaround changes the TLB flushing routines to invalidate
1151 entries regardless of the ASID.
1153 config ARM_ERRATA_743622
1154 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1156 depends on !ARCH_MULTIPLATFORM
1158 This option enables the workaround for the 743622 Cortex-A9
1159 (r2p*) erratum. Under very rare conditions, a faulty
1160 optimisation in the Cortex-A9 Store Buffer may lead to data
1161 corruption. This workaround sets a specific bit in the diagnostic
1162 register of the Cortex-A9 which disables the Store Buffer
1163 optimisation, preventing the defect from occurring. This has no
1164 visible impact on the overall performance or power consumption of the
1167 config ARM_ERRATA_751472
1168 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1170 depends on !ARCH_MULTIPLATFORM
1172 This option enables the workaround for the 751472 Cortex-A9 (prior
1173 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1174 completion of a following broadcasted operation if the second
1175 operation is received by a CPU before the ICIALLUIS has completed,
1176 potentially leading to corrupted entries in the cache or TLB.
1178 config ARM_ERRATA_754322
1179 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1182 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1183 r3p*) erratum. A speculative memory access may cause a page table walk
1184 which starts prior to an ASID switch but completes afterwards. This
1185 can populate the micro-TLB with a stale entry which may be hit with
1186 the new ASID. This workaround places two dsb instructions in the mm
1187 switching code so that no page table walks can cross the ASID switch.
1189 config ARM_ERRATA_754327
1190 bool "ARM errata: no automatic Store Buffer drain"
1191 depends on CPU_V7 && SMP
1193 This option enables the workaround for the 754327 Cortex-A9 (prior to
1194 r2p0) erratum. The Store Buffer does not have any automatic draining
1195 mechanism and therefore a livelock may occur if an external agent
1196 continuously polls a memory location waiting to observe an update.
1197 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1198 written polling loops from denying visibility of updates to memory.
1200 config ARM_ERRATA_364296
1201 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1204 This options enables the workaround for the 364296 ARM1136
1205 r0p2 erratum (possible cache data corruption with
1206 hit-under-miss enabled). It sets the undocumented bit 31 in
1207 the auxiliary control register and the FI bit in the control
1208 register, thus disabling hit-under-miss without putting the
1209 processor into full low interrupt latency mode. ARM11MPCore
1212 config ARM_ERRATA_764369
1213 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1214 depends on CPU_V7 && SMP
1216 This option enables the workaround for erratum 764369
1217 affecting Cortex-A9 MPCore with two or more processors (all
1218 current revisions). Under certain timing circumstances, a data
1219 cache line maintenance operation by MVA targeting an Inner
1220 Shareable memory region may fail to proceed up to either the
1221 Point of Coherency or to the Point of Unification of the
1222 system. This workaround adds a DSB instruction before the
1223 relevant cache maintenance functions and sets a specific bit
1224 in the diagnostic control register of the SCU.
1226 config ARM_ERRATA_775420
1227 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1230 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1231 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1232 operation aborts with MMU exception, it might cause the processor
1233 to deadlock. This workaround puts DSB before executing ISB if
1234 an abort may occur on cache maintenance.
1236 config ARM_ERRATA_798181
1237 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1238 depends on CPU_V7 && SMP
1240 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1241 adequately shooting down all use of the old entries. This
1242 option enables the Linux kernel workaround for this erratum
1243 which sends an IPI to the CPUs that are running the same ASID
1244 as the one being invalidated.
1246 config ARM_ERRATA_773022
1247 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1250 This option enables the workaround for the 773022 Cortex-A15
1251 (up to r0p4) erratum. In certain rare sequences of code, the
1252 loop buffer may deliver incorrect instructions. This
1253 workaround disables the loop buffer to avoid the erratum.
1257 source "arch/arm/common/Kconfig"
1264 Find out whether you have ISA slots on your motherboard. ISA is the
1265 name of a bus system, i.e. the way the CPU talks to the other stuff
1266 inside your box. Other bus systems are PCI, EISA, MicroChannel
1267 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1268 newer boards don't support it. If you have ISA, say Y, otherwise N.
1270 # Select ISA DMA controller support
1275 # Select ISA DMA interface
1280 bool "PCI support" if MIGHT_HAVE_PCI
1282 Find out whether you have a PCI motherboard. PCI is the name of a
1283 bus system, i.e. the way the CPU talks to the other stuff inside
1284 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1285 VESA. If you have PCI, say Y, otherwise N.
1291 config PCI_DOMAINS_GENERIC
1292 def_bool PCI_DOMAINS
1294 config PCI_NANOENGINE
1295 bool "BSE nanoEngine PCI support"
1296 depends on SA1100_NANOENGINE
1298 Enable PCI on the BSE nanoEngine board.
1303 config PCI_HOST_ITE8152
1305 depends on PCI && MACH_ARMCORE
1309 source "drivers/pci/Kconfig"
1310 source "drivers/pci/pcie/Kconfig"
1312 source "drivers/pcmcia/Kconfig"
1316 menu "Kernel Features"
1321 This option should be selected by machines which have an SMP-
1324 The only effect of this option is to make the SMP-related
1325 options available to the user for configuration.
1328 bool "Symmetric Multi-Processing"
1329 depends on CPU_V6K || CPU_V7
1330 depends on GENERIC_CLOCKEVENTS
1332 depends on MMU || ARM_MPU
1335 This enables support for systems with more than one CPU. If you have
1336 a system with only one CPU, say N. If you have a system with more
1337 than one CPU, say Y.
1339 If you say N here, the kernel will run on uni- and multiprocessor
1340 machines, but will use only one CPU of a multiprocessor machine. If
1341 you say Y here, the kernel will run on many, but not all,
1342 uniprocessor machines. On a uniprocessor machine, the kernel
1343 will run faster if you say N here.
1345 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1346 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1347 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1349 If you don't know what to do here, say N.
1352 bool "Allow booting SMP kernel on uniprocessor systems"
1353 depends on SMP && !XIP_KERNEL && MMU
1356 SMP kernels contain instructions which fail on non-SMP processors.
1357 Enabling this option allows the kernel to modify itself to make
1358 these instructions safe. Disabling it allows about 1K of space
1361 If you don't know what to do here, say Y.
1363 config ARM_CPU_TOPOLOGY
1364 bool "Support cpu topology definition"
1365 depends on SMP && CPU_V7
1368 Support ARM cpu topology definition. The MPIDR register defines
1369 affinity between processors which is then used to describe the cpu
1370 topology of an ARM System.
1373 bool "Multi-core scheduler support"
1374 depends on ARM_CPU_TOPOLOGY
1376 Multi-core scheduler support improves the CPU scheduler's decision
1377 making when dealing with multi-core CPU chips at a cost of slightly
1378 increased overhead in some places. If unsure say N here.
1381 bool "SMT scheduler support"
1382 depends on ARM_CPU_TOPOLOGY
1384 Improves the CPU scheduler's decision making when dealing with
1385 MultiThreading at a cost of slightly increased overhead in some
1386 places. If unsure say N here.
1391 This option enables support for the ARM system coherency unit
1393 config HAVE_ARM_ARCH_TIMER
1394 bool "Architected timer support"
1396 select ARM_ARCH_TIMER
1397 select GENERIC_CLOCKEVENTS
1399 This option enables support for the ARM architected timer
1403 select CLKSRC_OF if OF
1405 This options enables support for the ARM timer and watchdog unit
1408 bool "Multi-Cluster Power Management"
1409 depends on CPU_V7 && SMP
1411 This option provides the common power management infrastructure
1412 for (multi-)cluster based systems, such as big.LITTLE based
1415 config MCPM_QUAD_CLUSTER
1419 To avoid wasting resources unnecessarily, MCPM only supports up
1420 to 2 clusters by default.
1421 Platforms with 3 or 4 clusters that use MCPM must select this
1422 option to allow the additional clusters to be managed.
1425 bool "big.LITTLE support (Experimental)"
1426 depends on CPU_V7 && SMP
1429 This option enables support selections for the big.LITTLE
1430 system architecture.
1433 bool "big.LITTLE switcher support"
1434 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1435 select ARM_CPU_SUSPEND
1438 The big.LITTLE "switcher" provides the core functionality to
1439 transparently handle transition between a cluster of A15's
1440 and a cluster of A7's in a big.LITTLE system.
1442 config BL_SWITCHER_DUMMY_IF
1443 tristate "Simple big.LITTLE switcher user interface"
1444 depends on BL_SWITCHER && DEBUG_KERNEL
1446 This is a simple and dummy char dev interface to control
1447 the big.LITTLE switcher core code. It is meant for
1448 debugging purposes only.
1451 prompt "Memory split"
1455 Select the desired split between kernel and user memory.
1457 If you are not absolutely sure what you are doing, leave this
1461 bool "3G/1G user/kernel split"
1462 config VMSPLIT_3G_OPT
1463 bool "3G/1G user/kernel split (for full 1G low memory)"
1465 bool "2G/2G user/kernel split"
1467 bool "1G/3G user/kernel split"
1472 default PHYS_OFFSET if !MMU
1473 default 0x40000000 if VMSPLIT_1G
1474 default 0x80000000 if VMSPLIT_2G
1475 default 0xB0000000 if VMSPLIT_3G_OPT
1479 int "Maximum number of CPUs (2-32)"
1485 bool "Support for hot-pluggable CPUs"
1488 Say Y here to experiment with turning CPUs off and on. CPUs
1489 can be controlled through /sys/devices/system/cpu.
1492 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1496 Say Y here if you want Linux to communicate with system firmware
1497 implementing the PSCI specification for CPU-centric power
1498 management operations described in ARM document number ARM DEN
1499 0022A ("Power State Coordination Interface System Software on
1502 # The GPIO number here must be sorted by descending number. In case of
1503 # a multiplatform kernel, we just want the highest value required by the
1504 # selected platforms.
1507 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1509 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1510 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1511 default 416 if ARCH_SUNXI
1512 default 392 if ARCH_U8500
1513 default 352 if ARCH_VT8500
1514 default 288 if ARCH_ROCKCHIP
1515 default 264 if MACH_H4700
1518 Maximum number of GPIOs in the system.
1520 If unsure, leave the default value.
1522 source kernel/Kconfig.preempt
1526 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1527 ARCH_S5PV210 || ARCH_EXYNOS4
1528 default 128 if SOC_AT91RM9200
1532 depends on HZ_FIXED = 0
1533 prompt "Timer frequency"
1557 default HZ_FIXED if HZ_FIXED != 0
1558 default 100 if HZ_100
1559 default 200 if HZ_200
1560 default 250 if HZ_250
1561 default 300 if HZ_300
1562 default 500 if HZ_500
1566 def_bool HIGH_RES_TIMERS
1568 config THUMB2_KERNEL
1569 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1570 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1571 default y if CPU_THUMBONLY
1573 select ARM_ASM_UNIFIED
1576 By enabling this option, the kernel will be compiled in
1577 Thumb-2 mode. A compiler/assembler that understand the unified
1578 ARM-Thumb syntax is needed.
1582 config THUMB2_AVOID_R_ARM_THM_JUMP11
1583 bool "Work around buggy Thumb-2 short branch relocations in gas"
1584 depends on THUMB2_KERNEL && MODULES
1587 Various binutils versions can resolve Thumb-2 branches to
1588 locally-defined, preemptible global symbols as short-range "b.n"
1589 branch instructions.
1591 This is a problem, because there's no guarantee the final
1592 destination of the symbol, or any candidate locations for a
1593 trampoline, are within range of the branch. For this reason, the
1594 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1595 relocation in modules at all, and it makes little sense to add
1598 The symptom is that the kernel fails with an "unsupported
1599 relocation" error when loading some modules.
1601 Until fixed tools are available, passing
1602 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1603 code which hits this problem, at the cost of a bit of extra runtime
1604 stack usage in some cases.
1606 The problem is described in more detail at:
1607 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1609 Only Thumb-2 kernels are affected.
1611 Unless you are sure your tools don't have this problem, say Y.
1613 config ARM_ASM_UNIFIED
1617 bool "Use the ARM EABI to compile the kernel"
1619 This option allows for the kernel to be compiled using the latest
1620 ARM ABI (aka EABI). This is only useful if you are using a user
1621 space environment that is also compiled with EABI.
1623 Since there are major incompatibilities between the legacy ABI and
1624 EABI, especially with regard to structure member alignment, this
1625 option also changes the kernel syscall calling convention to
1626 disambiguate both ABIs and allow for backward compatibility support
1627 (selected with CONFIG_OABI_COMPAT).
1629 To use this you need GCC version 4.0.0 or later.
1632 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1633 depends on AEABI && !THUMB2_KERNEL
1635 This option preserves the old syscall interface along with the
1636 new (ARM EABI) one. It also provides a compatibility layer to
1637 intercept syscalls that have structure arguments which layout
1638 in memory differs between the legacy ABI and the new ARM EABI
1639 (only for non "thumb" binaries). This option adds a tiny
1640 overhead to all syscalls and produces a slightly larger kernel.
1642 The seccomp filter system will not be available when this is
1643 selected, since there is no way yet to sensibly distinguish
1644 between calling conventions during filtering.
1646 If you know you'll be using only pure EABI user space then you
1647 can say N here. If this option is not selected and you attempt
1648 to execute a legacy ABI binary then the result will be
1649 UNPREDICTABLE (in fact it can be predicted that it won't work
1650 at all). If in doubt say N.
1652 config ARCH_HAS_HOLES_MEMORYMODEL
1655 config ARCH_SPARSEMEM_ENABLE
1658 config ARCH_SPARSEMEM_DEFAULT
1659 def_bool ARCH_SPARSEMEM_ENABLE
1661 config ARCH_SELECT_MEMORY_MODEL
1662 def_bool ARCH_SPARSEMEM_ENABLE
1664 config HAVE_ARCH_PFN_VALID
1665 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1667 config HAVE_GENERIC_RCU_GUP
1672 bool "High Memory Support"
1675 The address space of ARM processors is only 4 Gigabytes large
1676 and it has to accommodate user address space, kernel address
1677 space as well as some memory mapped IO. That means that, if you
1678 have a large amount of physical memory and/or IO, not all of the
1679 memory can be "permanently mapped" by the kernel. The physical
1680 memory that is not permanently mapped is called "high memory".
1682 Depending on the selected kernel/user memory split, minimum
1683 vmalloc space and actual amount of RAM, you may not need this
1684 option which should result in a slightly faster kernel.
1689 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1693 The VM uses one page of physical memory for each page table.
1694 For systems with a lot of processes, this can use a lot of
1695 precious low memory, eventually leading to low memory being
1696 consumed by page tables. Setting this option will allow
1697 user-space 2nd level page tables to reside in high memory.
1699 config CPU_SW_DOMAIN_PAN
1700 bool "Enable use of CPU domains to implement privileged no-access"
1701 depends on MMU && !ARM_LPAE
1704 Increase kernel security by ensuring that normal kernel accesses
1705 are unable to access userspace addresses. This can help prevent
1706 use-after-free bugs becoming an exploitable privilege escalation
1707 by ensuring that magic values (such as LIST_POISON) will always
1708 fault when dereferenced.
1710 CPUs with low-vector mappings use a best-efforts implementation.
1711 Their lower 1MB needs to remain accessible for the vectors, but
1712 the remainder of userspace will become appropriately inaccessible.
1714 config HW_PERF_EVENTS
1718 config SYS_SUPPORTS_HUGETLBFS
1722 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1726 config ARCH_WANT_GENERAL_HUGETLB
1729 config ARM_MODULE_PLTS
1730 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1733 Allocate PLTs when loading modules so that jumps and calls whose
1734 targets are too far away for their relative offsets to be encoded
1735 in the instructions themselves can be bounced via veneers in the
1736 module's PLT. This allows modules to be allocated in the generic
1737 vmalloc area after the dedicated module memory area has been
1738 exhausted. The modules will use slightly more memory, but after
1739 rounding up to page size, the actual memory footprint is usually
1742 Say y if you are getting out of memory errors while loading modules
1746 config FORCE_MAX_ZONEORDER
1747 int "Maximum zone order"
1748 default "12" if SOC_AM33XX
1749 default "9" if SA1111 || ARCH_EFM32
1752 The kernel memory allocator divides physically contiguous memory
1753 blocks into "zones", where each zone is a power of two number of
1754 pages. This option selects the largest power of two that the kernel
1755 keeps in the memory allocator. If you need to allocate very large
1756 blocks of physically contiguous memory, then you may need to
1757 increase this value.
1759 This config option is actually maximum order plus one. For example,
1760 a value of 11 means that the largest free memory block is 2^10 pages.
1762 config ALIGNMENT_TRAP
1764 depends on CPU_CP15_MMU
1765 default y if !ARCH_EBSA110
1766 select HAVE_PROC_CPU if PROC_FS
1768 ARM processors cannot fetch/store information which is not
1769 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1770 address divisible by 4. On 32-bit ARM processors, these non-aligned
1771 fetch/store instructions will be emulated in software if you say
1772 here, which has a severe performance impact. This is necessary for
1773 correct operation of some network protocols. With an IP-only
1774 configuration it is safe to say N, otherwise say Y.
1776 config UACCESS_WITH_MEMCPY
1777 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1779 default y if CPU_FEROCEON
1781 Implement faster copy_to_user and clear_user methods for CPU
1782 cores where a 8-word STM instruction give significantly higher
1783 memory write throughput than a sequence of individual 32bit stores.
1785 A possible side effect is a slight increase in scheduling latency
1786 between threads sharing the same address space if they invoke
1787 such copy operations with large buffers.
1789 However, if the CPU data cache is using a write-allocate mode,
1790 this option is unlikely to provide any performance gain.
1794 prompt "Enable seccomp to safely compute untrusted bytecode"
1796 This kernel feature is useful for number crunching applications
1797 that may need to compute untrusted bytecode during their
1798 execution. By using pipes or other transports made available to
1799 the process as file descriptors supporting the read/write
1800 syscalls, it's possible to isolate those applications in
1801 their own address space using seccomp. Once seccomp is
1802 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1803 and the task is only allowed to execute a few safe syscalls
1804 defined by each seccomp mode.
1817 bool "Xen guest support on ARM"
1818 depends on ARM && AEABI && OF
1819 depends on CPU_V7 && !CPU_V6
1820 depends on !GENERIC_ATOMIC64
1822 select ARCH_DMA_ADDR_T_64BIT
1826 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1828 config ARM_FLUSH_CONSOLE_ON_RESTART
1829 bool "Force flush the console on restart"
1831 If the console is locked while the system is rebooted, the messages
1832 in the temporary logbuffer would not have propogated to all the
1833 console drivers. This option forces the console lock to be
1834 released if it failed to be acquired, which will cause all the
1835 pending messages to be flushed.
1842 bool "Flattened Device Tree support"
1846 Include support for flattened device tree machine descriptions.
1849 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1852 This is the traditional way of passing data to the kernel at boot
1853 time. If you are solely relying on the flattened device tree (or
1854 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1855 to remove ATAGS support from your kernel binary. If unsure,
1858 config DEPRECATED_PARAM_STRUCT
1859 bool "Provide old way to pass kernel parameters"
1862 This was deprecated in 2001 and announced to live on for 5 years.
1863 Some old boot loaders still use this way.
1865 config BUILD_ARM_APPENDED_DTB_IMAGE
1866 bool "Build a concatenated zImage/dtb by default"
1869 Enabling this option will cause a concatenated zImage and list of
1870 DTBs to be built by default (instead of a standalone zImage.)
1871 The image will built in arch/arm/boot/zImage-dtb
1873 config BUILD_ARM_APPENDED_DTB_IMAGE_NAMES
1874 string "Default dtb names"
1875 depends on BUILD_ARM_APPENDED_DTB_IMAGE
1877 Space separated list of names of dtbs to append when
1878 building a concatenated zImage-dtb.
1880 # Compressed boot loader in ROM. Yes, we really want to ask about
1881 # TEXT and BSS so we preserve their values in the config files.
1882 config ZBOOT_ROM_TEXT
1883 hex "Compressed ROM boot loader base address"
1886 The physical address at which the ROM-able zImage is to be
1887 placed in the target. Platforms which normally make use of
1888 ROM-able zImage formats normally set this to a suitable
1889 value in their defconfig file.
1891 If ZBOOT_ROM is not enabled, this has no effect.
1893 config ZBOOT_ROM_BSS
1894 hex "Compressed ROM boot loader BSS address"
1897 The base address of an area of read/write memory in the target
1898 for the ROM-able zImage which must be available while the
1899 decompressor is running. It must be large enough to hold the
1900 entire decompressed kernel plus an additional 128 KiB.
1901 Platforms which normally make use of ROM-able zImage formats
1902 normally set this to a suitable value in their defconfig file.
1904 If ZBOOT_ROM is not enabled, this has no effect.
1907 bool "Compressed boot loader in ROM/flash"
1908 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1909 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1911 Say Y here if you intend to execute your compressed kernel image
1912 (zImage) directly from ROM or flash. If unsure, say N.
1914 config ARM_APPENDED_DTB
1915 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1918 With this option, the boot code will look for a device tree binary
1919 (DTB) appended to zImage
1920 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1922 This is meant as a backward compatibility convenience for those
1923 systems with a bootloader that can't be upgraded to accommodate
1924 the documented boot protocol using a device tree.
1926 Beware that there is very little in terms of protection against
1927 this option being confused by leftover garbage in memory that might
1928 look like a DTB header after a reboot if no actual DTB is appended
1929 to zImage. Do not leave this option active in a production kernel
1930 if you don't intend to always append a DTB. Proper passing of the
1931 location into r2 of a bootloader provided DTB is always preferable
1934 config ARM_ATAG_DTB_COMPAT
1935 bool "Supplement the appended DTB with traditional ATAG information"
1936 depends on ARM_APPENDED_DTB
1938 Some old bootloaders can't be updated to a DTB capable one, yet
1939 they provide ATAGs with memory configuration, the ramdisk address,
1940 the kernel cmdline string, etc. Such information is dynamically
1941 provided by the bootloader and can't always be stored in a static
1942 DTB. To allow a device tree enabled kernel to be used with such
1943 bootloaders, this option allows zImage to extract the information
1944 from the ATAG list and store it at run time into the appended DTB.
1947 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1948 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1950 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1951 bool "Use bootloader kernel arguments if available"
1953 Uses the command-line options passed by the boot loader instead of
1954 the device tree bootargs property. If the boot loader doesn't provide
1955 any, the device tree bootargs property will be used.
1957 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1958 bool "Extend with bootloader kernel arguments"
1960 The command-line arguments provided by the boot loader will be
1961 appended to the the device tree bootargs property.
1966 string "Default kernel command string"
1969 On some architectures (EBSA110 and CATS), there is currently no way
1970 for the boot loader to pass arguments to the kernel. For these
1971 architectures, you should supply some command-line options at build
1972 time by entering them here. As a minimum, you should specify the
1973 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1976 prompt "Kernel command line type" if CMDLINE != ""
1977 default CMDLINE_FROM_BOOTLOADER
1980 config CMDLINE_FROM_BOOTLOADER
1981 bool "Use bootloader kernel arguments if available"
1983 Uses the command-line options passed by the boot loader. If
1984 the boot loader doesn't provide any, the default kernel command
1985 string provided in CMDLINE will be used.
1987 config CMDLINE_EXTEND
1988 bool "Extend bootloader kernel arguments"
1990 The command-line arguments provided by the boot loader will be
1991 appended to the default kernel command string.
1993 config CMDLINE_FORCE
1994 bool "Always use the default kernel command string"
1996 Always use the default kernel command string, even if the boot
1997 loader passes other arguments to the kernel.
1998 This is useful if you cannot or don't want to change the
1999 command-line options your boot loader passes to the kernel.
2003 bool "Kernel Execute-In-Place from ROM"
2004 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
2006 Execute-In-Place allows the kernel to run from non-volatile storage
2007 directly addressable by the CPU, such as NOR flash. This saves RAM
2008 space since the text section of the kernel is not loaded from flash
2009 to RAM. Read-write sections, such as the data section and stack,
2010 are still copied to RAM. The XIP kernel is not compressed since
2011 it has to run directly from flash, so it will take more space to
2012 store it. The flash address used to link the kernel object files,
2013 and for storing it, is configuration dependent. Therefore, if you
2014 say Y here, you must know the proper physical address where to
2015 store the kernel image depending on your own flash memory usage.
2017 Also note that the make target becomes "make xipImage" rather than
2018 "make zImage" or "make Image". The final kernel binary to put in
2019 ROM memory will be arch/arm/boot/xipImage.
2023 config XIP_PHYS_ADDR
2024 hex "XIP Kernel Physical Location"
2025 depends on XIP_KERNEL
2026 default "0x00080000"
2028 This is the physical address in your flash memory the kernel will
2029 be linked for and stored to. This address is dependent on your
2033 bool "Kexec system call (EXPERIMENTAL)"
2034 depends on (!SMP || PM_SLEEP_SMP)
2038 kexec is a system call that implements the ability to shutdown your
2039 current kernel, and to start another kernel. It is like a reboot
2040 but it is independent of the system firmware. And like a reboot
2041 you can start any kernel with it, not just Linux.
2043 It is an ongoing process to be certain the hardware in a machine
2044 is properly shutdown, so do not be surprised if this code does not
2045 initially work for you.
2048 bool "Export atags in procfs"
2049 depends on ATAGS && KEXEC
2052 Should the atags used to boot the kernel be exported in an "atags"
2053 file in procfs. Useful with kexec.
2056 bool "Build kdump crash kernel (EXPERIMENTAL)"
2058 Generate crash dump after being started by kexec. This should
2059 be normally only set in special crash dump kernels which are
2060 loaded in the main kernel with kexec-tools into a specially
2061 reserved region and then later executed after a crash by
2062 kdump/kexec. The crash dump kernel must be compiled to a
2063 memory address not used by the main kernel
2065 For more details see Documentation/kdump/kdump.txt
2067 config AUTO_ZRELADDR
2068 bool "Auto calculation of the decompressed kernel image address"
2070 ZRELADDR is the physical address where the decompressed kernel
2071 image will be placed. If AUTO_ZRELADDR is selected, the address
2072 will be determined at run-time by masking the current IP with
2073 0xf8000000. This assumes the zImage being placed in the first 128MB
2074 from start of memory.
2078 menu "CPU Power Management"
2080 source "drivers/cpufreq/Kconfig"
2082 source "drivers/cpuidle/Kconfig"
2086 menu "Floating point emulation"
2088 comment "At least one emulation must be selected"
2091 bool "NWFPE math emulation"
2092 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2094 Say Y to include the NWFPE floating point emulator in the kernel.
2095 This is necessary to run most binaries. Linux does not currently
2096 support floating point hardware so you need to say Y here even if
2097 your machine has an FPA or floating point co-processor podule.
2099 You may say N here if you are going to load the Acorn FPEmulator
2100 early in the bootup.
2103 bool "Support extended precision"
2104 depends on FPE_NWFPE
2106 Say Y to include 80-bit support in the kernel floating-point
2107 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2108 Note that gcc does not generate 80-bit operations by default,
2109 so in most cases this option only enlarges the size of the
2110 floating point emulator without any good reason.
2112 You almost surely want to say N here.
2115 bool "FastFPE math emulation (EXPERIMENTAL)"
2116 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2118 Say Y here to include the FAST floating point emulator in the kernel.
2119 This is an experimental much faster emulator which now also has full
2120 precision for the mantissa. It does not support any exceptions.
2121 It is very simple, and approximately 3-6 times faster than NWFPE.
2123 It should be sufficient for most programs. It may be not suitable
2124 for scientific calculations, but you have to check this for yourself.
2125 If you do not feel you need a faster FP emulation you should better
2129 bool "VFP-format floating point maths"
2130 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2132 Say Y to include VFP support code in the kernel. This is needed
2133 if your hardware includes a VFP unit.
2135 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2136 release notes and additional status information.
2138 Say N if your target does not have VFP hardware.
2146 bool "Advanced SIMD (NEON) Extension support"
2147 depends on VFPv3 && CPU_V7
2149 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2152 config KERNEL_MODE_NEON
2153 bool "Support for NEON in kernel mode"
2154 depends on NEON && AEABI
2156 Say Y to include support for NEON in kernel mode.
2160 menu "Userspace binary formats"
2162 source "fs/Kconfig.binfmt"
2166 menu "Power management options"
2168 source "kernel/power/Kconfig"
2170 config ARCH_SUSPEND_POSSIBLE
2171 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2172 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2175 config ARM_CPU_SUSPEND
2178 config ARCH_HIBERNATION_POSSIBLE
2181 default y if ARCH_SUSPEND_POSSIBLE
2185 source "net/Kconfig"
2187 source "drivers/Kconfig"
2189 source "drivers/firmware/Kconfig"
2193 source "arch/arm/Kconfig.debug"
2195 source "security/Kconfig"
2197 source "crypto/Kconfig"
2199 source "arch/arm/crypto/Kconfig"
2202 source "lib/Kconfig"
2204 source "arch/arm/kvm/Kconfig"