5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if !XIP_KERNEL
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
33 The ARM series is a line of low-power-consumption RISC chip designs
34 licensed by ARM Ltd and targeted at embedded applications and
35 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
36 manufactured, but legacy ARM-based PC hardware remains popular in
37 Europe. There is an ARM Linux project with a web page at
38 <http://www.arm.linux.org.uk/>.
40 config ARM_HAS_SG_CHAIN
49 config SYS_SUPPORTS_APM_EMULATION
52 config HAVE_SCHED_CLOCK
58 config ARCH_USES_GETTIMEOFFSET
62 config GENERIC_CLOCKEVENTS
65 config GENERIC_CLOCKEVENTS_BROADCAST
67 depends on GENERIC_CLOCKEVENTS
76 select GENERIC_ALLOCATOR
87 The Extended Industry Standard Architecture (EISA) bus was
88 developed as an open alternative to the IBM MicroChannel bus.
90 The EISA bus provided some of the features of the IBM MicroChannel
91 bus while maintaining backward compatibility with cards made for
92 the older ISA bus. The EISA bus saw limited use between 1988 and
93 1995 when it was made obsolete by the PCI bus.
95 Say Y here if you are building a kernel for an EISA-based machine.
105 MicroChannel Architecture is found in some IBM PS/2 machines and
106 laptops. It is a bus system similar to PCI or ISA. See
107 <file:Documentation/mca.txt> (and especially the web page given
108 there) before attempting to build an MCA bus kernel.
110 config STACKTRACE_SUPPORT
114 config HAVE_LATENCYTOP_SUPPORT
119 config LOCKDEP_SUPPORT
123 config TRACE_IRQFLAGS_SUPPORT
127 config HARDIRQS_SW_RESEND
131 config GENERIC_IRQ_PROBE
135 config GENERIC_LOCKBREAK
138 depends on SMP && PREEMPT
140 config RWSEM_GENERIC_SPINLOCK
144 config RWSEM_XCHGADD_ALGORITHM
147 config ARCH_HAS_ILOG2_U32
150 config ARCH_HAS_ILOG2_U64
153 config ARCH_HAS_CPUFREQ
156 Internal node to signify that the ARCH has CPUFREQ support
157 and that the relevant menu configurations are displayed for
160 config ARCH_HAS_CPU_IDLE_WAIT
163 config GENERIC_HWEIGHT
167 config GENERIC_CALIBRATE_DELAY
171 config ARCH_MAY_HAVE_PC_FDC
177 config NEED_DMA_MAP_STATE
180 config GENERIC_ISA_DMA
191 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
192 default DRAM_BASE if REMAP_VECTORS_TO_RAM
195 The base address of exception vectors.
197 config ARM_PATCH_PHYS_VIRT
198 bool "Patch physical to virtual translations at runtime" if EMBEDDED
200 depends on !XIP_KERNEL && MMU
201 depends on !ARCH_REALVIEW || !SPARSEMEM
203 Patch phys-to-virt and virt-to-phys translation functions at
204 boot and module load time according to the position of the
205 kernel in system memory.
207 This can only be used with non-XIP MMU kernels where the base
208 of physical memory is at a 16MB boundary.
210 Only disable this option if you know that you do not require
211 this feature (eg, building a kernel for a single machine) and
212 you need to shrink the kernel to the minimal size.
214 config NEED_MACH_MEMORY_H
217 Select this when mach/memory.h is required to provide special
218 definitions for this platform. The need for mach/memory.h should
219 be avoided when possible.
222 hex "Physical address of main memory"
223 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
225 Please provide the physical address corresponding to the
226 location of main memory in your system.
228 source "init/Kconfig"
230 source "kernel/Kconfig.freezer"
235 bool "MMU-based Paged Memory Management Support"
238 Select if you want MMU-based virtualised addressing space
239 support by paged memory management. If unsure, say 'Y'.
242 # The "ARM system type" choice list is ordered alphabetically by option
243 # text. Please add new entries in the option alphabetic order.
246 prompt "ARM system type"
247 default ARCH_VERSATILE
249 config ARCH_INTEGRATOR
250 bool "ARM Ltd. Integrator family"
252 select ARCH_HAS_CPUFREQ
254 select HAVE_MACH_CLKDEV
256 select GENERIC_CLOCKEVENTS
257 select PLAT_VERSATILE
258 select PLAT_VERSATILE_FPGA_IRQ
259 select NEED_MACH_MEMORY_H
261 Support for ARM's Integrator platform.
264 bool "ARM Ltd. RealView family"
267 select HAVE_MACH_CLKDEV
269 select GENERIC_CLOCKEVENTS
270 select ARCH_WANT_OPTIONAL_GPIOLIB
271 select PLAT_VERSATILE
272 select PLAT_VERSATILE_CLCD
273 select ARM_TIMER_SP804
274 select GPIO_PL061 if GPIOLIB
275 select NEED_MACH_MEMORY_H
277 This enables support for ARM Ltd RealView boards.
279 config ARCH_VERSATILE
280 bool "ARM Ltd. Versatile family"
284 select HAVE_MACH_CLKDEV
286 select GENERIC_CLOCKEVENTS
287 select ARCH_WANT_OPTIONAL_GPIOLIB
288 select PLAT_VERSATILE
289 select PLAT_VERSATILE_CLCD
290 select PLAT_VERSATILE_FPGA_IRQ
291 select ARM_TIMER_SP804
293 This enables support for ARM Ltd Versatile board.
296 bool "ARM Ltd. Versatile Express family"
297 select ARCH_WANT_OPTIONAL_GPIOLIB
299 select ARM_TIMER_SP804
301 select HAVE_MACH_CLKDEV
302 select GENERIC_CLOCKEVENTS
304 select HAVE_PATA_PLATFORM
306 select PLAT_VERSATILE
307 select PLAT_VERSATILE_CLCD
309 This enables support for the ARM Ltd Versatile Express boards.
313 select ARCH_REQUIRE_GPIOLIB
317 This enables support for systems based on the Atmel AT91RM9200,
318 AT91SAM9 and AT91CAP9 processors.
321 bool "Broadcom BCMRING"
325 select ARM_TIMER_SP804
327 select GENERIC_CLOCKEVENTS
328 select ARCH_WANT_OPTIONAL_GPIOLIB
330 Support for Broadcom's BCMRing platform.
333 bool "Cirrus Logic CLPS711x/EP721x-based"
335 select ARCH_USES_GETTIMEOFFSET
336 select NEED_MACH_MEMORY_H
338 Support for Cirrus Logic 711x/721x based boards.
341 bool "Cavium Networks CNS3XXX family"
343 select GENERIC_CLOCKEVENTS
345 select MIGHT_HAVE_PCI
346 select PCI_DOMAINS if PCI
348 Support for Cavium Networks CNS3XXX platform.
351 bool "Cortina Systems Gemini"
353 select ARCH_REQUIRE_GPIOLIB
354 select ARCH_USES_GETTIMEOFFSET
356 Support for the Cortina Systems Gemini family SoCs
359 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
363 select GENERIC_CLOCKEVENTS
365 select GENERIC_IRQ_CHIP
369 Support for CSR SiRFSoC ARM Cortex A9 Platform
376 select ARCH_USES_GETTIMEOFFSET
377 select NEED_MACH_MEMORY_H
379 This is an evaluation board for the StrongARM processor available
380 from Digital. It has limited hardware on-board, including an
381 Ethernet interface, two PCMCIA sockets, two serial ports and a
390 select ARCH_REQUIRE_GPIOLIB
391 select ARCH_HAS_HOLES_MEMORYMODEL
392 select ARCH_USES_GETTIMEOFFSET
395 This enables support for the Cirrus EP93xx series of CPUs.
397 config ARCH_FOOTBRIDGE
401 select GENERIC_CLOCKEVENTS
402 select NEED_MACH_MEMORY_H
404 Support for systems based on the DC21285 companion chip
405 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
408 bool "Freescale MXC/iMX-based"
409 select GENERIC_CLOCKEVENTS
410 select ARCH_REQUIRE_GPIOLIB
413 select GENERIC_IRQ_CHIP
414 select HAVE_SCHED_CLOCK
416 Support for Freescale MXC/iMX-based family of processors
419 bool "Freescale MXS-based"
420 select GENERIC_CLOCKEVENTS
421 select ARCH_REQUIRE_GPIOLIB
425 Support for Freescale MXS-based family of processors
428 bool "Hilscher NetX based"
432 select GENERIC_CLOCKEVENTS
434 This enables support for systems based on the Hilscher NetX Soc
437 bool "Hynix HMS720x-based"
440 select ARCH_USES_GETTIMEOFFSET
442 This enables support for systems based on the Hynix HMS720x
450 select ARCH_SUPPORTS_MSI
452 select NEED_MACH_MEMORY_H
454 Support for Intel's IOP13XX (XScale) family of processors.
462 select ARCH_REQUIRE_GPIOLIB
464 Support for Intel's 80219 and IOP32X (XScale) family of
473 select ARCH_REQUIRE_GPIOLIB
475 Support for Intel's IOP33X (XScale) family of processors.
482 select ARCH_USES_GETTIMEOFFSET
483 select NEED_MACH_MEMORY_H
485 Support for Intel's IXP23xx (XScale) family of processors.
488 bool "IXP2400/2800-based"
492 select ARCH_USES_GETTIMEOFFSET
493 select NEED_MACH_MEMORY_H
495 Support for Intel's IXP2400/2800 (XScale) family of processors.
503 select GENERIC_CLOCKEVENTS
504 select HAVE_SCHED_CLOCK
505 select MIGHT_HAVE_PCI
506 select DMABOUNCE if PCI
508 Support for Intel's IXP4XX (XScale) family of processors.
514 select ARCH_REQUIRE_GPIOLIB
515 select GENERIC_CLOCKEVENTS
518 Support for the Marvell Dove SoC 88AP510
521 bool "Marvell Kirkwood"
524 select ARCH_REQUIRE_GPIOLIB
525 select GENERIC_CLOCKEVENTS
528 Support for the following Marvell Kirkwood series SoCs:
529 88F6180, 88F6192 and 88F6281.
535 select ARCH_REQUIRE_GPIOLIB
538 select USB_ARCH_HAS_OHCI
541 select GENERIC_CLOCKEVENTS
543 Support for the NXP LPC32XX family of processors
546 bool "Marvell MV78xx0"
549 select ARCH_REQUIRE_GPIOLIB
550 select GENERIC_CLOCKEVENTS
553 Support for the following Marvell MV78xx0 series SoCs:
561 select ARCH_REQUIRE_GPIOLIB
562 select GENERIC_CLOCKEVENTS
565 Support for the following Marvell Orion 5x series SoCs:
566 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
567 Orion-2 (5281), Orion-1-90 (6183).
570 bool "Marvell PXA168/910/MMP2"
572 select ARCH_REQUIRE_GPIOLIB
574 select GENERIC_CLOCKEVENTS
575 select HAVE_SCHED_CLOCK
580 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
583 bool "Micrel/Kendin KS8695"
585 select ARCH_REQUIRE_GPIOLIB
586 select ARCH_USES_GETTIMEOFFSET
587 select NEED_MACH_MEMORY_H
589 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
590 System-on-Chip devices.
593 bool "Nuvoton W90X900 CPU"
595 select ARCH_REQUIRE_GPIOLIB
598 select GENERIC_CLOCKEVENTS
600 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
601 At present, the w90x900 has been renamed nuc900, regarding
602 the ARM series product line, you can login the following
603 link address to know more.
605 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
606 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
609 bool "Nuvoton NUC93X CPU"
613 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
614 low-power and high performance MPEG-4/JPEG multimedia controller chip.
621 select GENERIC_CLOCKEVENTS
624 select HAVE_SCHED_CLOCK
625 select ARCH_HAS_CPUFREQ
627 This enables support for NVIDIA Tegra based systems (Tegra APX,
628 Tegra 6xx and Tegra 2 series).
631 bool "Philips Nexperia PNX4008 Mobile"
634 select ARCH_USES_GETTIMEOFFSET
636 This enables support for Philips PNX4008 mobile platform.
639 bool "PXA2xx/PXA3xx-based"
642 select ARCH_HAS_CPUFREQ
645 select ARCH_REQUIRE_GPIOLIB
646 select GENERIC_CLOCKEVENTS
647 select HAVE_SCHED_CLOCK
652 select MULTI_IRQ_HANDLER
654 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
659 select GENERIC_CLOCKEVENTS
660 select ARCH_REQUIRE_GPIOLIB
663 Support for Qualcomm MSM/QSD based systems. This runs on the
664 apps processor of the MSM/QSD and depends on a shared memory
665 interface to the modem processor which runs the baseband
666 stack and controls some vital subsystems
667 (clock and power control, etc).
670 bool "Renesas SH-Mobile / R-Mobile"
673 select HAVE_MACH_CLKDEV
674 select GENERIC_CLOCKEVENTS
677 select MULTI_IRQ_HANDLER
678 select PM_GENERIC_DOMAINS if PM
679 select NEED_MACH_MEMORY_H
681 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
688 select ARCH_MAY_HAVE_PC_FDC
689 select HAVE_PATA_PLATFORM
692 select ARCH_SPARSEMEM_ENABLE
693 select ARCH_USES_GETTIMEOFFSET
694 select NEED_MACH_MEMORY_H
696 On the Acorn Risc-PC, Linux can support the internal IDE disk and
697 CD-ROM interface, serial and parallel port, and the floppy drive.
704 select ARCH_SPARSEMEM_ENABLE
706 select ARCH_HAS_CPUFREQ
708 select GENERIC_CLOCKEVENTS
710 select HAVE_SCHED_CLOCK
712 select ARCH_REQUIRE_GPIOLIB
713 select NEED_MACH_MEMORY_H
715 Support for StrongARM 11x0 based boards.
718 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
720 select ARCH_HAS_CPUFREQ
723 select ARCH_USES_GETTIMEOFFSET
724 select HAVE_S3C2410_I2C if I2C
726 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
727 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
728 the Samsung SMDK2410 development board (and derivatives).
730 Note, the S3C2416 and the S3C2450 are so close that they even share
731 the same SoC ID code. This means that there is no separate machine
732 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
735 bool "Samsung S3C64XX"
742 select ARCH_USES_GETTIMEOFFSET
743 select ARCH_HAS_CPUFREQ
744 select ARCH_REQUIRE_GPIOLIB
745 select SAMSUNG_CLKSRC
746 select SAMSUNG_IRQ_VIC_TIMER
747 select SAMSUNG_IRQ_UART
748 select S3C_GPIO_TRACK
749 select S3C_GPIO_PULL_UPDOWN
750 select S3C_GPIO_CFG_S3C24XX
751 select S3C_GPIO_CFG_S3C64XX
753 select USB_ARCH_HAS_OHCI
754 select SAMSUNG_GPIOLIB_4BIT
755 select HAVE_S3C2410_I2C if I2C
756 select HAVE_S3C2410_WATCHDOG if WATCHDOG
758 Samsung S3C64XX series based systems
761 bool "Samsung S5P6440 S5P6450"
767 select HAVE_S3C2410_WATCHDOG if WATCHDOG
768 select GENERIC_CLOCKEVENTS
769 select HAVE_SCHED_CLOCK
770 select HAVE_S3C2410_I2C if I2C
771 select HAVE_S3C_RTC if RTC_CLASS
773 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
777 bool "Samsung S5PC100"
782 select ARM_L1_CACHE_SHIFT_6
783 select ARCH_USES_GETTIMEOFFSET
784 select HAVE_S3C2410_I2C if I2C
785 select HAVE_S3C_RTC if RTC_CLASS
786 select HAVE_S3C2410_WATCHDOG if WATCHDOG
788 Samsung S5PC100 series based systems
791 bool "Samsung S5PV210/S5PC110"
793 select ARCH_SPARSEMEM_ENABLE
794 select ARCH_HAS_HOLES_MEMORYMODEL
799 select ARM_L1_CACHE_SHIFT_6
800 select ARCH_HAS_CPUFREQ
801 select GENERIC_CLOCKEVENTS
802 select HAVE_SCHED_CLOCK
803 select HAVE_S3C2410_I2C if I2C
804 select HAVE_S3C_RTC if RTC_CLASS
805 select HAVE_S3C2410_WATCHDOG if WATCHDOG
806 select NEED_MACH_MEMORY_H
808 Samsung S5PV210/S5PC110 series based systems
811 bool "Samsung EXYNOS4"
813 select ARCH_SPARSEMEM_ENABLE
814 select ARCH_HAS_HOLES_MEMORYMODEL
818 select ARCH_HAS_CPUFREQ
819 select GENERIC_CLOCKEVENTS
820 select HAVE_S3C_RTC if RTC_CLASS
821 select HAVE_S3C2410_I2C if I2C
822 select HAVE_S3C2410_WATCHDOG if WATCHDOG
823 select NEED_MACH_MEMORY_H
825 Samsung EXYNOS4 series based systems
834 select ARCH_USES_GETTIMEOFFSET
835 select NEED_MACH_MEMORY_H
837 Support for the StrongARM based Digital DNARD machine, also known
838 as "Shark" (<http://www.shark-linux.de/shark.html>).
841 bool "Telechips TCC ARM926-based systems"
846 select GENERIC_CLOCKEVENTS
848 Support for Telechips TCC ARM926-based systems.
851 bool "ST-Ericsson U300 Series"
855 select HAVE_SCHED_CLOCK
859 select GENERIC_CLOCKEVENTS
861 select HAVE_MACH_CLKDEV
863 select NEED_MACH_MEMORY_H
865 Support for ST-Ericsson U300 series mobile platforms.
868 bool "ST-Ericsson U8500 Series"
871 select GENERIC_CLOCKEVENTS
873 select ARCH_REQUIRE_GPIOLIB
874 select ARCH_HAS_CPUFREQ
876 Support for ST-Ericsson's Ux500 architecture
879 bool "STMicroelectronics Nomadik"
884 select GENERIC_CLOCKEVENTS
885 select ARCH_REQUIRE_GPIOLIB
887 Support for the Nomadik platform by ST-Ericsson
891 select GENERIC_CLOCKEVENTS
892 select ARCH_REQUIRE_GPIOLIB
896 select GENERIC_ALLOCATOR
897 select GENERIC_IRQ_CHIP
898 select ARCH_HAS_HOLES_MEMORYMODEL
900 Support for TI's DaVinci platform.
905 select ARCH_REQUIRE_GPIOLIB
906 select ARCH_HAS_CPUFREQ
908 select GENERIC_CLOCKEVENTS
909 select HAVE_SCHED_CLOCK
910 select ARCH_HAS_HOLES_MEMORYMODEL
912 Support for TI's OMAP platform (OMAP1/2/3/4).
917 select ARCH_REQUIRE_GPIOLIB
920 select GENERIC_CLOCKEVENTS
923 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
926 bool "VIA/WonderMedia 85xx"
929 select ARCH_HAS_CPUFREQ
930 select GENERIC_CLOCKEVENTS
931 select ARCH_REQUIRE_GPIOLIB
934 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
937 bool "Xilinx Zynq ARM Cortex A9 Platform"
940 select GENERIC_CLOCKEVENTS
947 Support for Xilinx Zynq ARM Cortex A9 Platform
951 # This is sorted alphabetically by mach-* pathname. However, plat-*
952 # Kconfigs may be included either alphabetically (according to the
953 # plat- suffix) or along side the corresponding mach-* source.
955 source "arch/arm/mach-at91/Kconfig"
957 source "arch/arm/mach-bcmring/Kconfig"
959 source "arch/arm/mach-clps711x/Kconfig"
961 source "arch/arm/mach-cns3xxx/Kconfig"
963 source "arch/arm/mach-davinci/Kconfig"
965 source "arch/arm/mach-dove/Kconfig"
967 source "arch/arm/mach-ep93xx/Kconfig"
969 source "arch/arm/mach-footbridge/Kconfig"
971 source "arch/arm/mach-gemini/Kconfig"
973 source "arch/arm/mach-h720x/Kconfig"
975 source "arch/arm/mach-integrator/Kconfig"
977 source "arch/arm/mach-iop32x/Kconfig"
979 source "arch/arm/mach-iop33x/Kconfig"
981 source "arch/arm/mach-iop13xx/Kconfig"
983 source "arch/arm/mach-ixp4xx/Kconfig"
985 source "arch/arm/mach-ixp2000/Kconfig"
987 source "arch/arm/mach-ixp23xx/Kconfig"
989 source "arch/arm/mach-kirkwood/Kconfig"
991 source "arch/arm/mach-ks8695/Kconfig"
993 source "arch/arm/mach-lpc32xx/Kconfig"
995 source "arch/arm/mach-msm/Kconfig"
997 source "arch/arm/mach-mv78xx0/Kconfig"
999 source "arch/arm/plat-mxc/Kconfig"
1001 source "arch/arm/mach-mxs/Kconfig"
1003 source "arch/arm/mach-netx/Kconfig"
1005 source "arch/arm/mach-nomadik/Kconfig"
1006 source "arch/arm/plat-nomadik/Kconfig"
1008 source "arch/arm/mach-nuc93x/Kconfig"
1010 source "arch/arm/plat-omap/Kconfig"
1012 source "arch/arm/mach-omap1/Kconfig"
1014 source "arch/arm/mach-omap2/Kconfig"
1016 source "arch/arm/mach-orion5x/Kconfig"
1018 source "arch/arm/mach-pxa/Kconfig"
1019 source "arch/arm/plat-pxa/Kconfig"
1021 source "arch/arm/mach-mmp/Kconfig"
1023 source "arch/arm/mach-realview/Kconfig"
1025 source "arch/arm/mach-sa1100/Kconfig"
1027 source "arch/arm/plat-samsung/Kconfig"
1028 source "arch/arm/plat-s3c24xx/Kconfig"
1029 source "arch/arm/plat-s5p/Kconfig"
1031 source "arch/arm/plat-spear/Kconfig"
1033 source "arch/arm/plat-tcc/Kconfig"
1036 source "arch/arm/mach-s3c2410/Kconfig"
1037 source "arch/arm/mach-s3c2412/Kconfig"
1038 source "arch/arm/mach-s3c2416/Kconfig"
1039 source "arch/arm/mach-s3c2440/Kconfig"
1040 source "arch/arm/mach-s3c2443/Kconfig"
1044 source "arch/arm/mach-s3c64xx/Kconfig"
1047 source "arch/arm/mach-s5p64x0/Kconfig"
1049 source "arch/arm/mach-s5pc100/Kconfig"
1051 source "arch/arm/mach-s5pv210/Kconfig"
1053 source "arch/arm/mach-exynos4/Kconfig"
1055 source "arch/arm/mach-shmobile/Kconfig"
1057 source "arch/arm/mach-tegra/Kconfig"
1059 source "arch/arm/mach-u300/Kconfig"
1061 source "arch/arm/mach-ux500/Kconfig"
1063 source "arch/arm/mach-versatile/Kconfig"
1065 source "arch/arm/mach-vexpress/Kconfig"
1066 source "arch/arm/plat-versatile/Kconfig"
1068 source "arch/arm/mach-vt8500/Kconfig"
1070 source "arch/arm/mach-w90x900/Kconfig"
1072 # Definitions to make life easier
1078 select GENERIC_CLOCKEVENTS
1079 select HAVE_SCHED_CLOCK
1084 select GENERIC_IRQ_CHIP
1085 select HAVE_SCHED_CLOCK
1090 config PLAT_VERSATILE
1093 config ARM_TIMER_SP804
1097 source arch/arm/mm/Kconfig
1100 bool "Enable iWMMXt support"
1101 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1102 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1104 Enable support for iWMMXt context switching at run time if
1105 running on a CPU that supports it.
1107 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1110 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1114 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1115 (!ARCH_OMAP3 || OMAP3_EMU)
1119 config MULTI_IRQ_HANDLER
1122 Allow each machine to specify it's own IRQ handler at run time.
1125 source "arch/arm/Kconfig-nommu"
1128 config ARM_ERRATA_411920
1129 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1130 depends on CPU_V6 || CPU_V6K
1132 Invalidation of the Instruction Cache operation can
1133 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1134 It does not affect the MPCore. This option enables the ARM Ltd.
1135 recommended workaround.
1137 config ARM_ERRATA_430973
1138 bool "ARM errata: Stale prediction on replaced interworking branch"
1141 This option enables the workaround for the 430973 Cortex-A8
1142 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1143 interworking branch is replaced with another code sequence at the
1144 same virtual address, whether due to self-modifying code or virtual
1145 to physical address re-mapping, Cortex-A8 does not recover from the
1146 stale interworking branch prediction. This results in Cortex-A8
1147 executing the new code sequence in the incorrect ARM or Thumb state.
1148 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1149 and also flushes the branch target cache at every context switch.
1150 Note that setting specific bits in the ACTLR register may not be
1151 available in non-secure mode.
1153 config ARM_ERRATA_458693
1154 bool "ARM errata: Processor deadlock when a false hazard is created"
1157 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1158 erratum. For very specific sequences of memory operations, it is
1159 possible for a hazard condition intended for a cache line to instead
1160 be incorrectly associated with a different cache line. This false
1161 hazard might then cause a processor deadlock. The workaround enables
1162 the L1 caching of the NEON accesses and disables the PLD instruction
1163 in the ACTLR register. Note that setting specific bits in the ACTLR
1164 register may not be available in non-secure mode.
1166 config ARM_ERRATA_460075
1167 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1170 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1171 erratum. Any asynchronous access to the L2 cache may encounter a
1172 situation in which recent store transactions to the L2 cache are lost
1173 and overwritten with stale memory contents from external memory. The
1174 workaround disables the write-allocate mode for the L2 cache via the
1175 ACTLR register. Note that setting specific bits in the ACTLR register
1176 may not be available in non-secure mode.
1178 config ARM_ERRATA_742230
1179 bool "ARM errata: DMB operation may be faulty"
1180 depends on CPU_V7 && SMP
1182 This option enables the workaround for the 742230 Cortex-A9
1183 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1184 between two write operations may not ensure the correct visibility
1185 ordering of the two writes. This workaround sets a specific bit in
1186 the diagnostic register of the Cortex-A9 which causes the DMB
1187 instruction to behave as a DSB, ensuring the correct behaviour of
1190 config ARM_ERRATA_742231
1191 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1192 depends on CPU_V7 && SMP
1194 This option enables the workaround for the 742231 Cortex-A9
1195 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1196 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1197 accessing some data located in the same cache line, may get corrupted
1198 data due to bad handling of the address hazard when the line gets
1199 replaced from one of the CPUs at the same time as another CPU is
1200 accessing it. This workaround sets specific bits in the diagnostic
1201 register of the Cortex-A9 which reduces the linefill issuing
1202 capabilities of the processor.
1204 config PL310_ERRATA_588369
1205 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1206 depends on CACHE_L2X0
1208 The PL310 L2 cache controller implements three types of Clean &
1209 Invalidate maintenance operations: by Physical Address
1210 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1211 They are architecturally defined to behave as the execution of a
1212 clean operation followed immediately by an invalidate operation,
1213 both performing to the same memory location. This functionality
1214 is not correctly implemented in PL310 as clean lines are not
1215 invalidated as a result of these operations.
1217 config ARM_ERRATA_720789
1218 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1219 depends on CPU_V7 && SMP
1221 This option enables the workaround for the 720789 Cortex-A9 (prior to
1222 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1223 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1224 As a consequence of this erratum, some TLB entries which should be
1225 invalidated are not, resulting in an incoherency in the system page
1226 tables. The workaround changes the TLB flushing routines to invalidate
1227 entries regardless of the ASID.
1229 config PL310_ERRATA_727915
1230 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1231 depends on CACHE_L2X0
1233 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1234 operation (offset 0x7FC). This operation runs in background so that
1235 PL310 can handle normal accesses while it is in progress. Under very
1236 rare circumstances, due to this erratum, write data can be lost when
1237 PL310 treats a cacheable write transaction during a Clean &
1238 Invalidate by Way operation.
1240 config ARM_ERRATA_743622
1241 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1244 This option enables the workaround for the 743622 Cortex-A9
1245 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1246 optimisation in the Cortex-A9 Store Buffer may lead to data
1247 corruption. This workaround sets a specific bit in the diagnostic
1248 register of the Cortex-A9 which disables the Store Buffer
1249 optimisation, preventing the defect from occurring. This has no
1250 visible impact on the overall performance or power consumption of the
1253 config ARM_ERRATA_751472
1254 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1255 depends on CPU_V7 && SMP
1257 This option enables the workaround for the 751472 Cortex-A9 (prior
1258 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1259 completion of a following broadcasted operation if the second
1260 operation is received by a CPU before the ICIALLUIS has completed,
1261 potentially leading to corrupted entries in the cache or TLB.
1263 config ARM_ERRATA_753970
1264 bool "ARM errata: cache sync operation may be faulty"
1265 depends on CACHE_PL310
1267 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1269 Under some condition the effect of cache sync operation on
1270 the store buffer still remains when the operation completes.
1271 This means that the store buffer is always asked to drain and
1272 this prevents it from merging any further writes. The workaround
1273 is to replace the normal offset of cache sync operation (0x730)
1274 by another offset targeting an unmapped PL310 register 0x740.
1275 This has the same effect as the cache sync operation: store buffer
1276 drain and waiting for all buffers empty.
1278 config ARM_ERRATA_754322
1279 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1282 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1283 r3p*) erratum. A speculative memory access may cause a page table walk
1284 which starts prior to an ASID switch but completes afterwards. This
1285 can populate the micro-TLB with a stale entry which may be hit with
1286 the new ASID. This workaround places two dsb instructions in the mm
1287 switching code so that no page table walks can cross the ASID switch.
1289 config ARM_ERRATA_754327
1290 bool "ARM errata: no automatic Store Buffer drain"
1291 depends on CPU_V7 && SMP
1293 This option enables the workaround for the 754327 Cortex-A9 (prior to
1294 r2p0) erratum. The Store Buffer does not have any automatic draining
1295 mechanism and therefore a livelock may occur if an external agent
1296 continuously polls a memory location waiting to observe an update.
1297 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1298 written polling loops from denying visibility of updates to memory.
1300 config ARM_ERRATA_364296
1301 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1302 depends on CPU_V6 && !SMP
1304 This options enables the workaround for the 364296 ARM1136
1305 r0p2 erratum (possible cache data corruption with
1306 hit-under-miss enabled). It sets the undocumented bit 31 in
1307 the auxiliary control register and the FI bit in the control
1308 register, thus disabling hit-under-miss without putting the
1309 processor into full low interrupt latency mode. ARM11MPCore
1312 config ARM_ERRATA_764369
1313 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1314 depends on CPU_V7 && SMP
1316 This option enables the workaround for erratum 764369
1317 affecting Cortex-A9 MPCore with two or more processors (all
1318 current revisions). Under certain timing circumstances, a data
1319 cache line maintenance operation by MVA targeting an Inner
1320 Shareable memory region may fail to proceed up to either the
1321 Point of Coherency or to the Point of Unification of the
1322 system. This workaround adds a DSB instruction before the
1323 relevant cache maintenance functions and sets a specific bit
1324 in the diagnostic control register of the SCU.
1328 source "arch/arm/common/Kconfig"
1338 Find out whether you have ISA slots on your motherboard. ISA is the
1339 name of a bus system, i.e. the way the CPU talks to the other stuff
1340 inside your box. Other bus systems are PCI, EISA, MicroChannel
1341 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1342 newer boards don't support it. If you have ISA, say Y, otherwise N.
1344 # Select ISA DMA controller support
1349 # Select ISA DMA interface
1354 bool "PCI support" if MIGHT_HAVE_PCI
1356 Find out whether you have a PCI motherboard. PCI is the name of a
1357 bus system, i.e. the way the CPU talks to the other stuff inside
1358 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1359 VESA. If you have PCI, say Y, otherwise N.
1365 config PCI_NANOENGINE
1366 bool "BSE nanoEngine PCI support"
1367 depends on SA1100_NANOENGINE
1369 Enable PCI on the BSE nanoEngine board.
1374 # Select the host bridge type
1375 config PCI_HOST_VIA82C505
1377 depends on PCI && ARCH_SHARK
1380 config PCI_HOST_ITE8152
1382 depends on PCI && MACH_ARMCORE
1386 source "drivers/pci/Kconfig"
1388 source "drivers/pcmcia/Kconfig"
1392 menu "Kernel Features"
1394 source "kernel/time/Kconfig"
1397 bool "Symmetric Multi-Processing"
1398 depends on CPU_V6K || CPU_V7
1399 depends on GENERIC_CLOCKEVENTS
1400 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1401 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1402 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1403 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1404 select USE_GENERIC_SMP_HELPERS
1405 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1407 This enables support for systems with more than one CPU. If you have
1408 a system with only one CPU, like most personal computers, say N. If
1409 you have a system with more than one CPU, say Y.
1411 If you say N here, the kernel will run on single and multiprocessor
1412 machines, but will use only one CPU of a multiprocessor machine. If
1413 you say Y here, the kernel will run on many, but not all, single
1414 processor machines. On a single processor machine, the kernel will
1415 run faster if you say N here.
1417 See also <file:Documentation/i386/IO-APIC.txt>,
1418 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1419 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1421 If you don't know what to do here, say N.
1424 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1425 depends on EXPERIMENTAL
1426 depends on SMP && !XIP_KERNEL
1429 SMP kernels contain instructions which fail on non-SMP processors.
1430 Enabling this option allows the kernel to modify itself to make
1431 these instructions safe. Disabling it allows about 1K of space
1434 If you don't know what to do here, say Y.
1439 This option enables support for the ARM system coherency unit
1446 This options enables support for the ARM timer and watchdog unit
1449 prompt "Memory split"
1452 Select the desired split between kernel and user memory.
1454 If you are not absolutely sure what you are doing, leave this
1458 bool "3G/1G user/kernel split"
1460 bool "2G/2G user/kernel split"
1462 bool "1G/3G user/kernel split"
1467 default 0x40000000 if VMSPLIT_1G
1468 default 0x80000000 if VMSPLIT_2G
1472 int "Maximum number of CPUs (2-32)"
1478 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1479 depends on SMP && HOTPLUG && EXPERIMENTAL
1481 Say Y here to experiment with turning CPUs off and on. CPUs
1482 can be controlled through /sys/devices/system/cpu.
1485 bool "Use local timer interrupts"
1488 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1490 Enable support for local timers on SMP platforms, rather then the
1491 legacy IPI broadcast method. Local timers allows the system
1492 accounting to be spread across the timer interval, preventing a
1493 "thundering herd" at every timer tick.
1495 source kernel/Kconfig.preempt
1499 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1500 ARCH_S5PV210 || ARCH_EXYNOS4
1501 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1502 default AT91_TIMER_HZ if ARCH_AT91
1503 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1506 config THUMB2_KERNEL
1507 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1508 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1510 select ARM_ASM_UNIFIED
1512 By enabling this option, the kernel will be compiled in
1513 Thumb-2 mode. A compiler/assembler that understand the unified
1514 ARM-Thumb syntax is needed.
1518 config THUMB2_AVOID_R_ARM_THM_JUMP11
1519 bool "Work around buggy Thumb-2 short branch relocations in gas"
1520 depends on THUMB2_KERNEL && MODULES
1523 Various binutils versions can resolve Thumb-2 branches to
1524 locally-defined, preemptible global symbols as short-range "b.n"
1525 branch instructions.
1527 This is a problem, because there's no guarantee the final
1528 destination of the symbol, or any candidate locations for a
1529 trampoline, are within range of the branch. For this reason, the
1530 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1531 relocation in modules at all, and it makes little sense to add
1534 The symptom is that the kernel fails with an "unsupported
1535 relocation" error when loading some modules.
1537 Until fixed tools are available, passing
1538 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1539 code which hits this problem, at the cost of a bit of extra runtime
1540 stack usage in some cases.
1542 The problem is described in more detail at:
1543 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1545 Only Thumb-2 kernels are affected.
1547 Unless you are sure your tools don't have this problem, say Y.
1549 config ARM_ASM_UNIFIED
1553 bool "Use the ARM EABI to compile the kernel"
1555 This option allows for the kernel to be compiled using the latest
1556 ARM ABI (aka EABI). This is only useful if you are using a user
1557 space environment that is also compiled with EABI.
1559 Since there are major incompatibilities between the legacy ABI and
1560 EABI, especially with regard to structure member alignment, this
1561 option also changes the kernel syscall calling convention to
1562 disambiguate both ABIs and allow for backward compatibility support
1563 (selected with CONFIG_OABI_COMPAT).
1565 To use this you need GCC version 4.0.0 or later.
1568 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1569 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1572 This option preserves the old syscall interface along with the
1573 new (ARM EABI) one. It also provides a compatibility layer to
1574 intercept syscalls that have structure arguments which layout
1575 in memory differs between the legacy ABI and the new ARM EABI
1576 (only for non "thumb" binaries). This option adds a tiny
1577 overhead to all syscalls and produces a slightly larger kernel.
1578 If you know you'll be using only pure EABI user space then you
1579 can say N here. If this option is not selected and you attempt
1580 to execute a legacy ABI binary then the result will be
1581 UNPREDICTABLE (in fact it can be predicted that it won't work
1582 at all). If in doubt say Y.
1584 config ARCH_HAS_HOLES_MEMORYMODEL
1587 config ARCH_SPARSEMEM_ENABLE
1590 config ARCH_SPARSEMEM_DEFAULT
1591 def_bool ARCH_SPARSEMEM_ENABLE
1593 config ARCH_SELECT_MEMORY_MODEL
1594 def_bool ARCH_SPARSEMEM_ENABLE
1596 config HAVE_ARCH_PFN_VALID
1597 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1600 bool "High Memory Support"
1603 The address space of ARM processors is only 4 Gigabytes large
1604 and it has to accommodate user address space, kernel address
1605 space as well as some memory mapped IO. That means that, if you
1606 have a large amount of physical memory and/or IO, not all of the
1607 memory can be "permanently mapped" by the kernel. The physical
1608 memory that is not permanently mapped is called "high memory".
1610 Depending on the selected kernel/user memory split, minimum
1611 vmalloc space and actual amount of RAM, you may not need this
1612 option which should result in a slightly faster kernel.
1617 bool "Allocate 2nd-level pagetables from highmem"
1620 config HW_PERF_EVENTS
1621 bool "Enable hardware performance counter support for perf events"
1622 depends on PERF_EVENTS && CPU_HAS_PMU
1625 Enable hardware performance counter support for perf events. If
1626 disabled, perf events will use software events only.
1630 config FORCE_MAX_ZONEORDER
1631 int "Maximum zone order" if ARCH_SHMOBILE
1632 range 11 64 if ARCH_SHMOBILE
1633 default "9" if SA1111
1636 The kernel memory allocator divides physically contiguous memory
1637 blocks into "zones", where each zone is a power of two number of
1638 pages. This option selects the largest power of two that the kernel
1639 keeps in the memory allocator. If you need to allocate very large
1640 blocks of physically contiguous memory, then you may need to
1641 increase this value.
1643 This config option is actually maximum order plus one. For example,
1644 a value of 11 means that the largest free memory block is 2^10 pages.
1647 bool "Timer and CPU usage LEDs"
1648 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1649 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1650 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1651 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1652 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1653 ARCH_AT91 || ARCH_DAVINCI || \
1654 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1656 If you say Y here, the LEDs on your machine will be used
1657 to provide useful information about your current system status.
1659 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1660 be able to select which LEDs are active using the options below. If
1661 you are compiling a kernel for the EBSA-110 or the LART however, the
1662 red LED will simply flash regularly to indicate that the system is
1663 still functional. It is safe to say Y here if you have a CATS
1664 system, but the driver will do nothing.
1667 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1668 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1669 || MACH_OMAP_PERSEUS2
1671 depends on !GENERIC_CLOCKEVENTS
1672 default y if ARCH_EBSA110
1674 If you say Y here, one of the system LEDs (the green one on the
1675 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1676 will flash regularly to indicate that the system is still
1677 operational. This is mainly useful to kernel hackers who are
1678 debugging unstable kernels.
1680 The LART uses the same LED for both Timer LED and CPU usage LED
1681 functions. You may choose to use both, but the Timer LED function
1682 will overrule the CPU usage LED.
1685 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1687 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1688 || MACH_OMAP_PERSEUS2
1691 If you say Y here, the red LED will be used to give a good real
1692 time indication of CPU usage, by lighting whenever the idle task
1693 is not currently executing.
1695 The LART uses the same LED for both Timer LED and CPU usage LED
1696 functions. You may choose to use both, but the Timer LED function
1697 will overrule the CPU usage LED.
1699 config ALIGNMENT_TRAP
1701 depends on CPU_CP15_MMU
1702 default y if !ARCH_EBSA110
1703 select HAVE_PROC_CPU if PROC_FS
1705 ARM processors cannot fetch/store information which is not
1706 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1707 address divisible by 4. On 32-bit ARM processors, these non-aligned
1708 fetch/store instructions will be emulated in software if you say
1709 here, which has a severe performance impact. This is necessary for
1710 correct operation of some network protocols. With an IP-only
1711 configuration it is safe to say N, otherwise say Y.
1713 config UACCESS_WITH_MEMCPY
1714 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1715 depends on MMU && EXPERIMENTAL
1716 default y if CPU_FEROCEON
1718 Implement faster copy_to_user and clear_user methods for CPU
1719 cores where a 8-word STM instruction give significantly higher
1720 memory write throughput than a sequence of individual 32bit stores.
1722 A possible side effect is a slight increase in scheduling latency
1723 between threads sharing the same address space if they invoke
1724 such copy operations with large buffers.
1726 However, if the CPU data cache is using a write-allocate mode,
1727 this option is unlikely to provide any performance gain.
1731 prompt "Enable seccomp to safely compute untrusted bytecode"
1733 This kernel feature is useful for number crunching applications
1734 that may need to compute untrusted bytecode during their
1735 execution. By using pipes or other transports made available to
1736 the process as file descriptors supporting the read/write
1737 syscalls, it's possible to isolate those applications in
1738 their own address space using seccomp. Once seccomp is
1739 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1740 and the task is only allowed to execute a few safe syscalls
1741 defined by each seccomp mode.
1743 config CC_STACKPROTECTOR
1744 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1745 depends on EXPERIMENTAL
1747 This option turns on the -fstack-protector GCC feature. This
1748 feature puts, at the beginning of functions, a canary value on
1749 the stack just before the return address, and validates
1750 the value just before actually returning. Stack based buffer
1751 overflows (that need to overwrite this return address) now also
1752 overwrite the canary, which gets detected and the attack is then
1753 neutralized via a kernel panic.
1754 This feature requires gcc version 4.2 or above.
1756 config DEPRECATED_PARAM_STRUCT
1757 bool "Provide old way to pass kernel parameters"
1759 This was deprecated in 2001 and announced to live on for 5 years.
1760 Some old boot loaders still use this way.
1767 bool "Flattened Device Tree support"
1769 select OF_EARLY_FLATTREE
1772 Include support for flattened device tree machine descriptions.
1774 # Compressed boot loader in ROM. Yes, we really want to ask about
1775 # TEXT and BSS so we preserve their values in the config files.
1776 config ZBOOT_ROM_TEXT
1777 hex "Compressed ROM boot loader base address"
1780 The physical address at which the ROM-able zImage is to be
1781 placed in the target. Platforms which normally make use of
1782 ROM-able zImage formats normally set this to a suitable
1783 value in their defconfig file.
1785 If ZBOOT_ROM is not enabled, this has no effect.
1787 config ZBOOT_ROM_BSS
1788 hex "Compressed ROM boot loader BSS address"
1791 The base address of an area of read/write memory in the target
1792 for the ROM-able zImage which must be available while the
1793 decompressor is running. It must be large enough to hold the
1794 entire decompressed kernel plus an additional 128 KiB.
1795 Platforms which normally make use of ROM-able zImage formats
1796 normally set this to a suitable value in their defconfig file.
1798 If ZBOOT_ROM is not enabled, this has no effect.
1801 bool "Compressed boot loader in ROM/flash"
1802 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1804 Say Y here if you intend to execute your compressed kernel image
1805 (zImage) directly from ROM or flash. If unsure, say N.
1808 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1809 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1810 default ZBOOT_ROM_NONE
1812 Include experimental SD/MMC loading code in the ROM-able zImage.
1813 With this enabled it is possible to write the the ROM-able zImage
1814 kernel image to an MMC or SD card and boot the kernel straight
1815 from the reset vector. At reset the processor Mask ROM will load
1816 the first part of the the ROM-able zImage which in turn loads the
1817 rest the kernel image to RAM.
1819 config ZBOOT_ROM_NONE
1820 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1822 Do not load image from SD or MMC
1824 config ZBOOT_ROM_MMCIF
1825 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1827 Load image from MMCIF hardware block.
1829 config ZBOOT_ROM_SH_MOBILE_SDHI
1830 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1832 Load image from SDHI hardware block
1837 string "Default kernel command string"
1840 On some architectures (EBSA110 and CATS), there is currently no way
1841 for the boot loader to pass arguments to the kernel. For these
1842 architectures, you should supply some command-line options at build
1843 time by entering them here. As a minimum, you should specify the
1844 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1847 prompt "Kernel command line type" if CMDLINE != ""
1848 default CMDLINE_FROM_BOOTLOADER
1850 config CMDLINE_FROM_BOOTLOADER
1851 bool "Use bootloader kernel arguments if available"
1853 Uses the command-line options passed by the boot loader. If
1854 the boot loader doesn't provide any, the default kernel command
1855 string provided in CMDLINE will be used.
1857 config CMDLINE_EXTEND
1858 bool "Extend bootloader kernel arguments"
1860 The command-line arguments provided by the boot loader will be
1861 appended to the default kernel command string.
1863 config CMDLINE_FORCE
1864 bool "Always use the default kernel command string"
1866 Always use the default kernel command string, even if the boot
1867 loader passes other arguments to the kernel.
1868 This is useful if you cannot or don't want to change the
1869 command-line options your boot loader passes to the kernel.
1873 bool "Kernel Execute-In-Place from ROM"
1874 depends on !ZBOOT_ROM
1876 Execute-In-Place allows the kernel to run from non-volatile storage
1877 directly addressable by the CPU, such as NOR flash. This saves RAM
1878 space since the text section of the kernel is not loaded from flash
1879 to RAM. Read-write sections, such as the data section and stack,
1880 are still copied to RAM. The XIP kernel is not compressed since
1881 it has to run directly from flash, so it will take more space to
1882 store it. The flash address used to link the kernel object files,
1883 and for storing it, is configuration dependent. Therefore, if you
1884 say Y here, you must know the proper physical address where to
1885 store the kernel image depending on your own flash memory usage.
1887 Also note that the make target becomes "make xipImage" rather than
1888 "make zImage" or "make Image". The final kernel binary to put in
1889 ROM memory will be arch/arm/boot/xipImage.
1893 config XIP_PHYS_ADDR
1894 hex "XIP Kernel Physical Location"
1895 depends on XIP_KERNEL
1896 default "0x00080000"
1898 This is the physical address in your flash memory the kernel will
1899 be linked for and stored to. This address is dependent on your
1903 bool "Kexec system call (EXPERIMENTAL)"
1904 depends on EXPERIMENTAL
1906 kexec is a system call that implements the ability to shutdown your
1907 current kernel, and to start another kernel. It is like a reboot
1908 but it is independent of the system firmware. And like a reboot
1909 you can start any kernel with it, not just Linux.
1911 It is an ongoing process to be certain the hardware in a machine
1912 is properly shutdown, so do not be surprised if this code does not
1913 initially work for you. It may help to enable device hotplugging
1917 bool "Export atags in procfs"
1921 Should the atags used to boot the kernel be exported in an "atags"
1922 file in procfs. Useful with kexec.
1925 bool "Build kdump crash kernel (EXPERIMENTAL)"
1926 depends on EXPERIMENTAL
1928 Generate crash dump after being started by kexec. This should
1929 be normally only set in special crash dump kernels which are
1930 loaded in the main kernel with kexec-tools into a specially
1931 reserved region and then later executed after a crash by
1932 kdump/kexec. The crash dump kernel must be compiled to a
1933 memory address not used by the main kernel
1935 For more details see Documentation/kdump/kdump.txt
1937 config AUTO_ZRELADDR
1938 bool "Auto calculation of the decompressed kernel image address"
1939 depends on !ZBOOT_ROM && !ARCH_U300
1941 ZRELADDR is the physical address where the decompressed kernel
1942 image will be placed. If AUTO_ZRELADDR is selected, the address
1943 will be determined at run-time by masking the current IP with
1944 0xf8000000. This assumes the zImage being placed in the first 128MB
1945 from start of memory.
1949 menu "CPU Power Management"
1953 source "drivers/cpufreq/Kconfig"
1956 tristate "CPUfreq driver for i.MX CPUs"
1957 depends on ARCH_MXC && CPU_FREQ
1959 This enables the CPUfreq driver for i.MX CPUs.
1961 config CPU_FREQ_SA1100
1964 config CPU_FREQ_SA1110
1967 config CPU_FREQ_INTEGRATOR
1968 tristate "CPUfreq driver for ARM Integrator CPUs"
1969 depends on ARCH_INTEGRATOR && CPU_FREQ
1972 This enables the CPUfreq driver for ARM Integrator CPUs.
1974 For details, take a look at <file:Documentation/cpu-freq>.
1980 depends on CPU_FREQ && ARCH_PXA && PXA25x
1982 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1987 Internal configuration node for common cpufreq on Samsung SoC
1989 config CPU_FREQ_S3C24XX
1990 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
1991 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1994 This enables the CPUfreq driver for the Samsung S3C24XX family
1997 For details, take a look at <file:Documentation/cpu-freq>.
2001 config CPU_FREQ_S3C24XX_PLL
2002 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2003 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2005 Compile in support for changing the PLL frequency from the
2006 S3C24XX series CPUfreq driver. The PLL takes time to settle
2007 after a frequency change, so by default it is not enabled.
2009 This also means that the PLL tables for the selected CPU(s) will
2010 be built which may increase the size of the kernel image.
2012 config CPU_FREQ_S3C24XX_DEBUG
2013 bool "Debug CPUfreq Samsung driver core"
2014 depends on CPU_FREQ_S3C24XX
2016 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2018 config CPU_FREQ_S3C24XX_IODEBUG
2019 bool "Debug CPUfreq Samsung driver IO timing"
2020 depends on CPU_FREQ_S3C24XX
2022 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2024 config CPU_FREQ_S3C24XX_DEBUGFS
2025 bool "Export debugfs for CPUFreq"
2026 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2028 Export status information via debugfs.
2032 source "drivers/cpuidle/Kconfig"
2036 menu "Floating point emulation"
2038 comment "At least one emulation must be selected"
2041 bool "NWFPE math emulation"
2042 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2044 Say Y to include the NWFPE floating point emulator in the kernel.
2045 This is necessary to run most binaries. Linux does not currently
2046 support floating point hardware so you need to say Y here even if
2047 your machine has an FPA or floating point co-processor podule.
2049 You may say N here if you are going to load the Acorn FPEmulator
2050 early in the bootup.
2053 bool "Support extended precision"
2054 depends on FPE_NWFPE
2056 Say Y to include 80-bit support in the kernel floating-point
2057 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2058 Note that gcc does not generate 80-bit operations by default,
2059 so in most cases this option only enlarges the size of the
2060 floating point emulator without any good reason.
2062 You almost surely want to say N here.
2065 bool "FastFPE math emulation (EXPERIMENTAL)"
2066 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2068 Say Y here to include the FAST floating point emulator in the kernel.
2069 This is an experimental much faster emulator which now also has full
2070 precision for the mantissa. It does not support any exceptions.
2071 It is very simple, and approximately 3-6 times faster than NWFPE.
2073 It should be sufficient for most programs. It may be not suitable
2074 for scientific calculations, but you have to check this for yourself.
2075 If you do not feel you need a faster FP emulation you should better
2079 bool "VFP-format floating point maths"
2080 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2082 Say Y to include VFP support code in the kernel. This is needed
2083 if your hardware includes a VFP unit.
2085 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2086 release notes and additional status information.
2088 Say N if your target does not have VFP hardware.
2096 bool "Advanced SIMD (NEON) Extension support"
2097 depends on VFPv3 && CPU_V7
2099 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2104 menu "Userspace binary formats"
2106 source "fs/Kconfig.binfmt"
2109 tristate "RISC OS personality"
2112 Say Y here to include the kernel code necessary if you want to run
2113 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2114 experimental; if this sounds frightening, say N and sleep in peace.
2115 You can also say M here to compile this support as a module (which
2116 will be called arthur).
2120 menu "Power management options"
2122 source "kernel/power/Kconfig"
2124 config ARCH_SUSPEND_POSSIBLE
2125 depends on !ARCH_S5P64X0 && !ARCH_S5PC100
2126 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2127 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2132 source "net/Kconfig"
2134 source "drivers/Kconfig"
2138 source "arch/arm/Kconfig.debug"
2140 source "security/Kconfig"
2142 source "crypto/Kconfig"
2144 source "lib/Kconfig"