4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_MIGHT_HAVE_PC_PARPORT
9 select ARCH_USE_BUILTIN_BSWAP
10 select ARCH_USE_CMPXCHG_LOCKREF
11 select ARCH_WANT_IPC_PARSE_VERSION
12 select BUILDTIME_EXTABLE_SORT if MMU
13 select CLONE_BACKWARDS
14 select CPU_PM if (SUSPEND || CPU_IDLE)
15 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
16 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
17 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
18 select GENERIC_IDLE_POLL_SETUP
19 select GENERIC_IRQ_PROBE
20 select GENERIC_IRQ_SHOW
21 select GENERIC_PCI_IOMAP
22 select GENERIC_SCHED_CLOCK
23 select GENERIC_SMP_IDLE_THREAD
24 select GENERIC_STRNCPY_FROM_USER
25 select GENERIC_STRNLEN_USER
26 select HARDIRQS_SW_RESEND
27 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
28 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
30 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
31 select HAVE_ARCH_TRACEHOOK
33 select HAVE_CC_STACKPROTECTOR
34 select HAVE_CONTEXT_TRACKING
35 select HAVE_C_RECORDMCOUNT
36 select HAVE_DEBUG_KMEMLEAK
37 select HAVE_DMA_API_DEBUG
39 select HAVE_DMA_CONTIGUOUS if MMU
40 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
41 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
42 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
43 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
44 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
45 select HAVE_GENERIC_DMA_COHERENT
46 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
47 select HAVE_IDE if PCI || ISA || PCMCIA
48 select HAVE_IRQ_TIME_ACCOUNTING
49 select HAVE_KERNEL_GZIP
50 select HAVE_KERNEL_LZ4
51 select HAVE_KERNEL_LZMA
52 select HAVE_KERNEL_LZO
54 select HAVE_KPROBES if !XIP_KERNEL
55 select HAVE_KRETPROBES if (HAVE_KPROBES)
57 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
58 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
59 select HAVE_PERF_EVENTS
61 select HAVE_PERF_USER_STACK_DUMP
62 select HAVE_REGS_AND_STACK_ACCESS_API
63 select HAVE_SYSCALL_TRACEPOINTS
65 select HAVE_VIRT_CPU_ACCOUNTING_GEN
66 select IRQ_FORCED_THREADING
68 select MODULES_USE_ELF_REL
71 select OLD_SIGSUSPEND3
72 select PERF_USE_VMALLOC
74 select SYS_SUPPORTS_APM_EMULATION
75 # Above selects are sorted alphabetically; please add new ones
76 # according to that. Thanks.
78 The ARM series is a line of low-power-consumption RISC chip designs
79 licensed by ARM Ltd and targeted at embedded applications and
80 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
81 manufactured, but legacy ARM-based PC hardware remains popular in
82 Europe. There is an ARM Linux project with a web page at
83 <http://www.arm.linux.org.uk/>.
85 config ARM_HAS_SG_CHAIN
88 config NEED_SG_DMA_LENGTH
91 config ARM_DMA_USE_IOMMU
93 select ARM_HAS_SG_CHAIN
94 select NEED_SG_DMA_LENGTH
98 config ARM_DMA_IOMMU_ALIGNMENT
99 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
103 DMA mapping framework by default aligns all buffers to the smallest
104 PAGE_SIZE order which is greater than or equal to the requested buffer
105 size. This works well for buffers up to a few hundreds kilobytes, but
106 for larger buffers it just a waste of address space. Drivers which has
107 relatively small addressing window (like 64Mib) might run out of
108 virtual space with just a few allocations.
110 With this parameter you can specify the maximum PAGE_SIZE order for
111 DMA IOMMU buffers. Larger buffers will be aligned only to this
112 specified order. The order is expressed as a power of two multiplied
117 config MIGHT_HAVE_PCI
120 config SYS_SUPPORTS_APM_EMULATION
125 select GENERIC_ALLOCATOR
136 The Extended Industry Standard Architecture (EISA) bus was
137 developed as an open alternative to the IBM MicroChannel bus.
139 The EISA bus provided some of the features of the IBM MicroChannel
140 bus while maintaining backward compatibility with cards made for
141 the older ISA bus. The EISA bus saw limited use between 1988 and
142 1995 when it was made obsolete by the PCI bus.
144 Say Y here if you are building a kernel for an EISA-based machine.
151 config STACKTRACE_SUPPORT
155 config HAVE_LATENCYTOP_SUPPORT
160 config LOCKDEP_SUPPORT
164 config TRACE_IRQFLAGS_SUPPORT
168 config RWSEM_GENERIC_SPINLOCK
172 config RWSEM_XCHGADD_ALGORITHM
175 config ARCH_HAS_ILOG2_U32
178 config ARCH_HAS_ILOG2_U64
181 config ARCH_HAS_CPUFREQ
184 Internal node to signify that the ARCH has CPUFREQ support
185 and that the relevant menu configurations are displayed for
188 config ARCH_HAS_BANDGAP
191 config GENERIC_HWEIGHT
195 config GENERIC_CALIBRATE_DELAY
199 config ARCH_MAY_HAVE_PC_FDC
205 config NEED_DMA_MAP_STATE
208 config ARCH_SUPPORTS_UPROBES
211 config ARCH_HAS_DMA_SET_COHERENT_MASK
214 config GENERIC_ISA_DMA
220 config NEED_RET_TO_USER
228 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
229 default DRAM_BASE if REMAP_VECTORS_TO_RAM
232 The base address of exception vectors. This must be two pages
235 config ARM_PATCH_PHYS_VIRT
236 bool "Patch physical to virtual translations at runtime" if EMBEDDED
238 depends on !XIP_KERNEL && MMU
239 depends on !ARCH_REALVIEW || !SPARSEMEM
241 Patch phys-to-virt and virt-to-phys translation functions at
242 boot and module load time according to the position of the
243 kernel in system memory.
245 This can only be used with non-XIP MMU kernels where the base
246 of physical memory is at a 16MB boundary.
248 Only disable this option if you know that you do not require
249 this feature (eg, building a kernel for a single machine) and
250 you need to shrink the kernel to the minimal size.
252 config NEED_MACH_GPIO_H
255 Select this when mach/gpio.h is required to provide special
256 definitions for this platform. The need for mach/gpio.h should
257 be avoided when possible.
259 config NEED_MACH_IO_H
262 Select this when mach/io.h is required to provide special
263 definitions for this platform. The need for mach/io.h should
264 be avoided when possible.
266 config NEED_MACH_MEMORY_H
269 Select this when mach/memory.h is required to provide special
270 definitions for this platform. The need for mach/memory.h should
271 be avoided when possible.
274 hex "Physical address of main memory" if MMU
275 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
276 default DRAM_BASE if !MMU
278 Please provide the physical address corresponding to the
279 location of main memory in your system.
285 source "init/Kconfig"
287 source "kernel/Kconfig.freezer"
292 bool "MMU-based Paged Memory Management Support"
295 Select if you want MMU-based virtualised addressing space
296 support by paged memory management. If unsure, say 'Y'.
299 # The "ARM system type" choice list is ordered alphabetically by option
300 # text. Please add new entries in the option alphabetic order.
303 prompt "ARM system type"
304 default ARCH_VERSATILE if !MMU
305 default ARCH_MULTIPLATFORM if MMU
307 config ARCH_MULTIPLATFORM
308 bool "Allow multiple platforms to be selected"
310 select ARCH_WANT_OPTIONAL_GPIOLIB
311 select ARM_HAS_SG_CHAIN
312 select ARM_PATCH_PHYS_VIRT
316 select GENERIC_CLOCKEVENTS
317 select MULTI_IRQ_HANDLER
321 config ARCH_INTEGRATOR
322 bool "ARM Ltd. Integrator family"
323 select ARCH_HAS_CPUFREQ
325 select ARM_PATCH_PHYS_VIRT
328 select COMMON_CLK_VERSATILE
329 select GENERIC_CLOCKEVENTS
332 select MULTI_IRQ_HANDLER
333 select NEED_MACH_MEMORY_H
334 select PLAT_VERSATILE
337 select VERSATILE_FPGA_IRQ
339 Support for ARM's Integrator platform.
342 bool "ARM Ltd. RealView family"
343 select ARCH_WANT_OPTIONAL_GPIOLIB
345 select ARM_TIMER_SP804
347 select COMMON_CLK_VERSATILE
348 select GENERIC_CLOCKEVENTS
349 select GPIO_PL061 if GPIOLIB
351 select NEED_MACH_MEMORY_H
352 select PLAT_VERSATILE
353 select PLAT_VERSATILE_CLCD
355 This enables support for ARM Ltd RealView boards.
357 config ARCH_VERSATILE
358 bool "ARM Ltd. Versatile family"
359 select ARCH_WANT_OPTIONAL_GPIOLIB
361 select ARM_TIMER_SP804
364 select GENERIC_CLOCKEVENTS
365 select HAVE_MACH_CLKDEV
367 select PLAT_VERSATILE
368 select PLAT_VERSATILE_CLCD
369 select PLAT_VERSATILE_CLOCK
370 select VERSATILE_FPGA_IRQ
372 This enables support for ARM Ltd Versatile board.
376 select ARCH_REQUIRE_GPIOLIB
379 select NEED_MACH_GPIO_H
380 select NEED_MACH_IO_H if PCCARD
382 select PINCTRL_AT91 if USE_OF
384 This enables support for systems based on Atmel
385 AT91RM9200 and AT91SAM9* processors.
388 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
389 select ARCH_REQUIRE_GPIOLIB
394 select GENERIC_CLOCKEVENTS
397 Support for Cirrus Logic 711x/721x/731x based boards.
400 bool "Cortina Systems Gemini"
401 select ARCH_REQUIRE_GPIOLIB
404 select GENERIC_CLOCKEVENTS
406 Support for the Cortina Systems Gemini family SoCs
410 select ARCH_USES_GETTIMEOFFSET
413 select NEED_MACH_IO_H
414 select NEED_MACH_MEMORY_H
417 This is an evaluation board for the StrongARM processor available
418 from Digital. It has limited hardware on-board, including an
419 Ethernet interface, two PCMCIA sockets, two serial ports and a
423 bool "Energy Micro efm32"
425 select ARCH_REQUIRE_GPIOLIB
431 select GENERIC_CLOCKEVENTS
437 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
442 select ARCH_HAS_HOLES_MEMORYMODEL
443 select ARCH_REQUIRE_GPIOLIB
444 select ARCH_USES_GETTIMEOFFSET
449 select NEED_MACH_MEMORY_H
451 This enables support for the Cirrus EP93xx series of CPUs.
453 config ARCH_FOOTBRIDGE
457 select GENERIC_CLOCKEVENTS
459 select NEED_MACH_IO_H if !MMU
460 select NEED_MACH_MEMORY_H
462 Support for systems based on the DC21285 companion chip
463 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
466 bool "Hilscher NetX based"
470 select GENERIC_CLOCKEVENTS
472 This enables support for systems based on the Hilscher NetX Soc
478 select NEED_MACH_MEMORY_H
479 select NEED_RET_TO_USER
485 Support for Intel's IOP13XX (XScale) family of processors.
490 select ARCH_REQUIRE_GPIOLIB
493 select NEED_RET_TO_USER
497 Support for Intel's 80219 and IOP32X (XScale) family of
503 select ARCH_REQUIRE_GPIOLIB
506 select NEED_RET_TO_USER
510 Support for Intel's IOP33X (XScale) family of processors.
515 select ARCH_HAS_DMA_SET_COHERENT_MASK
516 select ARCH_REQUIRE_GPIOLIB
517 select ARCH_SUPPORTS_BIG_ENDIAN
520 select DMABOUNCE if PCI
521 select GENERIC_CLOCKEVENTS
522 select MIGHT_HAVE_PCI
523 select NEED_MACH_IO_H
524 select USB_EHCI_BIG_ENDIAN_DESC
525 select USB_EHCI_BIG_ENDIAN_MMIO
527 Support for Intel's IXP4XX (XScale) family of processors.
531 select ARCH_REQUIRE_GPIOLIB
533 select GENERIC_CLOCKEVENTS
534 select MIGHT_HAVE_PCI
538 select PLAT_ORION_LEGACY
540 Support for the Marvell Dove SoC 88AP510
543 bool "Marvell Kirkwood"
544 select ARCH_HAS_CPUFREQ
545 select ARCH_REQUIRE_GPIOLIB
547 select GENERIC_CLOCKEVENTS
552 select PINCTRL_KIRKWOOD
553 select PLAT_ORION_LEGACY
555 Support for the following Marvell Kirkwood series SoCs:
556 88F6180, 88F6192 and 88F6281.
559 bool "Marvell MV78xx0"
560 select ARCH_REQUIRE_GPIOLIB
562 select GENERIC_CLOCKEVENTS
565 select PLAT_ORION_LEGACY
567 Support for the following Marvell MV78xx0 series SoCs:
573 select ARCH_REQUIRE_GPIOLIB
575 select GENERIC_CLOCKEVENTS
578 select PLAT_ORION_LEGACY
580 Support for the following Marvell Orion 5x series SoCs:
581 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
582 Orion-2 (5281), Orion-1-90 (6183).
585 bool "Marvell PXA168/910/MMP2"
587 select ARCH_REQUIRE_GPIOLIB
589 select GENERIC_ALLOCATOR
590 select GENERIC_CLOCKEVENTS
593 select MULTI_IRQ_HANDLER
598 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
601 bool "Micrel/Kendin KS8695"
602 select ARCH_REQUIRE_GPIOLIB
605 select GENERIC_CLOCKEVENTS
606 select NEED_MACH_MEMORY_H
608 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
609 System-on-Chip devices.
612 bool "Nuvoton W90X900 CPU"
613 select ARCH_REQUIRE_GPIOLIB
617 select GENERIC_CLOCKEVENTS
619 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
620 At present, the w90x900 has been renamed nuc900, regarding
621 the ARM series product line, you can login the following
622 link address to know more.
624 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
625 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
629 select ARCH_REQUIRE_GPIOLIB
634 select GENERIC_CLOCKEVENTS
638 Support for the NXP LPC32XX family of processors
641 bool "PXA2xx/PXA3xx-based"
643 select ARCH_HAS_CPUFREQ
645 select ARCH_REQUIRE_GPIOLIB
646 select ARM_CPU_SUSPEND if PM
650 select GENERIC_CLOCKEVENTS
653 select MULTI_IRQ_HANDLER
657 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
660 bool "Qualcomm MSM (non-multiplatform)"
661 select ARCH_REQUIRE_GPIOLIB
663 select GENERIC_CLOCKEVENTS
665 Support for Qualcomm MSM/QSD based systems. This runs on the
666 apps processor of the MSM/QSD and depends on a shared memory
667 interface to the modem processor which runs the baseband
668 stack and controls some vital subsystems
669 (clock and power control, etc).
671 config ARCH_SHMOBILE_LEGACY
672 bool "Renesas ARM SoCs (non-multiplatform)"
674 select ARM_PATCH_PHYS_VIRT
676 select GENERIC_CLOCKEVENTS
677 select HAVE_ARM_SCU if SMP
678 select HAVE_ARM_TWD if SMP
679 select HAVE_MACH_CLKDEV
681 select MIGHT_HAVE_CACHE_L2X0
682 select MULTI_IRQ_HANDLER
685 select PM_GENERIC_DOMAINS if PM
688 Support for Renesas ARM SoC platforms using a non-multiplatform
689 kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
695 select ARCH_MAY_HAVE_PC_FDC
696 select ARCH_SPARSEMEM_ENABLE
697 select ARCH_USES_GETTIMEOFFSET
701 select HAVE_PATA_PLATFORM
703 select NEED_MACH_IO_H
704 select NEED_MACH_MEMORY_H
708 On the Acorn Risc-PC, Linux can support the internal IDE disk and
709 CD-ROM interface, serial and parallel port, and the floppy drive.
713 select ARCH_HAS_CPUFREQ
715 select ARCH_REQUIRE_GPIOLIB
716 select ARCH_SPARSEMEM_ENABLE
721 select GENERIC_CLOCKEVENTS
724 select NEED_MACH_MEMORY_H
727 Support for StrongARM 11x0 based boards.
730 bool "Samsung S3C24XX SoCs"
731 select ARCH_HAS_CPUFREQ
732 select ARCH_REQUIRE_GPIOLIB
735 select CLKSRC_SAMSUNG_PWM
736 select GENERIC_CLOCKEVENTS
738 select HAVE_S3C2410_I2C if I2C
739 select HAVE_S3C2410_WATCHDOG if WATCHDOG
740 select HAVE_S3C_RTC if RTC_CLASS
741 select MULTI_IRQ_HANDLER
742 select NEED_MACH_IO_H
745 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
746 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
747 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
748 Samsung SMDK2410 development board (and derivatives).
751 bool "Samsung S3C64XX"
752 select ARCH_HAS_CPUFREQ
753 select ARCH_REQUIRE_GPIOLIB
758 select CLKSRC_SAMSUNG_PWM
761 select GENERIC_CLOCKEVENTS
763 select HAVE_S3C2410_I2C if I2C
764 select HAVE_S3C2410_WATCHDOG if WATCHDOG
768 select PM_GENERIC_DOMAINS if PM
770 select S3C_GPIO_TRACK
772 select SAMSUNG_WAKEMASK
773 select SAMSUNG_WDT_RESET
775 Samsung S3C64XX series based systems
778 bool "Samsung S5P6440 S5P6450"
781 select CLKSRC_SAMSUNG_PWM
783 select GENERIC_CLOCKEVENTS
785 select HAVE_S3C2410_I2C if I2C
786 select HAVE_S3C2410_WATCHDOG if WATCHDOG
787 select HAVE_S3C_RTC if RTC_CLASS
788 select NEED_MACH_GPIO_H
790 select SAMSUNG_WDT_RESET
792 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
796 bool "Samsung S5PC100"
797 select ARCH_REQUIRE_GPIOLIB
800 select CLKSRC_SAMSUNG_PWM
802 select GENERIC_CLOCKEVENTS
804 select HAVE_S3C2410_I2C if I2C
805 select HAVE_S3C2410_WATCHDOG if WATCHDOG
806 select HAVE_S3C_RTC if RTC_CLASS
807 select NEED_MACH_GPIO_H
809 select SAMSUNG_WDT_RESET
811 Samsung S5PC100 series based systems
814 bool "Samsung S5PV210/S5PC110"
815 select ARCH_HAS_CPUFREQ
816 select ARCH_HAS_HOLES_MEMORYMODEL
817 select ARCH_SPARSEMEM_ENABLE
820 select CLKSRC_SAMSUNG_PWM
822 select GENERIC_CLOCKEVENTS
824 select HAVE_S3C2410_I2C if I2C
825 select HAVE_S3C2410_WATCHDOG if WATCHDOG
826 select HAVE_S3C_RTC if RTC_CLASS
827 select NEED_MACH_GPIO_H
828 select NEED_MACH_MEMORY_H
831 Samsung S5PV210/S5PC110 series based systems
834 bool "Samsung EXYNOS"
835 select ARCH_HAS_CPUFREQ
836 select ARCH_HAS_HOLES_MEMORYMODEL
837 select ARCH_REQUIRE_GPIOLIB
838 select ARCH_SPARSEMEM_ENABLE
842 select GENERIC_CLOCKEVENTS
843 select HAVE_S3C2410_I2C if I2C
844 select HAVE_S3C2410_WATCHDOG if WATCHDOG
845 select HAVE_S3C_RTC if RTC_CLASS
846 select NEED_MACH_MEMORY_H
850 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
854 select ARCH_HAS_HOLES_MEMORYMODEL
855 select ARCH_REQUIRE_GPIOLIB
857 select GENERIC_ALLOCATOR
858 select GENERIC_CLOCKEVENTS
859 select GENERIC_IRQ_CHIP
865 Support for TI's DaVinci platform.
870 select ARCH_HAS_CPUFREQ
871 select ARCH_HAS_HOLES_MEMORYMODEL
873 select ARCH_REQUIRE_GPIOLIB
876 select GENERIC_CLOCKEVENTS
877 select GENERIC_IRQ_CHIP
880 select NEED_MACH_IO_H if PCCARD
881 select NEED_MACH_MEMORY_H
883 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
887 menu "Multiple platform selection"
888 depends on ARCH_MULTIPLATFORM
890 comment "CPU Core family selection"
893 bool "ARMv4 based platforms (FA526)"
894 depends on !ARCH_MULTI_V6_V7
895 select ARCH_MULTI_V4_V5
898 config ARCH_MULTI_V4T
899 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
900 depends on !ARCH_MULTI_V6_V7
901 select ARCH_MULTI_V4_V5
902 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
903 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
904 CPU_ARM925T || CPU_ARM940T)
907 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
908 depends on !ARCH_MULTI_V6_V7
909 select ARCH_MULTI_V4_V5
910 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
911 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
912 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
914 config ARCH_MULTI_V4_V5
918 bool "ARMv6 based platforms (ARM11)"
919 select ARCH_MULTI_V6_V7
923 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
925 select ARCH_MULTI_V6_V7
929 config ARCH_MULTI_V6_V7
931 select MIGHT_HAVE_CACHE_L2X0
933 config ARCH_MULTI_CPU_AUTO
934 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
940 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
944 select HAVE_ARM_ARCH_TIMER
947 # This is sorted alphabetically by mach-* pathname. However, plat-*
948 # Kconfigs may be included either alphabetically (according to the
949 # plat- suffix) or along side the corresponding mach-* source.
951 source "arch/arm/mach-mvebu/Kconfig"
953 source "arch/arm/mach-at91/Kconfig"
955 source "arch/arm/mach-bcm/Kconfig"
957 source "arch/arm/mach-berlin/Kconfig"
959 source "arch/arm/mach-clps711x/Kconfig"
961 source "arch/arm/mach-cns3xxx/Kconfig"
963 source "arch/arm/mach-davinci/Kconfig"
965 source "arch/arm/mach-dove/Kconfig"
967 source "arch/arm/mach-ep93xx/Kconfig"
969 source "arch/arm/mach-footbridge/Kconfig"
971 source "arch/arm/mach-gemini/Kconfig"
973 source "arch/arm/mach-highbank/Kconfig"
975 source "arch/arm/mach-hisi/Kconfig"
977 source "arch/arm/mach-integrator/Kconfig"
979 source "arch/arm/mach-iop32x/Kconfig"
981 source "arch/arm/mach-iop33x/Kconfig"
983 source "arch/arm/mach-iop13xx/Kconfig"
985 source "arch/arm/mach-ixp4xx/Kconfig"
987 source "arch/arm/mach-keystone/Kconfig"
989 source "arch/arm/mach-kirkwood/Kconfig"
991 source "arch/arm/mach-ks8695/Kconfig"
993 source "arch/arm/mach-msm/Kconfig"
995 source "arch/arm/mach-moxart/Kconfig"
997 source "arch/arm/mach-mv78xx0/Kconfig"
999 source "arch/arm/mach-imx/Kconfig"
1001 source "arch/arm/mach-mxs/Kconfig"
1003 source "arch/arm/mach-netx/Kconfig"
1005 source "arch/arm/mach-nomadik/Kconfig"
1007 source "arch/arm/mach-nspire/Kconfig"
1009 source "arch/arm/plat-omap/Kconfig"
1011 source "arch/arm/mach-omap1/Kconfig"
1013 source "arch/arm/mach-omap2/Kconfig"
1015 source "arch/arm/mach-orion5x/Kconfig"
1017 source "arch/arm/mach-picoxcell/Kconfig"
1019 source "arch/arm/mach-pxa/Kconfig"
1020 source "arch/arm/plat-pxa/Kconfig"
1022 source "arch/arm/mach-mmp/Kconfig"
1024 source "arch/arm/mach-qcom/Kconfig"
1026 source "arch/arm/mach-realview/Kconfig"
1028 source "arch/arm/mach-rockchip/Kconfig"
1030 source "arch/arm/mach-sa1100/Kconfig"
1032 source "arch/arm/plat-samsung/Kconfig"
1034 source "arch/arm/mach-socfpga/Kconfig"
1036 source "arch/arm/mach-spear/Kconfig"
1038 source "arch/arm/mach-sti/Kconfig"
1040 source "arch/arm/mach-s3c24xx/Kconfig"
1042 source "arch/arm/mach-s3c64xx/Kconfig"
1044 source "arch/arm/mach-s5p64x0/Kconfig"
1046 source "arch/arm/mach-s5pc100/Kconfig"
1048 source "arch/arm/mach-s5pv210/Kconfig"
1050 source "arch/arm/mach-exynos/Kconfig"
1052 source "arch/arm/mach-shmobile/Kconfig"
1054 source "arch/arm/mach-sunxi/Kconfig"
1056 source "arch/arm/mach-prima2/Kconfig"
1058 source "arch/arm/mach-tegra/Kconfig"
1060 source "arch/arm/mach-u300/Kconfig"
1062 source "arch/arm/mach-ux500/Kconfig"
1064 source "arch/arm/mach-versatile/Kconfig"
1066 source "arch/arm/mach-vexpress/Kconfig"
1067 source "arch/arm/plat-versatile/Kconfig"
1069 source "arch/arm/mach-vt8500/Kconfig"
1071 source "arch/arm/mach-w90x900/Kconfig"
1073 source "arch/arm/mach-zynq/Kconfig"
1075 # Definitions to make life easier
1081 select GENERIC_CLOCKEVENTS
1087 select GENERIC_IRQ_CHIP
1090 config PLAT_ORION_LEGACY
1097 config PLAT_VERSATILE
1100 config ARM_TIMER_SP804
1103 select CLKSRC_OF if OF
1105 source "arch/arm/firmware/Kconfig"
1107 source arch/arm/mm/Kconfig
1111 default 16 if ARCH_EP93XX
1115 bool "Enable iWMMXt support"
1116 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1117 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1119 Enable support for iWMMXt context switching at run time if
1120 running on a CPU that supports it.
1122 config MULTI_IRQ_HANDLER
1125 Allow each machine to specify it's own IRQ handler at run time.
1128 source "arch/arm/Kconfig-nommu"
1131 config PJ4B_ERRATA_4742
1132 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1133 depends on CPU_PJ4B && MACH_ARMADA_370
1136 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1137 Event (WFE) IDLE states, a specific timing sensitivity exists between
1138 the retiring WFI/WFE instructions and the newly issued subsequent
1139 instructions. This sensitivity can result in a CPU hang scenario.
1141 The software must insert either a Data Synchronization Barrier (DSB)
1142 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1145 config ARM_ERRATA_326103
1146 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1149 Executing a SWP instruction to read-only memory does not set bit 11
1150 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1151 treat the access as a read, preventing a COW from occurring and
1152 causing the faulting task to livelock.
1154 config ARM_ERRATA_411920
1155 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1156 depends on CPU_V6 || CPU_V6K
1158 Invalidation of the Instruction Cache operation can
1159 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1160 It does not affect the MPCore. This option enables the ARM Ltd.
1161 recommended workaround.
1163 config ARM_ERRATA_430973
1164 bool "ARM errata: Stale prediction on replaced interworking branch"
1167 This option enables the workaround for the 430973 Cortex-A8
1168 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1169 interworking branch is replaced with another code sequence at the
1170 same virtual address, whether due to self-modifying code or virtual
1171 to physical address re-mapping, Cortex-A8 does not recover from the
1172 stale interworking branch prediction. This results in Cortex-A8
1173 executing the new code sequence in the incorrect ARM or Thumb state.
1174 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1175 and also flushes the branch target cache at every context switch.
1176 Note that setting specific bits in the ACTLR register may not be
1177 available in non-secure mode.
1179 config ARM_ERRATA_458693
1180 bool "ARM errata: Processor deadlock when a false hazard is created"
1182 depends on !ARCH_MULTIPLATFORM
1184 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1185 erratum. For very specific sequences of memory operations, it is
1186 possible for a hazard condition intended for a cache line to instead
1187 be incorrectly associated with a different cache line. This false
1188 hazard might then cause a processor deadlock. The workaround enables
1189 the L1 caching of the NEON accesses and disables the PLD instruction
1190 in the ACTLR register. Note that setting specific bits in the ACTLR
1191 register may not be available in non-secure mode.
1193 config ARM_ERRATA_460075
1194 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1196 depends on !ARCH_MULTIPLATFORM
1198 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1199 erratum. Any asynchronous access to the L2 cache may encounter a
1200 situation in which recent store transactions to the L2 cache are lost
1201 and overwritten with stale memory contents from external memory. The
1202 workaround disables the write-allocate mode for the L2 cache via the
1203 ACTLR register. Note that setting specific bits in the ACTLR register
1204 may not be available in non-secure mode.
1206 config ARM_ERRATA_742230
1207 bool "ARM errata: DMB operation may be faulty"
1208 depends on CPU_V7 && SMP
1209 depends on !ARCH_MULTIPLATFORM
1211 This option enables the workaround for the 742230 Cortex-A9
1212 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1213 between two write operations may not ensure the correct visibility
1214 ordering of the two writes. This workaround sets a specific bit in
1215 the diagnostic register of the Cortex-A9 which causes the DMB
1216 instruction to behave as a DSB, ensuring the correct behaviour of
1219 config ARM_ERRATA_742231
1220 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1221 depends on CPU_V7 && SMP
1222 depends on !ARCH_MULTIPLATFORM
1224 This option enables the workaround for the 742231 Cortex-A9
1225 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1226 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1227 accessing some data located in the same cache line, may get corrupted
1228 data due to bad handling of the address hazard when the line gets
1229 replaced from one of the CPUs at the same time as another CPU is
1230 accessing it. This workaround sets specific bits in the diagnostic
1231 register of the Cortex-A9 which reduces the linefill issuing
1232 capabilities of the processor.
1234 config PL310_ERRATA_588369
1235 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1236 depends on CACHE_L2X0
1238 The PL310 L2 cache controller implements three types of Clean &
1239 Invalidate maintenance operations: by Physical Address
1240 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1241 They are architecturally defined to behave as the execution of a
1242 clean operation followed immediately by an invalidate operation,
1243 both performing to the same memory location. This functionality
1244 is not correctly implemented in PL310 as clean lines are not
1245 invalidated as a result of these operations.
1247 config ARM_ERRATA_643719
1248 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1249 depends on CPU_V7 && SMP
1251 This option enables the workaround for the 643719 Cortex-A9 (prior to
1252 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1253 register returns zero when it should return one. The workaround
1254 corrects this value, ensuring cache maintenance operations which use
1255 it behave as intended and avoiding data corruption.
1257 config ARM_ERRATA_720789
1258 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1261 This option enables the workaround for the 720789 Cortex-A9 (prior to
1262 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1263 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1264 As a consequence of this erratum, some TLB entries which should be
1265 invalidated are not, resulting in an incoherency in the system page
1266 tables. The workaround changes the TLB flushing routines to invalidate
1267 entries regardless of the ASID.
1269 config PL310_ERRATA_727915
1270 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1271 depends on CACHE_L2X0
1273 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1274 operation (offset 0x7FC). This operation runs in background so that
1275 PL310 can handle normal accesses while it is in progress. Under very
1276 rare circumstances, due to this erratum, write data can be lost when
1277 PL310 treats a cacheable write transaction during a Clean &
1278 Invalidate by Way operation.
1280 config ARM_ERRATA_743622
1281 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1283 depends on !ARCH_MULTIPLATFORM
1285 This option enables the workaround for the 743622 Cortex-A9
1286 (r2p*) erratum. Under very rare conditions, a faulty
1287 optimisation in the Cortex-A9 Store Buffer may lead to data
1288 corruption. This workaround sets a specific bit in the diagnostic
1289 register of the Cortex-A9 which disables the Store Buffer
1290 optimisation, preventing the defect from occurring. This has no
1291 visible impact on the overall performance or power consumption of the
1294 config ARM_ERRATA_751472
1295 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1297 depends on !ARCH_MULTIPLATFORM
1299 This option enables the workaround for the 751472 Cortex-A9 (prior
1300 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1301 completion of a following broadcasted operation if the second
1302 operation is received by a CPU before the ICIALLUIS has completed,
1303 potentially leading to corrupted entries in the cache or TLB.
1305 config PL310_ERRATA_753970
1306 bool "PL310 errata: cache sync operation may be faulty"
1307 depends on CACHE_PL310
1309 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1311 Under some condition the effect of cache sync operation on
1312 the store buffer still remains when the operation completes.
1313 This means that the store buffer is always asked to drain and
1314 this prevents it from merging any further writes. The workaround
1315 is to replace the normal offset of cache sync operation (0x730)
1316 by another offset targeting an unmapped PL310 register 0x740.
1317 This has the same effect as the cache sync operation: store buffer
1318 drain and waiting for all buffers empty.
1320 config ARM_ERRATA_754322
1321 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1324 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1325 r3p*) erratum. A speculative memory access may cause a page table walk
1326 which starts prior to an ASID switch but completes afterwards. This
1327 can populate the micro-TLB with a stale entry which may be hit with
1328 the new ASID. This workaround places two dsb instructions in the mm
1329 switching code so that no page table walks can cross the ASID switch.
1331 config ARM_ERRATA_754327
1332 bool "ARM errata: no automatic Store Buffer drain"
1333 depends on CPU_V7 && SMP
1335 This option enables the workaround for the 754327 Cortex-A9 (prior to
1336 r2p0) erratum. The Store Buffer does not have any automatic draining
1337 mechanism and therefore a livelock may occur if an external agent
1338 continuously polls a memory location waiting to observe an update.
1339 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1340 written polling loops from denying visibility of updates to memory.
1342 config ARM_ERRATA_364296
1343 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1346 This options enables the workaround for the 364296 ARM1136
1347 r0p2 erratum (possible cache data corruption with
1348 hit-under-miss enabled). It sets the undocumented bit 31 in
1349 the auxiliary control register and the FI bit in the control
1350 register, thus disabling hit-under-miss without putting the
1351 processor into full low interrupt latency mode. ARM11MPCore
1354 config ARM_ERRATA_764369
1355 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1356 depends on CPU_V7 && SMP
1358 This option enables the workaround for erratum 764369
1359 affecting Cortex-A9 MPCore with two or more processors (all
1360 current revisions). Under certain timing circumstances, a data
1361 cache line maintenance operation by MVA targeting an Inner
1362 Shareable memory region may fail to proceed up to either the
1363 Point of Coherency or to the Point of Unification of the
1364 system. This workaround adds a DSB instruction before the
1365 relevant cache maintenance functions and sets a specific bit
1366 in the diagnostic control register of the SCU.
1368 config PL310_ERRATA_769419
1369 bool "PL310 errata: no automatic Store Buffer drain"
1370 depends on CACHE_L2X0
1372 On revisions of the PL310 prior to r3p2, the Store Buffer does
1373 not automatically drain. This can cause normal, non-cacheable
1374 writes to be retained when the memory system is idle, leading
1375 to suboptimal I/O performance for drivers using coherent DMA.
1376 This option adds a write barrier to the cpu_idle loop so that,
1377 on systems with an outer cache, the store buffer is drained
1380 config ARM_ERRATA_775420
1381 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1384 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1385 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1386 operation aborts with MMU exception, it might cause the processor
1387 to deadlock. This workaround puts DSB before executing ISB if
1388 an abort may occur on cache maintenance.
1390 config ARM_ERRATA_798181
1391 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1392 depends on CPU_V7 && SMP
1394 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1395 adequately shooting down all use of the old entries. This
1396 option enables the Linux kernel workaround for this erratum
1397 which sends an IPI to the CPUs that are running the same ASID
1398 as the one being invalidated.
1400 config ARM_ERRATA_773022
1401 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1404 This option enables the workaround for the 773022 Cortex-A15
1405 (up to r0p4) erratum. In certain rare sequences of code, the
1406 loop buffer may deliver incorrect instructions. This
1407 workaround disables the loop buffer to avoid the erratum.
1411 source "arch/arm/common/Kconfig"
1421 Find out whether you have ISA slots on your motherboard. ISA is the
1422 name of a bus system, i.e. the way the CPU talks to the other stuff
1423 inside your box. Other bus systems are PCI, EISA, MicroChannel
1424 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1425 newer boards don't support it. If you have ISA, say Y, otherwise N.
1427 # Select ISA DMA controller support
1432 # Select ISA DMA interface
1437 bool "PCI support" if MIGHT_HAVE_PCI
1439 Find out whether you have a PCI motherboard. PCI is the name of a
1440 bus system, i.e. the way the CPU talks to the other stuff inside
1441 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1442 VESA. If you have PCI, say Y, otherwise N.
1448 config PCI_NANOENGINE
1449 bool "BSE nanoEngine PCI support"
1450 depends on SA1100_NANOENGINE
1452 Enable PCI on the BSE nanoEngine board.
1457 config PCI_HOST_ITE8152
1459 depends on PCI && MACH_ARMCORE
1463 source "drivers/pci/Kconfig"
1464 source "drivers/pci/pcie/Kconfig"
1466 source "drivers/pcmcia/Kconfig"
1470 menu "Kernel Features"
1475 This option should be selected by machines which have an SMP-
1478 The only effect of this option is to make the SMP-related
1479 options available to the user for configuration.
1482 bool "Symmetric Multi-Processing"
1483 depends on CPU_V6K || CPU_V7
1484 depends on GENERIC_CLOCKEVENTS
1486 depends on MMU || ARM_MPU
1488 This enables support for systems with more than one CPU. If you have
1489 a system with only one CPU, say N. If you have a system with more
1490 than one CPU, say Y.
1492 If you say N here, the kernel will run on uni- and multiprocessor
1493 machines, but will use only one CPU of a multiprocessor machine. If
1494 you say Y here, the kernel will run on many, but not all,
1495 uniprocessor machines. On a uniprocessor machine, the kernel
1496 will run faster if you say N here.
1498 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1499 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1500 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1502 If you don't know what to do here, say N.
1505 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1506 depends on SMP && !XIP_KERNEL && MMU
1509 SMP kernels contain instructions which fail on non-SMP processors.
1510 Enabling this option allows the kernel to modify itself to make
1511 these instructions safe. Disabling it allows about 1K of space
1514 If you don't know what to do here, say Y.
1516 config ARM_CPU_TOPOLOGY
1517 bool "Support cpu topology definition"
1518 depends on SMP && CPU_V7
1521 Support ARM cpu topology definition. The MPIDR register defines
1522 affinity between processors which is then used to describe the cpu
1523 topology of an ARM System.
1526 bool "Multi-core scheduler support"
1527 depends on ARM_CPU_TOPOLOGY
1529 Multi-core scheduler support improves the CPU scheduler's decision
1530 making when dealing with multi-core CPU chips at a cost of slightly
1531 increased overhead in some places. If unsure say N here.
1534 bool "SMT scheduler support"
1535 depends on ARM_CPU_TOPOLOGY
1537 Improves the CPU scheduler's decision making when dealing with
1538 MultiThreading at a cost of slightly increased overhead in some
1539 places. If unsure say N here.
1544 This option enables support for the ARM system coherency unit
1546 config HAVE_ARM_ARCH_TIMER
1547 bool "Architected timer support"
1549 select ARM_ARCH_TIMER
1550 select GENERIC_CLOCKEVENTS
1552 This option enables support for the ARM architected timer
1557 select CLKSRC_OF if OF
1559 This options enables support for the ARM timer and watchdog unit
1562 bool "Multi-Cluster Power Management"
1563 depends on CPU_V7 && SMP
1565 This option provides the common power management infrastructure
1566 for (multi-)cluster based systems, such as big.LITTLE based
1570 bool "big.LITTLE support (Experimental)"
1571 depends on CPU_V7 && SMP
1574 This option enables support selections for the big.LITTLE
1575 system architecture.
1578 bool "big.LITTLE switcher support"
1579 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1580 select ARM_CPU_SUSPEND
1583 The big.LITTLE "switcher" provides the core functionality to
1584 transparently handle transition between a cluster of A15's
1585 and a cluster of A7's in a big.LITTLE system.
1587 config BL_SWITCHER_DUMMY_IF
1588 tristate "Simple big.LITTLE switcher user interface"
1589 depends on BL_SWITCHER && DEBUG_KERNEL
1591 This is a simple and dummy char dev interface to control
1592 the big.LITTLE switcher core code. It is meant for
1593 debugging purposes only.
1596 prompt "Memory split"
1600 Select the desired split between kernel and user memory.
1602 If you are not absolutely sure what you are doing, leave this
1606 bool "3G/1G user/kernel split"
1608 bool "2G/2G user/kernel split"
1610 bool "1G/3G user/kernel split"
1615 default PHYS_OFFSET if !MMU
1616 default 0x40000000 if VMSPLIT_1G
1617 default 0x80000000 if VMSPLIT_2G
1621 int "Maximum number of CPUs (2-32)"
1627 bool "Support for hot-pluggable CPUs"
1630 Say Y here to experiment with turning CPUs off and on. CPUs
1631 can be controlled through /sys/devices/system/cpu.
1634 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1637 Say Y here if you want Linux to communicate with system firmware
1638 implementing the PSCI specification for CPU-centric power
1639 management operations described in ARM document number ARM DEN
1640 0022A ("Power State Coordination Interface System Software on
1643 # The GPIO number here must be sorted by descending number. In case of
1644 # a multiplatform kernel, we just want the highest value required by the
1645 # selected platforms.
1648 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1649 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX
1650 default 392 if ARCH_U8500
1651 default 352 if ARCH_VT8500
1652 default 288 if ARCH_SUNXI
1653 default 264 if MACH_H4700
1656 Maximum number of GPIOs in the system.
1658 If unsure, leave the default value.
1660 source kernel/Kconfig.preempt
1664 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1665 ARCH_S5PV210 || ARCH_EXYNOS4
1666 default AT91_TIMER_HZ if ARCH_AT91
1667 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1671 depends on HZ_FIXED = 0
1672 prompt "Timer frequency"
1696 default HZ_FIXED if HZ_FIXED != 0
1697 default 100 if HZ_100
1698 default 200 if HZ_200
1699 default 250 if HZ_250
1700 default 300 if HZ_300
1701 default 500 if HZ_500
1705 def_bool HIGH_RES_TIMERS
1707 config THUMB2_KERNEL
1708 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1709 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1710 default y if CPU_THUMBONLY
1712 select ARM_ASM_UNIFIED
1715 By enabling this option, the kernel will be compiled in
1716 Thumb-2 mode. A compiler/assembler that understand the unified
1717 ARM-Thumb syntax is needed.
1721 config THUMB2_AVOID_R_ARM_THM_JUMP11
1722 bool "Work around buggy Thumb-2 short branch relocations in gas"
1723 depends on THUMB2_KERNEL && MODULES
1726 Various binutils versions can resolve Thumb-2 branches to
1727 locally-defined, preemptible global symbols as short-range "b.n"
1728 branch instructions.
1730 This is a problem, because there's no guarantee the final
1731 destination of the symbol, or any candidate locations for a
1732 trampoline, are within range of the branch. For this reason, the
1733 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1734 relocation in modules at all, and it makes little sense to add
1737 The symptom is that the kernel fails with an "unsupported
1738 relocation" error when loading some modules.
1740 Until fixed tools are available, passing
1741 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1742 code which hits this problem, at the cost of a bit of extra runtime
1743 stack usage in some cases.
1745 The problem is described in more detail at:
1746 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1748 Only Thumb-2 kernels are affected.
1750 Unless you are sure your tools don't have this problem, say Y.
1752 config ARM_ASM_UNIFIED
1756 bool "Use the ARM EABI to compile the kernel"
1758 This option allows for the kernel to be compiled using the latest
1759 ARM ABI (aka EABI). This is only useful if you are using a user
1760 space environment that is also compiled with EABI.
1762 Since there are major incompatibilities between the legacy ABI and
1763 EABI, especially with regard to structure member alignment, this
1764 option also changes the kernel syscall calling convention to
1765 disambiguate both ABIs and allow for backward compatibility support
1766 (selected with CONFIG_OABI_COMPAT).
1768 To use this you need GCC version 4.0.0 or later.
1771 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1772 depends on AEABI && !THUMB2_KERNEL
1774 This option preserves the old syscall interface along with the
1775 new (ARM EABI) one. It also provides a compatibility layer to
1776 intercept syscalls that have structure arguments which layout
1777 in memory differs between the legacy ABI and the new ARM EABI
1778 (only for non "thumb" binaries). This option adds a tiny
1779 overhead to all syscalls and produces a slightly larger kernel.
1781 The seccomp filter system will not be available when this is
1782 selected, since there is no way yet to sensibly distinguish
1783 between calling conventions during filtering.
1785 If you know you'll be using only pure EABI user space then you
1786 can say N here. If this option is not selected and you attempt
1787 to execute a legacy ABI binary then the result will be
1788 UNPREDICTABLE (in fact it can be predicted that it won't work
1789 at all). If in doubt say N.
1791 config ARCH_HAS_HOLES_MEMORYMODEL
1794 config ARCH_SPARSEMEM_ENABLE
1797 config ARCH_SPARSEMEM_DEFAULT
1798 def_bool ARCH_SPARSEMEM_ENABLE
1800 config ARCH_SELECT_MEMORY_MODEL
1801 def_bool ARCH_SPARSEMEM_ENABLE
1803 config HAVE_ARCH_PFN_VALID
1804 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1807 bool "High Memory Support"
1810 The address space of ARM processors is only 4 Gigabytes large
1811 and it has to accommodate user address space, kernel address
1812 space as well as some memory mapped IO. That means that, if you
1813 have a large amount of physical memory and/or IO, not all of the
1814 memory can be "permanently mapped" by the kernel. The physical
1815 memory that is not permanently mapped is called "high memory".
1817 Depending on the selected kernel/user memory split, minimum
1818 vmalloc space and actual amount of RAM, you may not need this
1819 option which should result in a slightly faster kernel.
1824 bool "Allocate 2nd-level pagetables from highmem"
1827 config HW_PERF_EVENTS
1828 bool "Enable hardware performance counter support for perf events"
1829 depends on PERF_EVENTS
1832 Enable hardware performance counter support for perf events. If
1833 disabled, perf events will use software events only.
1835 config SYS_SUPPORTS_HUGETLBFS
1839 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1843 config ARCH_WANT_GENERAL_HUGETLB
1848 config FORCE_MAX_ZONEORDER
1849 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1850 range 11 64 if ARCH_SHMOBILE_LEGACY
1851 default "12" if SOC_AM33XX
1852 default "9" if SA1111 || ARCH_EFM32
1855 The kernel memory allocator divides physically contiguous memory
1856 blocks into "zones", where each zone is a power of two number of
1857 pages. This option selects the largest power of two that the kernel
1858 keeps in the memory allocator. If you need to allocate very large
1859 blocks of physically contiguous memory, then you may need to
1860 increase this value.
1862 This config option is actually maximum order plus one. For example,
1863 a value of 11 means that the largest free memory block is 2^10 pages.
1865 config ALIGNMENT_TRAP
1867 depends on CPU_CP15_MMU
1868 default y if !ARCH_EBSA110
1869 select HAVE_PROC_CPU if PROC_FS
1871 ARM processors cannot fetch/store information which is not
1872 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1873 address divisible by 4. On 32-bit ARM processors, these non-aligned
1874 fetch/store instructions will be emulated in software if you say
1875 here, which has a severe performance impact. This is necessary for
1876 correct operation of some network protocols. With an IP-only
1877 configuration it is safe to say N, otherwise say Y.
1879 config UACCESS_WITH_MEMCPY
1880 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1882 default y if CPU_FEROCEON
1884 Implement faster copy_to_user and clear_user methods for CPU
1885 cores where a 8-word STM instruction give significantly higher
1886 memory write throughput than a sequence of individual 32bit stores.
1888 A possible side effect is a slight increase in scheduling latency
1889 between threads sharing the same address space if they invoke
1890 such copy operations with large buffers.
1892 However, if the CPU data cache is using a write-allocate mode,
1893 this option is unlikely to provide any performance gain.
1897 prompt "Enable seccomp to safely compute untrusted bytecode"
1899 This kernel feature is useful for number crunching applications
1900 that may need to compute untrusted bytecode during their
1901 execution. By using pipes or other transports made available to
1902 the process as file descriptors supporting the read/write
1903 syscalls, it's possible to isolate those applications in
1904 their own address space using seccomp. Once seccomp is
1905 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1906 and the task is only allowed to execute a few safe syscalls
1907 defined by each seccomp mode.
1920 bool "Xen guest support on ARM (EXPERIMENTAL)"
1921 depends on ARM && AEABI && OF
1922 depends on CPU_V7 && !CPU_V6
1923 depends on !GENERIC_ATOMIC64
1925 select ARCH_DMA_ADDR_T_64BIT
1929 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1936 bool "Flattened Device Tree support"
1939 select OF_EARLY_FLATTREE
1940 select OF_RESERVED_MEM
1942 Include support for flattened device tree machine descriptions.
1945 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1948 This is the traditional way of passing data to the kernel at boot
1949 time. If you are solely relying on the flattened device tree (or
1950 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1951 to remove ATAGS support from your kernel binary. If unsure,
1954 config DEPRECATED_PARAM_STRUCT
1955 bool "Provide old way to pass kernel parameters"
1958 This was deprecated in 2001 and announced to live on for 5 years.
1959 Some old boot loaders still use this way.
1961 # Compressed boot loader in ROM. Yes, we really want to ask about
1962 # TEXT and BSS so we preserve their values in the config files.
1963 config ZBOOT_ROM_TEXT
1964 hex "Compressed ROM boot loader base address"
1967 The physical address at which the ROM-able zImage is to be
1968 placed in the target. Platforms which normally make use of
1969 ROM-able zImage formats normally set this to a suitable
1970 value in their defconfig file.
1972 If ZBOOT_ROM is not enabled, this has no effect.
1974 config ZBOOT_ROM_BSS
1975 hex "Compressed ROM boot loader BSS address"
1978 The base address of an area of read/write memory in the target
1979 for the ROM-able zImage which must be available while the
1980 decompressor is running. It must be large enough to hold the
1981 entire decompressed kernel plus an additional 128 KiB.
1982 Platforms which normally make use of ROM-able zImage formats
1983 normally set this to a suitable value in their defconfig file.
1985 If ZBOOT_ROM is not enabled, this has no effect.
1988 bool "Compressed boot loader in ROM/flash"
1989 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1990 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1992 Say Y here if you intend to execute your compressed kernel image
1993 (zImage) directly from ROM or flash. If unsure, say N.
1996 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1997 depends on ZBOOT_ROM && ARCH_SH7372
1998 default ZBOOT_ROM_NONE
2000 Include experimental SD/MMC loading code in the ROM-able zImage.
2001 With this enabled it is possible to write the ROM-able zImage
2002 kernel image to an MMC or SD card and boot the kernel straight
2003 from the reset vector. At reset the processor Mask ROM will load
2004 the first part of the ROM-able zImage which in turn loads the
2005 rest the kernel image to RAM.
2007 config ZBOOT_ROM_NONE
2008 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
2010 Do not load image from SD or MMC
2012 config ZBOOT_ROM_MMCIF
2013 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
2015 Load image from MMCIF hardware block.
2017 config ZBOOT_ROM_SH_MOBILE_SDHI
2018 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
2020 Load image from SDHI hardware block
2024 config ARM_APPENDED_DTB
2025 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
2028 With this option, the boot code will look for a device tree binary
2029 (DTB) appended to zImage
2030 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
2032 This is meant as a backward compatibility convenience for those
2033 systems with a bootloader that can't be upgraded to accommodate
2034 the documented boot protocol using a device tree.
2036 Beware that there is very little in terms of protection against
2037 this option being confused by leftover garbage in memory that might
2038 look like a DTB header after a reboot if no actual DTB is appended
2039 to zImage. Do not leave this option active in a production kernel
2040 if you don't intend to always append a DTB. Proper passing of the
2041 location into r2 of a bootloader provided DTB is always preferable
2044 config ARM_ATAG_DTB_COMPAT
2045 bool "Supplement the appended DTB with traditional ATAG information"
2046 depends on ARM_APPENDED_DTB
2048 Some old bootloaders can't be updated to a DTB capable one, yet
2049 they provide ATAGs with memory configuration, the ramdisk address,
2050 the kernel cmdline string, etc. Such information is dynamically
2051 provided by the bootloader and can't always be stored in a static
2052 DTB. To allow a device tree enabled kernel to be used with such
2053 bootloaders, this option allows zImage to extract the information
2054 from the ATAG list and store it at run time into the appended DTB.
2057 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2058 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2060 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2061 bool "Use bootloader kernel arguments if available"
2063 Uses the command-line options passed by the boot loader instead of
2064 the device tree bootargs property. If the boot loader doesn't provide
2065 any, the device tree bootargs property will be used.
2067 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2068 bool "Extend with bootloader kernel arguments"
2070 The command-line arguments provided by the boot loader will be
2071 appended to the the device tree bootargs property.
2076 string "Default kernel command string"
2079 On some architectures (EBSA110 and CATS), there is currently no way
2080 for the boot loader to pass arguments to the kernel. For these
2081 architectures, you should supply some command-line options at build
2082 time by entering them here. As a minimum, you should specify the
2083 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2086 prompt "Kernel command line type" if CMDLINE != ""
2087 default CMDLINE_FROM_BOOTLOADER
2090 config CMDLINE_FROM_BOOTLOADER
2091 bool "Use bootloader kernel arguments if available"
2093 Uses the command-line options passed by the boot loader. If
2094 the boot loader doesn't provide any, the default kernel command
2095 string provided in CMDLINE will be used.
2097 config CMDLINE_EXTEND
2098 bool "Extend bootloader kernel arguments"
2100 The command-line arguments provided by the boot loader will be
2101 appended to the default kernel command string.
2103 config CMDLINE_FORCE
2104 bool "Always use the default kernel command string"
2106 Always use the default kernel command string, even if the boot
2107 loader passes other arguments to the kernel.
2108 This is useful if you cannot or don't want to change the
2109 command-line options your boot loader passes to the kernel.
2113 bool "Kernel Execute-In-Place from ROM"
2114 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
2116 Execute-In-Place allows the kernel to run from non-volatile storage
2117 directly addressable by the CPU, such as NOR flash. This saves RAM
2118 space since the text section of the kernel is not loaded from flash
2119 to RAM. Read-write sections, such as the data section and stack,
2120 are still copied to RAM. The XIP kernel is not compressed since
2121 it has to run directly from flash, so it will take more space to
2122 store it. The flash address used to link the kernel object files,
2123 and for storing it, is configuration dependent. Therefore, if you
2124 say Y here, you must know the proper physical address where to
2125 store the kernel image depending on your own flash memory usage.
2127 Also note that the make target becomes "make xipImage" rather than
2128 "make zImage" or "make Image". The final kernel binary to put in
2129 ROM memory will be arch/arm/boot/xipImage.
2133 config XIP_PHYS_ADDR
2134 hex "XIP Kernel Physical Location"
2135 depends on XIP_KERNEL
2136 default "0x00080000"
2138 This is the physical address in your flash memory the kernel will
2139 be linked for and stored to. This address is dependent on your
2143 bool "Kexec system call (EXPERIMENTAL)"
2144 depends on (!SMP || PM_SLEEP_SMP)
2146 kexec is a system call that implements the ability to shutdown your
2147 current kernel, and to start another kernel. It is like a reboot
2148 but it is independent of the system firmware. And like a reboot
2149 you can start any kernel with it, not just Linux.
2151 It is an ongoing process to be certain the hardware in a machine
2152 is properly shutdown, so do not be surprised if this code does not
2153 initially work for you.
2156 bool "Export atags in procfs"
2157 depends on ATAGS && KEXEC
2160 Should the atags used to boot the kernel be exported in an "atags"
2161 file in procfs. Useful with kexec.
2164 bool "Build kdump crash kernel (EXPERIMENTAL)"
2166 Generate crash dump after being started by kexec. This should
2167 be normally only set in special crash dump kernels which are
2168 loaded in the main kernel with kexec-tools into a specially
2169 reserved region and then later executed after a crash by
2170 kdump/kexec. The crash dump kernel must be compiled to a
2171 memory address not used by the main kernel
2173 For more details see Documentation/kdump/kdump.txt
2175 config AUTO_ZRELADDR
2176 bool "Auto calculation of the decompressed kernel image address"
2178 ZRELADDR is the physical address where the decompressed kernel
2179 image will be placed. If AUTO_ZRELADDR is selected, the address
2180 will be determined at run-time by masking the current IP with
2181 0xf8000000. This assumes the zImage being placed in the first 128MB
2182 from start of memory.
2186 menu "CPU Power Management"
2189 source "drivers/cpufreq/Kconfig"
2192 source "drivers/cpuidle/Kconfig"
2196 menu "Floating point emulation"
2198 comment "At least one emulation must be selected"
2201 bool "NWFPE math emulation"
2202 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2204 Say Y to include the NWFPE floating point emulator in the kernel.
2205 This is necessary to run most binaries. Linux does not currently
2206 support floating point hardware so you need to say Y here even if
2207 your machine has an FPA or floating point co-processor podule.
2209 You may say N here if you are going to load the Acorn FPEmulator
2210 early in the bootup.
2213 bool "Support extended precision"
2214 depends on FPE_NWFPE
2216 Say Y to include 80-bit support in the kernel floating-point
2217 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2218 Note that gcc does not generate 80-bit operations by default,
2219 so in most cases this option only enlarges the size of the
2220 floating point emulator without any good reason.
2222 You almost surely want to say N here.
2225 bool "FastFPE math emulation (EXPERIMENTAL)"
2226 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2228 Say Y here to include the FAST floating point emulator in the kernel.
2229 This is an experimental much faster emulator which now also has full
2230 precision for the mantissa. It does not support any exceptions.
2231 It is very simple, and approximately 3-6 times faster than NWFPE.
2233 It should be sufficient for most programs. It may be not suitable
2234 for scientific calculations, but you have to check this for yourself.
2235 If you do not feel you need a faster FP emulation you should better
2239 bool "VFP-format floating point maths"
2240 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2242 Say Y to include VFP support code in the kernel. This is needed
2243 if your hardware includes a VFP unit.
2245 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2246 release notes and additional status information.
2248 Say N if your target does not have VFP hardware.
2256 bool "Advanced SIMD (NEON) Extension support"
2257 depends on VFPv3 && CPU_V7
2259 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2262 config KERNEL_MODE_NEON
2263 bool "Support for NEON in kernel mode"
2264 depends on NEON && AEABI
2266 Say Y to include support for NEON in kernel mode.
2270 menu "Userspace binary formats"
2272 source "fs/Kconfig.binfmt"
2275 tristate "RISC OS personality"
2278 Say Y here to include the kernel code necessary if you want to run
2279 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2280 experimental; if this sounds frightening, say N and sleep in peace.
2281 You can also say M here to compile this support as a module (which
2282 will be called arthur).
2286 menu "Power management options"
2288 source "kernel/power/Kconfig"
2290 config ARCH_SUSPEND_POSSIBLE
2291 depends on !ARCH_S5PC100
2292 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2293 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2296 config ARM_CPU_SUSPEND
2301 source "net/Kconfig"
2303 source "drivers/Kconfig"
2307 source "arch/arm/Kconfig.debug"
2309 source "security/Kconfig"
2311 source "crypto/Kconfig"
2313 source "lib/Kconfig"
2315 source "arch/arm/kvm/Kconfig"