4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_MIGHT_HAVE_PC_PARPORT
9 select ARCH_USE_BUILTIN_BSWAP
10 select ARCH_USE_CMPXCHG_LOCKREF
11 select ARCH_WANT_IPC_PARSE_VERSION
12 select BUILDTIME_EXTABLE_SORT if MMU
13 select CLONE_BACKWARDS
14 select CPU_PM if (SUSPEND || CPU_IDLE)
15 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
16 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
17 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
18 select GENERIC_IDLE_POLL_SETUP
19 select GENERIC_IRQ_PROBE
20 select GENERIC_IRQ_SHOW
21 select GENERIC_PCI_IOMAP
22 select GENERIC_SCHED_CLOCK
23 select GENERIC_SMP_IDLE_THREAD
24 select GENERIC_STRNCPY_FROM_USER
25 select GENERIC_STRNLEN_USER
26 select HARDIRQS_SW_RESEND
27 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
29 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
30 select HAVE_ARCH_TRACEHOOK
32 select HAVE_CONTEXT_TRACKING
33 select HAVE_C_RECORDMCOUNT
34 select HAVE_CC_STACKPROTECTOR
35 select HAVE_DEBUG_KMEMLEAK
36 select HAVE_DMA_API_DEBUG
38 select HAVE_DMA_CONTIGUOUS if MMU
39 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
40 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
41 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
42 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
43 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
44 select HAVE_GENERIC_DMA_COHERENT
45 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
46 select HAVE_IDE if PCI || ISA || PCMCIA
47 select HAVE_IRQ_TIME_ACCOUNTING
48 select HAVE_KERNEL_GZIP
49 select HAVE_KERNEL_LZ4
50 select HAVE_KERNEL_LZMA
51 select HAVE_KERNEL_LZO
53 select HAVE_KPROBES if !XIP_KERNEL
54 select HAVE_KRETPROBES if (HAVE_KPROBES)
56 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
57 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
58 select HAVE_PERF_EVENTS
60 select HAVE_PERF_USER_STACK_DUMP
61 select HAVE_REGS_AND_STACK_ACCESS_API
62 select HAVE_SYSCALL_TRACEPOINTS
64 select HAVE_VIRT_CPU_ACCOUNTING_GEN
65 select IRQ_FORCED_THREADING
67 select MODULES_USE_ELF_REL
70 select OLD_SIGSUSPEND3
71 select PERF_USE_VMALLOC
73 select SYS_SUPPORTS_APM_EMULATION
74 # Above selects are sorted alphabetically; please add new ones
75 # according to that. Thanks.
77 The ARM series is a line of low-power-consumption RISC chip designs
78 licensed by ARM Ltd and targeted at embedded applications and
79 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
80 manufactured, but legacy ARM-based PC hardware remains popular in
81 Europe. There is an ARM Linux project with a web page at
82 <http://www.arm.linux.org.uk/>.
84 config ARM_HAS_SG_CHAIN
87 config NEED_SG_DMA_LENGTH
90 config ARM_DMA_USE_IOMMU
92 select ARM_HAS_SG_CHAIN
93 select NEED_SG_DMA_LENGTH
97 config ARM_DMA_IOMMU_ALIGNMENT
98 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
102 DMA mapping framework by default aligns all buffers to the smallest
103 PAGE_SIZE order which is greater than or equal to the requested buffer
104 size. This works well for buffers up to a few hundreds kilobytes, but
105 for larger buffers it just a waste of address space. Drivers which has
106 relatively small addressing window (like 64Mib) might run out of
107 virtual space with just a few allocations.
109 With this parameter you can specify the maximum PAGE_SIZE order for
110 DMA IOMMU buffers. Larger buffers will be aligned only to this
111 specified order. The order is expressed as a power of two multiplied
119 config MIGHT_HAVE_PCI
122 config SYS_SUPPORTS_APM_EMULATION
127 select GENERIC_ALLOCATOR
138 The Extended Industry Standard Architecture (EISA) bus was
139 developed as an open alternative to the IBM MicroChannel bus.
141 The EISA bus provided some of the features of the IBM MicroChannel
142 bus while maintaining backward compatibility with cards made for
143 the older ISA bus. The EISA bus saw limited use between 1988 and
144 1995 when it was made obsolete by the PCI bus.
146 Say Y here if you are building a kernel for an EISA-based machine.
153 config STACKTRACE_SUPPORT
157 config HAVE_LATENCYTOP_SUPPORT
162 config LOCKDEP_SUPPORT
166 config TRACE_IRQFLAGS_SUPPORT
170 config RWSEM_GENERIC_SPINLOCK
174 config RWSEM_XCHGADD_ALGORITHM
177 config ARCH_HAS_ILOG2_U32
180 config ARCH_HAS_ILOG2_U64
183 config ARCH_HAS_CPUFREQ
186 Internal node to signify that the ARCH has CPUFREQ support
187 and that the relevant menu configurations are displayed for
190 config ARCH_HAS_BANDGAP
193 config GENERIC_HWEIGHT
197 config GENERIC_CALIBRATE_DELAY
201 config ARCH_MAY_HAVE_PC_FDC
207 config NEED_DMA_MAP_STATE
210 config ARCH_SUPPORTS_UPROBES
213 config ARCH_HAS_DMA_SET_COHERENT_MASK
216 config GENERIC_ISA_DMA
222 config NEED_RET_TO_USER
230 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
231 default DRAM_BASE if REMAP_VECTORS_TO_RAM
234 The base address of exception vectors. This must be two pages
237 config ARM_PATCH_PHYS_VIRT
238 bool "Patch physical to virtual translations at runtime" if EMBEDDED
240 depends on !XIP_KERNEL && MMU
241 depends on !ARCH_REALVIEW || !SPARSEMEM
243 Patch phys-to-virt and virt-to-phys translation functions at
244 boot and module load time according to the position of the
245 kernel in system memory.
247 This can only be used with non-XIP MMU kernels where the base
248 of physical memory is at a 16MB boundary.
250 Only disable this option if you know that you do not require
251 this feature (eg, building a kernel for a single machine) and
252 you need to shrink the kernel to the minimal size.
254 config NEED_MACH_GPIO_H
257 Select this when mach/gpio.h is required to provide special
258 definitions for this platform. The need for mach/gpio.h should
259 be avoided when possible.
261 config NEED_MACH_IO_H
264 Select this when mach/io.h is required to provide special
265 definitions for this platform. The need for mach/io.h should
266 be avoided when possible.
268 config NEED_MACH_MEMORY_H
271 Select this when mach/memory.h is required to provide special
272 definitions for this platform. The need for mach/memory.h should
273 be avoided when possible.
276 hex "Physical address of main memory" if MMU
277 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
278 default DRAM_BASE if !MMU
280 Please provide the physical address corresponding to the
281 location of main memory in your system.
287 source "init/Kconfig"
289 source "kernel/Kconfig.freezer"
294 bool "MMU-based Paged Memory Management Support"
297 Select if you want MMU-based virtualised addressing space
298 support by paged memory management. If unsure, say 'Y'.
301 # The "ARM system type" choice list is ordered alphabetically by option
302 # text. Please add new entries in the option alphabetic order.
305 prompt "ARM system type"
306 default ARCH_VERSATILE if !MMU
307 default ARCH_MULTIPLATFORM if MMU
309 config ARCH_MULTIPLATFORM
310 bool "Allow multiple platforms to be selected"
312 select ARCH_WANT_OPTIONAL_GPIOLIB
313 select ARM_PATCH_PHYS_VIRT
316 select GENERIC_CLOCKEVENTS
317 select MULTI_IRQ_HANDLER
321 config ARCH_INTEGRATOR
322 bool "ARM Ltd. Integrator family"
323 select ARCH_HAS_CPUFREQ
325 select ARM_PATCH_PHYS_VIRT
328 select COMMON_CLK_VERSATILE
329 select GENERIC_CLOCKEVENTS
332 select MULTI_IRQ_HANDLER
333 select NEED_MACH_MEMORY_H
334 select PLAT_VERSATILE
337 select VERSATILE_FPGA_IRQ
339 Support for ARM's Integrator platform.
342 bool "ARM Ltd. RealView family"
343 select ARCH_WANT_OPTIONAL_GPIOLIB
345 select ARM_TIMER_SP804
347 select COMMON_CLK_VERSATILE
348 select GENERIC_CLOCKEVENTS
349 select GPIO_PL061 if GPIOLIB
351 select NEED_MACH_MEMORY_H
352 select PLAT_VERSATILE
353 select PLAT_VERSATILE_CLCD
355 This enables support for ARM Ltd RealView boards.
357 config ARCH_VERSATILE
358 bool "ARM Ltd. Versatile family"
359 select ARCH_WANT_OPTIONAL_GPIOLIB
361 select ARM_TIMER_SP804
364 select GENERIC_CLOCKEVENTS
365 select HAVE_MACH_CLKDEV
367 select PLAT_VERSATILE
368 select PLAT_VERSATILE_CLCD
369 select PLAT_VERSATILE_CLOCK
370 select VERSATILE_FPGA_IRQ
372 This enables support for ARM Ltd Versatile board.
376 select ARCH_REQUIRE_GPIOLIB
379 select NEED_MACH_GPIO_H
380 select NEED_MACH_IO_H if PCCARD
382 select PINCTRL_AT91 if USE_OF
384 This enables support for systems based on Atmel
385 AT91RM9200 and AT91SAM9* processors.
388 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
389 select ARCH_REQUIRE_GPIOLIB
394 select GENERIC_CLOCKEVENTS
396 select MULTI_IRQ_HANDLER
399 Support for Cirrus Logic 711x/721x/731x based boards.
402 bool "Cortina Systems Gemini"
403 select ARCH_REQUIRE_GPIOLIB
406 select GENERIC_CLOCKEVENTS
408 Support for the Cortina Systems Gemini family SoCs
412 select ARCH_USES_GETTIMEOFFSET
415 select NEED_MACH_IO_H
416 select NEED_MACH_MEMORY_H
419 This is an evaluation board for the StrongARM processor available
420 from Digital. It has limited hardware on-board, including an
421 Ethernet interface, two PCMCIA sockets, two serial ports and a
425 bool "Energy Micro efm32"
427 select ARCH_REQUIRE_GPIOLIB
433 select GENERIC_CLOCKEVENTS
439 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
444 select ARCH_HAS_HOLES_MEMORYMODEL
445 select ARCH_REQUIRE_GPIOLIB
446 select ARCH_USES_GETTIMEOFFSET
451 select NEED_MACH_MEMORY_H
453 This enables support for the Cirrus EP93xx series of CPUs.
455 config ARCH_FOOTBRIDGE
459 select GENERIC_CLOCKEVENTS
461 select NEED_MACH_IO_H if !MMU
462 select NEED_MACH_MEMORY_H
464 Support for systems based on the DC21285 companion chip
465 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
468 bool "Hilscher NetX based"
472 select GENERIC_CLOCKEVENTS
474 This enables support for systems based on the Hilscher NetX Soc
480 select NEED_MACH_MEMORY_H
481 select NEED_RET_TO_USER
486 Support for Intel's IOP13XX (XScale) family of processors.
491 select ARCH_REQUIRE_GPIOLIB
494 select NEED_RET_TO_USER
498 Support for Intel's 80219 and IOP32X (XScale) family of
504 select ARCH_REQUIRE_GPIOLIB
507 select NEED_RET_TO_USER
511 Support for Intel's IOP33X (XScale) family of processors.
516 select ARCH_HAS_DMA_SET_COHERENT_MASK
517 select ARCH_SUPPORTS_BIG_ENDIAN
518 select ARCH_REQUIRE_GPIOLIB
521 select DMABOUNCE if PCI
522 select GENERIC_CLOCKEVENTS
523 select MIGHT_HAVE_PCI
524 select NEED_MACH_IO_H
525 select USB_EHCI_BIG_ENDIAN_DESC
526 select USB_EHCI_BIG_ENDIAN_MMIO
528 Support for Intel's IXP4XX (XScale) family of processors.
532 select ARCH_REQUIRE_GPIOLIB
534 select GENERIC_CLOCKEVENTS
535 select MIGHT_HAVE_PCI
539 select PLAT_ORION_LEGACY
541 Support for the Marvell Dove SoC 88AP510
544 bool "Marvell Kirkwood"
545 select ARCH_HAS_CPUFREQ
546 select ARCH_REQUIRE_GPIOLIB
548 select GENERIC_CLOCKEVENTS
553 select PINCTRL_KIRKWOOD
554 select PLAT_ORION_LEGACY
556 Support for the following Marvell Kirkwood series SoCs:
557 88F6180, 88F6192 and 88F6281.
560 bool "Marvell MV78xx0"
561 select ARCH_REQUIRE_GPIOLIB
563 select GENERIC_CLOCKEVENTS
566 select PLAT_ORION_LEGACY
568 Support for the following Marvell MV78xx0 series SoCs:
574 select ARCH_REQUIRE_GPIOLIB
576 select GENERIC_CLOCKEVENTS
579 select PLAT_ORION_LEGACY
581 Support for the following Marvell Orion 5x series SoCs:
582 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
583 Orion-2 (5281), Orion-1-90 (6183).
586 bool "Marvell PXA168/910/MMP2"
588 select ARCH_REQUIRE_GPIOLIB
590 select GENERIC_ALLOCATOR
591 select GENERIC_CLOCKEVENTS
594 select MULTI_IRQ_HANDLER
599 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
602 bool "Micrel/Kendin KS8695"
603 select ARCH_REQUIRE_GPIOLIB
606 select GENERIC_CLOCKEVENTS
607 select NEED_MACH_MEMORY_H
609 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
610 System-on-Chip devices.
613 bool "Nuvoton W90X900 CPU"
614 select ARCH_REQUIRE_GPIOLIB
618 select GENERIC_CLOCKEVENTS
620 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
621 At present, the w90x900 has been renamed nuc900, regarding
622 the ARM series product line, you can login the following
623 link address to know more.
625 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
626 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
630 select ARCH_REQUIRE_GPIOLIB
635 select GENERIC_CLOCKEVENTS
640 Support for the NXP LPC32XX family of processors
643 bool "PXA2xx/PXA3xx-based"
645 select ARCH_HAS_CPUFREQ
647 select ARCH_REQUIRE_GPIOLIB
648 select ARM_CPU_SUSPEND if PM
652 select GENERIC_CLOCKEVENTS
655 select MULTI_IRQ_HANDLER
659 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
662 bool "Qualcomm MSM (non-multiplatform)"
663 select ARCH_REQUIRE_GPIOLIB
665 select GENERIC_CLOCKEVENTS
667 Support for Qualcomm MSM/QSD based systems. This runs on the
668 apps processor of the MSM/QSD and depends on a shared memory
669 interface to the modem processor which runs the baseband
670 stack and controls some vital subsystems
671 (clock and power control, etc).
673 config ARCH_SHMOBILE_LEGACY
674 bool "Renesas ARM SoCs (non-multiplatform)"
676 select ARM_PATCH_PHYS_VIRT
678 select GENERIC_CLOCKEVENTS
679 select HAVE_ARM_SCU if SMP
680 select HAVE_ARM_TWD if SMP
681 select HAVE_MACH_CLKDEV
683 select MIGHT_HAVE_CACHE_L2X0
684 select MULTI_IRQ_HANDLER
687 select PM_GENERIC_DOMAINS if PM
690 Support for Renesas ARM SoC platforms using a non-multiplatform
691 kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
697 select ARCH_MAY_HAVE_PC_FDC
698 select ARCH_SPARSEMEM_ENABLE
699 select ARCH_USES_GETTIMEOFFSET
703 select HAVE_PATA_PLATFORM
705 select NEED_MACH_IO_H
706 select NEED_MACH_MEMORY_H
710 On the Acorn Risc-PC, Linux can support the internal IDE disk and
711 CD-ROM interface, serial and parallel port, and the floppy drive.
715 select ARCH_HAS_CPUFREQ
717 select ARCH_REQUIRE_GPIOLIB
718 select ARCH_SPARSEMEM_ENABLE
723 select GENERIC_CLOCKEVENTS
726 select NEED_MACH_MEMORY_H
729 Support for StrongARM 11x0 based boards.
732 bool "Samsung S3C24XX SoCs"
733 select ARCH_HAS_CPUFREQ
734 select ARCH_REQUIRE_GPIOLIB
737 select CLKSRC_SAMSUNG_PWM
738 select GENERIC_CLOCKEVENTS
740 select HAVE_S3C2410_I2C if I2C
741 select HAVE_S3C2410_WATCHDOG if WATCHDOG
742 select HAVE_S3C_RTC if RTC_CLASS
743 select MULTI_IRQ_HANDLER
744 select NEED_MACH_IO_H
747 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
748 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
749 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
750 Samsung SMDK2410 development board (and derivatives).
753 bool "Samsung S3C64XX"
754 select ARCH_HAS_CPUFREQ
755 select ARCH_REQUIRE_GPIOLIB
760 select CLKSRC_SAMSUNG_PWM
763 select GENERIC_CLOCKEVENTS
765 select HAVE_S3C2410_I2C if I2C
766 select HAVE_S3C2410_WATCHDOG if WATCHDOG
770 select PM_GENERIC_DOMAINS if PM
772 select S3C_GPIO_TRACK
774 select SAMSUNG_WAKEMASK
775 select SAMSUNG_WDT_RESET
777 Samsung S3C64XX series based systems
780 bool "Samsung S5P6440 S5P6450"
783 select CLKSRC_SAMSUNG_PWM
785 select GENERIC_CLOCKEVENTS
787 select HAVE_S3C2410_I2C if I2C
788 select HAVE_S3C2410_WATCHDOG if WATCHDOG
789 select HAVE_S3C_RTC if RTC_CLASS
790 select NEED_MACH_GPIO_H
792 select SAMSUNG_WDT_RESET
794 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
798 bool "Samsung S5PC100"
799 select ARCH_REQUIRE_GPIOLIB
802 select CLKSRC_SAMSUNG_PWM
804 select GENERIC_CLOCKEVENTS
806 select HAVE_S3C2410_I2C if I2C
807 select HAVE_S3C2410_WATCHDOG if WATCHDOG
808 select HAVE_S3C_RTC if RTC_CLASS
809 select NEED_MACH_GPIO_H
811 select SAMSUNG_WDT_RESET
813 Samsung S5PC100 series based systems
816 bool "Samsung S5PV210/S5PC110"
817 select ARCH_HAS_CPUFREQ
818 select ARCH_HAS_HOLES_MEMORYMODEL
819 select ARCH_SPARSEMEM_ENABLE
822 select CLKSRC_SAMSUNG_PWM
824 select GENERIC_CLOCKEVENTS
826 select HAVE_S3C2410_I2C if I2C
827 select HAVE_S3C2410_WATCHDOG if WATCHDOG
828 select HAVE_S3C_RTC if RTC_CLASS
829 select NEED_MACH_GPIO_H
830 select NEED_MACH_MEMORY_H
833 Samsung S5PV210/S5PC110 series based systems
836 bool "Samsung EXYNOS"
837 select ARCH_HAS_CPUFREQ
838 select ARCH_HAS_HOLES_MEMORYMODEL
839 select ARCH_REQUIRE_GPIOLIB
840 select ARCH_SPARSEMEM_ENABLE
844 select GENERIC_CLOCKEVENTS
845 select HAVE_S3C2410_I2C if I2C
846 select HAVE_S3C2410_WATCHDOG if WATCHDOG
847 select HAVE_S3C_RTC if RTC_CLASS
848 select NEED_MACH_MEMORY_H
852 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
856 select ARCH_HAS_HOLES_MEMORYMODEL
857 select ARCH_REQUIRE_GPIOLIB
859 select GENERIC_ALLOCATOR
860 select GENERIC_CLOCKEVENTS
861 select GENERIC_IRQ_CHIP
867 Support for TI's DaVinci platform.
872 select ARCH_HAS_CPUFREQ
873 select ARCH_HAS_HOLES_MEMORYMODEL
875 select ARCH_REQUIRE_GPIOLIB
878 select GENERIC_CLOCKEVENTS
879 select GENERIC_IRQ_CHIP
882 select NEED_MACH_IO_H if PCCARD
883 select NEED_MACH_MEMORY_H
885 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
889 menu "Multiple platform selection"
890 depends on ARCH_MULTIPLATFORM
892 comment "CPU Core family selection"
895 bool "ARMv4 based platforms (FA526)"
896 depends on !ARCH_MULTI_V6_V7
897 select ARCH_MULTI_V4_V5
900 config ARCH_MULTI_V4T
901 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
902 depends on !ARCH_MULTI_V6_V7
903 select ARCH_MULTI_V4_V5
904 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
905 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
906 CPU_ARM925T || CPU_ARM940T)
909 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
910 depends on !ARCH_MULTI_V6_V7
911 select ARCH_MULTI_V4_V5
912 select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \
913 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
914 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
916 config ARCH_MULTI_V4_V5
920 bool "ARMv6 based platforms (ARM11)"
921 select ARCH_MULTI_V6_V7
925 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
927 select ARCH_MULTI_V6_V7
931 config ARCH_MULTI_V6_V7
933 select MIGHT_HAVE_CACHE_L2X0
935 config ARCH_MULTI_CPU_AUTO
936 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
942 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
946 select HAVE_ARM_ARCH_TIMER
949 # This is sorted alphabetically by mach-* pathname. However, plat-*
950 # Kconfigs may be included either alphabetically (according to the
951 # plat- suffix) or along side the corresponding mach-* source.
953 source "arch/arm/mach-mvebu/Kconfig"
955 source "arch/arm/mach-at91/Kconfig"
957 source "arch/arm/mach-bcm/Kconfig"
959 source "arch/arm/mach-berlin/Kconfig"
961 source "arch/arm/mach-clps711x/Kconfig"
963 source "arch/arm/mach-cns3xxx/Kconfig"
965 source "arch/arm/mach-davinci/Kconfig"
967 source "arch/arm/mach-dove/Kconfig"
969 source "arch/arm/mach-ep93xx/Kconfig"
971 source "arch/arm/mach-footbridge/Kconfig"
973 source "arch/arm/mach-gemini/Kconfig"
975 source "arch/arm/mach-highbank/Kconfig"
977 source "arch/arm/mach-hisi/Kconfig"
979 source "arch/arm/mach-integrator/Kconfig"
981 source "arch/arm/mach-iop32x/Kconfig"
983 source "arch/arm/mach-iop33x/Kconfig"
985 source "arch/arm/mach-iop13xx/Kconfig"
987 source "arch/arm/mach-ixp4xx/Kconfig"
989 source "arch/arm/mach-keystone/Kconfig"
991 source "arch/arm/mach-kirkwood/Kconfig"
993 source "arch/arm/mach-ks8695/Kconfig"
995 source "arch/arm/mach-msm/Kconfig"
997 source "arch/arm/mach-moxart/Kconfig"
999 source "arch/arm/mach-mv78xx0/Kconfig"
1001 source "arch/arm/mach-imx/Kconfig"
1003 source "arch/arm/mach-mxs/Kconfig"
1005 source "arch/arm/mach-netx/Kconfig"
1007 source "arch/arm/mach-nomadik/Kconfig"
1009 source "arch/arm/mach-nspire/Kconfig"
1011 source "arch/arm/plat-omap/Kconfig"
1013 source "arch/arm/mach-omap1/Kconfig"
1015 source "arch/arm/mach-omap2/Kconfig"
1017 source "arch/arm/mach-orion5x/Kconfig"
1019 source "arch/arm/mach-picoxcell/Kconfig"
1021 source "arch/arm/mach-pxa/Kconfig"
1022 source "arch/arm/plat-pxa/Kconfig"
1024 source "arch/arm/mach-mmp/Kconfig"
1026 source "arch/arm/mach-qcom/Kconfig"
1028 source "arch/arm/mach-realview/Kconfig"
1030 source "arch/arm/mach-rockchip/Kconfig"
1032 source "arch/arm/mach-sa1100/Kconfig"
1034 source "arch/arm/plat-samsung/Kconfig"
1036 source "arch/arm/mach-socfpga/Kconfig"
1038 source "arch/arm/mach-spear/Kconfig"
1040 source "arch/arm/mach-sti/Kconfig"
1042 source "arch/arm/mach-s3c24xx/Kconfig"
1044 source "arch/arm/mach-s3c64xx/Kconfig"
1046 source "arch/arm/mach-s5p64x0/Kconfig"
1048 source "arch/arm/mach-s5pc100/Kconfig"
1050 source "arch/arm/mach-s5pv210/Kconfig"
1052 source "arch/arm/mach-exynos/Kconfig"
1054 source "arch/arm/mach-shmobile/Kconfig"
1056 source "arch/arm/mach-sunxi/Kconfig"
1058 source "arch/arm/mach-prima2/Kconfig"
1060 source "arch/arm/mach-tegra/Kconfig"
1062 source "arch/arm/mach-u300/Kconfig"
1064 source "arch/arm/mach-ux500/Kconfig"
1066 source "arch/arm/mach-versatile/Kconfig"
1068 source "arch/arm/mach-vexpress/Kconfig"
1069 source "arch/arm/plat-versatile/Kconfig"
1071 source "arch/arm/mach-vt8500/Kconfig"
1073 source "arch/arm/mach-w90x900/Kconfig"
1075 source "arch/arm/mach-zynq/Kconfig"
1077 # Definitions to make life easier
1083 select GENERIC_CLOCKEVENTS
1089 select GENERIC_IRQ_CHIP
1092 config PLAT_ORION_LEGACY
1099 config PLAT_VERSATILE
1102 config ARM_TIMER_SP804
1105 select CLKSRC_OF if OF
1107 source "arch/arm/firmware/Kconfig"
1109 source arch/arm/mm/Kconfig
1113 default 16 if ARCH_EP93XX
1117 bool "Enable iWMMXt support" if !CPU_PJ4
1118 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1119 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1121 Enable support for iWMMXt context switching at run time if
1122 running on a CPU that supports it.
1124 config MULTI_IRQ_HANDLER
1127 Allow each machine to specify it's own IRQ handler at run time.
1130 source "arch/arm/Kconfig-nommu"
1133 config PJ4B_ERRATA_4742
1134 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1135 depends on CPU_PJ4B && MACH_ARMADA_370
1138 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1139 Event (WFE) IDLE states, a specific timing sensitivity exists between
1140 the retiring WFI/WFE instructions and the newly issued subsequent
1141 instructions. This sensitivity can result in a CPU hang scenario.
1143 The software must insert either a Data Synchronization Barrier (DSB)
1144 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1147 config ARM_ERRATA_326103
1148 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1151 Executing a SWP instruction to read-only memory does not set bit 11
1152 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1153 treat the access as a read, preventing a COW from occurring and
1154 causing the faulting task to livelock.
1156 config ARM_ERRATA_411920
1157 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1158 depends on CPU_V6 || CPU_V6K
1160 Invalidation of the Instruction Cache operation can
1161 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1162 It does not affect the MPCore. This option enables the ARM Ltd.
1163 recommended workaround.
1165 config ARM_ERRATA_430973
1166 bool "ARM errata: Stale prediction on replaced interworking branch"
1169 This option enables the workaround for the 430973 Cortex-A8
1170 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1171 interworking branch is replaced with another code sequence at the
1172 same virtual address, whether due to self-modifying code or virtual
1173 to physical address re-mapping, Cortex-A8 does not recover from the
1174 stale interworking branch prediction. This results in Cortex-A8
1175 executing the new code sequence in the incorrect ARM or Thumb state.
1176 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1177 and also flushes the branch target cache at every context switch.
1178 Note that setting specific bits in the ACTLR register may not be
1179 available in non-secure mode.
1181 config ARM_ERRATA_458693
1182 bool "ARM errata: Processor deadlock when a false hazard is created"
1184 depends on !ARCH_MULTIPLATFORM
1186 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1187 erratum. For very specific sequences of memory operations, it is
1188 possible for a hazard condition intended for a cache line to instead
1189 be incorrectly associated with a different cache line. This false
1190 hazard might then cause a processor deadlock. The workaround enables
1191 the L1 caching of the NEON accesses and disables the PLD instruction
1192 in the ACTLR register. Note that setting specific bits in the ACTLR
1193 register may not be available in non-secure mode.
1195 config ARM_ERRATA_460075
1196 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1198 depends on !ARCH_MULTIPLATFORM
1200 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1201 erratum. Any asynchronous access to the L2 cache may encounter a
1202 situation in which recent store transactions to the L2 cache are lost
1203 and overwritten with stale memory contents from external memory. The
1204 workaround disables the write-allocate mode for the L2 cache via the
1205 ACTLR register. Note that setting specific bits in the ACTLR register
1206 may not be available in non-secure mode.
1208 config ARM_ERRATA_742230
1209 bool "ARM errata: DMB operation may be faulty"
1210 depends on CPU_V7 && SMP
1211 depends on !ARCH_MULTIPLATFORM
1213 This option enables the workaround for the 742230 Cortex-A9
1214 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1215 between two write operations may not ensure the correct visibility
1216 ordering of the two writes. This workaround sets a specific bit in
1217 the diagnostic register of the Cortex-A9 which causes the DMB
1218 instruction to behave as a DSB, ensuring the correct behaviour of
1221 config ARM_ERRATA_742231
1222 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1223 depends on CPU_V7 && SMP
1224 depends on !ARCH_MULTIPLATFORM
1226 This option enables the workaround for the 742231 Cortex-A9
1227 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1228 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1229 accessing some data located in the same cache line, may get corrupted
1230 data due to bad handling of the address hazard when the line gets
1231 replaced from one of the CPUs at the same time as another CPU is
1232 accessing it. This workaround sets specific bits in the diagnostic
1233 register of the Cortex-A9 which reduces the linefill issuing
1234 capabilities of the processor.
1236 config PL310_ERRATA_588369
1237 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1238 depends on CACHE_L2X0
1240 The PL310 L2 cache controller implements three types of Clean &
1241 Invalidate maintenance operations: by Physical Address
1242 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1243 They are architecturally defined to behave as the execution of a
1244 clean operation followed immediately by an invalidate operation,
1245 both performing to the same memory location. This functionality
1246 is not correctly implemented in PL310 as clean lines are not
1247 invalidated as a result of these operations.
1249 config ARM_ERRATA_643719
1250 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1251 depends on CPU_V7 && SMP
1253 This option enables the workaround for the 643719 Cortex-A9 (prior to
1254 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1255 register returns zero when it should return one. The workaround
1256 corrects this value, ensuring cache maintenance operations which use
1257 it behave as intended and avoiding data corruption.
1259 config ARM_ERRATA_720789
1260 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1263 This option enables the workaround for the 720789 Cortex-A9 (prior to
1264 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1265 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1266 As a consequence of this erratum, some TLB entries which should be
1267 invalidated are not, resulting in an incoherency in the system page
1268 tables. The workaround changes the TLB flushing routines to invalidate
1269 entries regardless of the ASID.
1271 config PL310_ERRATA_727915
1272 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1273 depends on CACHE_L2X0
1275 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1276 operation (offset 0x7FC). This operation runs in background so that
1277 PL310 can handle normal accesses while it is in progress. Under very
1278 rare circumstances, due to this erratum, write data can be lost when
1279 PL310 treats a cacheable write transaction during a Clean &
1280 Invalidate by Way operation.
1282 config ARM_ERRATA_743622
1283 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1285 depends on !ARCH_MULTIPLATFORM
1287 This option enables the workaround for the 743622 Cortex-A9
1288 (r2p*) erratum. Under very rare conditions, a faulty
1289 optimisation in the Cortex-A9 Store Buffer may lead to data
1290 corruption. This workaround sets a specific bit in the diagnostic
1291 register of the Cortex-A9 which disables the Store Buffer
1292 optimisation, preventing the defect from occurring. This has no
1293 visible impact on the overall performance or power consumption of the
1296 config ARM_ERRATA_751472
1297 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1299 depends on !ARCH_MULTIPLATFORM
1301 This option enables the workaround for the 751472 Cortex-A9 (prior
1302 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1303 completion of a following broadcasted operation if the second
1304 operation is received by a CPU before the ICIALLUIS has completed,
1305 potentially leading to corrupted entries in the cache or TLB.
1307 config PL310_ERRATA_753970
1308 bool "PL310 errata: cache sync operation may be faulty"
1309 depends on CACHE_PL310
1311 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1313 Under some condition the effect of cache sync operation on
1314 the store buffer still remains when the operation completes.
1315 This means that the store buffer is always asked to drain and
1316 this prevents it from merging any further writes. The workaround
1317 is to replace the normal offset of cache sync operation (0x730)
1318 by another offset targeting an unmapped PL310 register 0x740.
1319 This has the same effect as the cache sync operation: store buffer
1320 drain and waiting for all buffers empty.
1322 config ARM_ERRATA_754322
1323 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1326 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1327 r3p*) erratum. A speculative memory access may cause a page table walk
1328 which starts prior to an ASID switch but completes afterwards. This
1329 can populate the micro-TLB with a stale entry which may be hit with
1330 the new ASID. This workaround places two dsb instructions in the mm
1331 switching code so that no page table walks can cross the ASID switch.
1333 config ARM_ERRATA_754327
1334 bool "ARM errata: no automatic Store Buffer drain"
1335 depends on CPU_V7 && SMP
1337 This option enables the workaround for the 754327 Cortex-A9 (prior to
1338 r2p0) erratum. The Store Buffer does not have any automatic draining
1339 mechanism and therefore a livelock may occur if an external agent
1340 continuously polls a memory location waiting to observe an update.
1341 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1342 written polling loops from denying visibility of updates to memory.
1344 config ARM_ERRATA_364296
1345 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1348 This options enables the workaround for the 364296 ARM1136
1349 r0p2 erratum (possible cache data corruption with
1350 hit-under-miss enabled). It sets the undocumented bit 31 in
1351 the auxiliary control register and the FI bit in the control
1352 register, thus disabling hit-under-miss without putting the
1353 processor into full low interrupt latency mode. ARM11MPCore
1356 config ARM_ERRATA_764369
1357 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1358 depends on CPU_V7 && SMP
1360 This option enables the workaround for erratum 764369
1361 affecting Cortex-A9 MPCore with two or more processors (all
1362 current revisions). Under certain timing circumstances, a data
1363 cache line maintenance operation by MVA targeting an Inner
1364 Shareable memory region may fail to proceed up to either the
1365 Point of Coherency or to the Point of Unification of the
1366 system. This workaround adds a DSB instruction before the
1367 relevant cache maintenance functions and sets a specific bit
1368 in the diagnostic control register of the SCU.
1370 config PL310_ERRATA_769419
1371 bool "PL310 errata: no automatic Store Buffer drain"
1372 depends on CACHE_L2X0
1374 On revisions of the PL310 prior to r3p2, the Store Buffer does
1375 not automatically drain. This can cause normal, non-cacheable
1376 writes to be retained when the memory system is idle, leading
1377 to suboptimal I/O performance for drivers using coherent DMA.
1378 This option adds a write barrier to the cpu_idle loop so that,
1379 on systems with an outer cache, the store buffer is drained
1382 config ARM_ERRATA_775420
1383 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1386 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1387 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1388 operation aborts with MMU exception, it might cause the processor
1389 to deadlock. This workaround puts DSB before executing ISB if
1390 an abort may occur on cache maintenance.
1392 config ARM_ERRATA_798181
1393 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1394 depends on CPU_V7 && SMP
1396 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1397 adequately shooting down all use of the old entries. This
1398 option enables the Linux kernel workaround for this erratum
1399 which sends an IPI to the CPUs that are running the same ASID
1400 as the one being invalidated.
1402 config ARM_ERRATA_773022
1403 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1406 This option enables the workaround for the 773022 Cortex-A15
1407 (up to r0p4) erratum. In certain rare sequences of code, the
1408 loop buffer may deliver incorrect instructions. This
1409 workaround disables the loop buffer to avoid the erratum.
1413 source "arch/arm/common/Kconfig"
1423 Find out whether you have ISA slots on your motherboard. ISA is the
1424 name of a bus system, i.e. the way the CPU talks to the other stuff
1425 inside your box. Other bus systems are PCI, EISA, MicroChannel
1426 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1427 newer boards don't support it. If you have ISA, say Y, otherwise N.
1429 # Select ISA DMA controller support
1434 # Select ISA DMA interface
1439 bool "PCI support" if MIGHT_HAVE_PCI
1441 Find out whether you have a PCI motherboard. PCI is the name of a
1442 bus system, i.e. the way the CPU talks to the other stuff inside
1443 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1444 VESA. If you have PCI, say Y, otherwise N.
1450 config PCI_NANOENGINE
1451 bool "BSE nanoEngine PCI support"
1452 depends on SA1100_NANOENGINE
1454 Enable PCI on the BSE nanoEngine board.
1459 config PCI_HOST_ITE8152
1461 depends on PCI && MACH_ARMCORE
1465 source "drivers/pci/Kconfig"
1466 source "drivers/pci/pcie/Kconfig"
1468 source "drivers/pcmcia/Kconfig"
1472 menu "Kernel Features"
1477 This option should be selected by machines which have an SMP-
1480 The only effect of this option is to make the SMP-related
1481 options available to the user for configuration.
1484 bool "Symmetric Multi-Processing"
1485 depends on CPU_V6K || CPU_V7
1486 depends on GENERIC_CLOCKEVENTS
1488 depends on MMU || ARM_MPU
1490 This enables support for systems with more than one CPU. If you have
1491 a system with only one CPU, say N. If you have a system with more
1492 than one CPU, say Y.
1494 If you say N here, the kernel will run on uni- and multiprocessor
1495 machines, but will use only one CPU of a multiprocessor machine. If
1496 you say Y here, the kernel will run on many, but not all,
1497 uniprocessor machines. On a uniprocessor machine, the kernel
1498 will run faster if you say N here.
1500 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1501 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1502 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1504 If you don't know what to do here, say N.
1507 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1508 depends on SMP && !XIP_KERNEL && MMU
1511 SMP kernels contain instructions which fail on non-SMP processors.
1512 Enabling this option allows the kernel to modify itself to make
1513 these instructions safe. Disabling it allows about 1K of space
1516 If you don't know what to do here, say Y.
1518 config ARM_CPU_TOPOLOGY
1519 bool "Support cpu topology definition"
1520 depends on SMP && CPU_V7
1523 Support ARM cpu topology definition. The MPIDR register defines
1524 affinity between processors which is then used to describe the cpu
1525 topology of an ARM System.
1528 bool "Multi-core scheduler support"
1529 depends on ARM_CPU_TOPOLOGY
1531 Multi-core scheduler support improves the CPU scheduler's decision
1532 making when dealing with multi-core CPU chips at a cost of slightly
1533 increased overhead in some places. If unsure say N here.
1536 bool "SMT scheduler support"
1537 depends on ARM_CPU_TOPOLOGY
1539 Improves the CPU scheduler's decision making when dealing with
1540 MultiThreading at a cost of slightly increased overhead in some
1541 places. If unsure say N here.
1546 This option enables support for the ARM system coherency unit
1548 config HAVE_ARM_ARCH_TIMER
1549 bool "Architected timer support"
1551 select ARM_ARCH_TIMER
1552 select GENERIC_CLOCKEVENTS
1554 This option enables support for the ARM architected timer
1559 select CLKSRC_OF if OF
1561 This options enables support for the ARM timer and watchdog unit
1564 bool "Multi-Cluster Power Management"
1565 depends on CPU_V7 && SMP
1567 This option provides the common power management infrastructure
1568 for (multi-)cluster based systems, such as big.LITTLE based
1572 bool "big.LITTLE support (Experimental)"
1573 depends on CPU_V7 && SMP
1576 This option enables support selections for the big.LITTLE
1577 system architecture.
1580 bool "big.LITTLE switcher support"
1581 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1583 select ARM_CPU_SUSPEND
1585 The big.LITTLE "switcher" provides the core functionality to
1586 transparently handle transition between a cluster of A15's
1587 and a cluster of A7's in a big.LITTLE system.
1589 config BL_SWITCHER_DUMMY_IF
1590 tristate "Simple big.LITTLE switcher user interface"
1591 depends on BL_SWITCHER && DEBUG_KERNEL
1593 This is a simple and dummy char dev interface to control
1594 the big.LITTLE switcher core code. It is meant for
1595 debugging purposes only.
1598 prompt "Memory split"
1602 Select the desired split between kernel and user memory.
1604 If you are not absolutely sure what you are doing, leave this
1608 bool "3G/1G user/kernel split"
1610 bool "2G/2G user/kernel split"
1612 bool "1G/3G user/kernel split"
1617 default PHYS_OFFSET if !MMU
1618 default 0x40000000 if VMSPLIT_1G
1619 default 0x80000000 if VMSPLIT_2G
1623 int "Maximum number of CPUs (2-32)"
1629 bool "Support for hot-pluggable CPUs"
1632 Say Y here to experiment with turning CPUs off and on. CPUs
1633 can be controlled through /sys/devices/system/cpu.
1636 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1639 Say Y here if you want Linux to communicate with system firmware
1640 implementing the PSCI specification for CPU-centric power
1641 management operations described in ARM document number ARM DEN
1642 0022A ("Power State Coordination Interface System Software on
1645 # The GPIO number here must be sorted by descending number. In case of
1646 # a multiplatform kernel, we just want the highest value required by the
1647 # selected platforms.
1650 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1651 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX
1652 default 392 if ARCH_U8500
1653 default 352 if ARCH_VT8500
1654 default 288 if ARCH_SUNXI
1655 default 264 if MACH_H4700
1658 Maximum number of GPIOs in the system.
1660 If unsure, leave the default value.
1662 source kernel/Kconfig.preempt
1666 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1667 ARCH_S5PV210 || ARCH_EXYNOS4
1668 default AT91_TIMER_HZ if ARCH_AT91
1669 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1673 depends on HZ_FIXED = 0
1674 prompt "Timer frequency"
1698 default HZ_FIXED if HZ_FIXED != 0
1699 default 100 if HZ_100
1700 default 200 if HZ_200
1701 default 250 if HZ_250
1702 default 300 if HZ_300
1703 default 500 if HZ_500
1707 def_bool HIGH_RES_TIMERS
1709 config THUMB2_KERNEL
1710 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1711 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1712 default y if CPU_THUMBONLY
1714 select ARM_ASM_UNIFIED
1717 By enabling this option, the kernel will be compiled in
1718 Thumb-2 mode. A compiler/assembler that understand the unified
1719 ARM-Thumb syntax is needed.
1723 config THUMB2_AVOID_R_ARM_THM_JUMP11
1724 bool "Work around buggy Thumb-2 short branch relocations in gas"
1725 depends on THUMB2_KERNEL && MODULES
1728 Various binutils versions can resolve Thumb-2 branches to
1729 locally-defined, preemptible global symbols as short-range "b.n"
1730 branch instructions.
1732 This is a problem, because there's no guarantee the final
1733 destination of the symbol, or any candidate locations for a
1734 trampoline, are within range of the branch. For this reason, the
1735 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1736 relocation in modules at all, and it makes little sense to add
1739 The symptom is that the kernel fails with an "unsupported
1740 relocation" error when loading some modules.
1742 Until fixed tools are available, passing
1743 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1744 code which hits this problem, at the cost of a bit of extra runtime
1745 stack usage in some cases.
1747 The problem is described in more detail at:
1748 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1750 Only Thumb-2 kernels are affected.
1752 Unless you are sure your tools don't have this problem, say Y.
1754 config ARM_ASM_UNIFIED
1758 bool "Use the ARM EABI to compile the kernel"
1760 This option allows for the kernel to be compiled using the latest
1761 ARM ABI (aka EABI). This is only useful if you are using a user
1762 space environment that is also compiled with EABI.
1764 Since there are major incompatibilities between the legacy ABI and
1765 EABI, especially with regard to structure member alignment, this
1766 option also changes the kernel syscall calling convention to
1767 disambiguate both ABIs and allow for backward compatibility support
1768 (selected with CONFIG_OABI_COMPAT).
1770 To use this you need GCC version 4.0.0 or later.
1773 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1774 depends on AEABI && !THUMB2_KERNEL
1776 This option preserves the old syscall interface along with the
1777 new (ARM EABI) one. It also provides a compatibility layer to
1778 intercept syscalls that have structure arguments which layout
1779 in memory differs between the legacy ABI and the new ARM EABI
1780 (only for non "thumb" binaries). This option adds a tiny
1781 overhead to all syscalls and produces a slightly larger kernel.
1783 The seccomp filter system will not be available when this is
1784 selected, since there is no way yet to sensibly distinguish
1785 between calling conventions during filtering.
1787 If you know you'll be using only pure EABI user space then you
1788 can say N here. If this option is not selected and you attempt
1789 to execute a legacy ABI binary then the result will be
1790 UNPREDICTABLE (in fact it can be predicted that it won't work
1791 at all). If in doubt say N.
1793 config ARCH_HAS_HOLES_MEMORYMODEL
1796 config ARCH_SPARSEMEM_ENABLE
1799 config ARCH_SPARSEMEM_DEFAULT
1800 def_bool ARCH_SPARSEMEM_ENABLE
1802 config ARCH_SELECT_MEMORY_MODEL
1803 def_bool ARCH_SPARSEMEM_ENABLE
1805 config HAVE_ARCH_PFN_VALID
1806 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1809 bool "High Memory Support"
1812 The address space of ARM processors is only 4 Gigabytes large
1813 and it has to accommodate user address space, kernel address
1814 space as well as some memory mapped IO. That means that, if you
1815 have a large amount of physical memory and/or IO, not all of the
1816 memory can be "permanently mapped" by the kernel. The physical
1817 memory that is not permanently mapped is called "high memory".
1819 Depending on the selected kernel/user memory split, minimum
1820 vmalloc space and actual amount of RAM, you may not need this
1821 option which should result in a slightly faster kernel.
1826 bool "Allocate 2nd-level pagetables from highmem"
1829 config HW_PERF_EVENTS
1830 bool "Enable hardware performance counter support for perf events"
1831 depends on PERF_EVENTS
1834 Enable hardware performance counter support for perf events. If
1835 disabled, perf events will use software events only.
1837 config SYS_SUPPORTS_HUGETLBFS
1841 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1845 config ARCH_WANT_GENERAL_HUGETLB
1850 config FORCE_MAX_ZONEORDER
1851 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1852 range 11 64 if ARCH_SHMOBILE_LEGACY
1853 default "12" if SOC_AM33XX
1854 default "9" if SA1111 || ARCH_EFM32
1857 The kernel memory allocator divides physically contiguous memory
1858 blocks into "zones", where each zone is a power of two number of
1859 pages. This option selects the largest power of two that the kernel
1860 keeps in the memory allocator. If you need to allocate very large
1861 blocks of physically contiguous memory, then you may need to
1862 increase this value.
1864 This config option is actually maximum order plus one. For example,
1865 a value of 11 means that the largest free memory block is 2^10 pages.
1867 config ALIGNMENT_TRAP
1869 depends on CPU_CP15_MMU
1870 default y if !ARCH_EBSA110
1871 select HAVE_PROC_CPU if PROC_FS
1873 ARM processors cannot fetch/store information which is not
1874 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1875 address divisible by 4. On 32-bit ARM processors, these non-aligned
1876 fetch/store instructions will be emulated in software if you say
1877 here, which has a severe performance impact. This is necessary for
1878 correct operation of some network protocols. With an IP-only
1879 configuration it is safe to say N, otherwise say Y.
1881 config UACCESS_WITH_MEMCPY
1882 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1884 default y if CPU_FEROCEON
1886 Implement faster copy_to_user and clear_user methods for CPU
1887 cores where a 8-word STM instruction give significantly higher
1888 memory write throughput than a sequence of individual 32bit stores.
1890 A possible side effect is a slight increase in scheduling latency
1891 between threads sharing the same address space if they invoke
1892 such copy operations with large buffers.
1894 However, if the CPU data cache is using a write-allocate mode,
1895 this option is unlikely to provide any performance gain.
1899 prompt "Enable seccomp to safely compute untrusted bytecode"
1901 This kernel feature is useful for number crunching applications
1902 that may need to compute untrusted bytecode during their
1903 execution. By using pipes or other transports made available to
1904 the process as file descriptors supporting the read/write
1905 syscalls, it's possible to isolate those applications in
1906 their own address space using seccomp. Once seccomp is
1907 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1908 and the task is only allowed to execute a few safe syscalls
1909 defined by each seccomp mode.
1922 bool "Xen guest support on ARM (EXPERIMENTAL)"
1923 depends on ARM && AEABI && OF
1924 depends on CPU_V7 && !CPU_V6
1925 depends on !GENERIC_ATOMIC64
1929 select ARCH_DMA_ADDR_T_64BIT
1931 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1938 bool "Flattened Device Tree support"
1941 select OF_EARLY_FLATTREE
1942 select OF_RESERVED_MEM
1944 Include support for flattened device tree machine descriptions.
1947 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1950 This is the traditional way of passing data to the kernel at boot
1951 time. If you are solely relying on the flattened device tree (or
1952 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1953 to remove ATAGS support from your kernel binary. If unsure,
1956 config DEPRECATED_PARAM_STRUCT
1957 bool "Provide old way to pass kernel parameters"
1960 This was deprecated in 2001 and announced to live on for 5 years.
1961 Some old boot loaders still use this way.
1963 # Compressed boot loader in ROM. Yes, we really want to ask about
1964 # TEXT and BSS so we preserve their values in the config files.
1965 config ZBOOT_ROM_TEXT
1966 hex "Compressed ROM boot loader base address"
1969 The physical address at which the ROM-able zImage is to be
1970 placed in the target. Platforms which normally make use of
1971 ROM-able zImage formats normally set this to a suitable
1972 value in their defconfig file.
1974 If ZBOOT_ROM is not enabled, this has no effect.
1976 config ZBOOT_ROM_BSS
1977 hex "Compressed ROM boot loader BSS address"
1980 The base address of an area of read/write memory in the target
1981 for the ROM-able zImage which must be available while the
1982 decompressor is running. It must be large enough to hold the
1983 entire decompressed kernel plus an additional 128 KiB.
1984 Platforms which normally make use of ROM-able zImage formats
1985 normally set this to a suitable value in their defconfig file.
1987 If ZBOOT_ROM is not enabled, this has no effect.
1990 bool "Compressed boot loader in ROM/flash"
1991 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1992 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1994 Say Y here if you intend to execute your compressed kernel image
1995 (zImage) directly from ROM or flash. If unsure, say N.
1998 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1999 depends on ZBOOT_ROM && ARCH_SH7372
2000 default ZBOOT_ROM_NONE
2002 Include experimental SD/MMC loading code in the ROM-able zImage.
2003 With this enabled it is possible to write the ROM-able zImage
2004 kernel image to an MMC or SD card and boot the kernel straight
2005 from the reset vector. At reset the processor Mask ROM will load
2006 the first part of the ROM-able zImage which in turn loads the
2007 rest the kernel image to RAM.
2009 config ZBOOT_ROM_NONE
2010 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
2012 Do not load image from SD or MMC
2014 config ZBOOT_ROM_MMCIF
2015 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
2017 Load image from MMCIF hardware block.
2019 config ZBOOT_ROM_SH_MOBILE_SDHI
2020 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
2022 Load image from SDHI hardware block
2026 config ARM_APPENDED_DTB
2027 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
2030 With this option, the boot code will look for a device tree binary
2031 (DTB) appended to zImage
2032 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
2034 This is meant as a backward compatibility convenience for those
2035 systems with a bootloader that can't be upgraded to accommodate
2036 the documented boot protocol using a device tree.
2038 Beware that there is very little in terms of protection against
2039 this option being confused by leftover garbage in memory that might
2040 look like a DTB header after a reboot if no actual DTB is appended
2041 to zImage. Do not leave this option active in a production kernel
2042 if you don't intend to always append a DTB. Proper passing of the
2043 location into r2 of a bootloader provided DTB is always preferable
2046 config ARM_ATAG_DTB_COMPAT
2047 bool "Supplement the appended DTB with traditional ATAG information"
2048 depends on ARM_APPENDED_DTB
2050 Some old bootloaders can't be updated to a DTB capable one, yet
2051 they provide ATAGs with memory configuration, the ramdisk address,
2052 the kernel cmdline string, etc. Such information is dynamically
2053 provided by the bootloader and can't always be stored in a static
2054 DTB. To allow a device tree enabled kernel to be used with such
2055 bootloaders, this option allows zImage to extract the information
2056 from the ATAG list and store it at run time into the appended DTB.
2059 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2060 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2062 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2063 bool "Use bootloader kernel arguments if available"
2065 Uses the command-line options passed by the boot loader instead of
2066 the device tree bootargs property. If the boot loader doesn't provide
2067 any, the device tree bootargs property will be used.
2069 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2070 bool "Extend with bootloader kernel arguments"
2072 The command-line arguments provided by the boot loader will be
2073 appended to the the device tree bootargs property.
2078 string "Default kernel command string"
2081 On some architectures (EBSA110 and CATS), there is currently no way
2082 for the boot loader to pass arguments to the kernel. For these
2083 architectures, you should supply some command-line options at build
2084 time by entering them here. As a minimum, you should specify the
2085 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2088 prompt "Kernel command line type" if CMDLINE != ""
2089 default CMDLINE_FROM_BOOTLOADER
2092 config CMDLINE_FROM_BOOTLOADER
2093 bool "Use bootloader kernel arguments if available"
2095 Uses the command-line options passed by the boot loader. If
2096 the boot loader doesn't provide any, the default kernel command
2097 string provided in CMDLINE will be used.
2099 config CMDLINE_EXTEND
2100 bool "Extend bootloader kernel arguments"
2102 The command-line arguments provided by the boot loader will be
2103 appended to the default kernel command string.
2105 config CMDLINE_FORCE
2106 bool "Always use the default kernel command string"
2108 Always use the default kernel command string, even if the boot
2109 loader passes other arguments to the kernel.
2110 This is useful if you cannot or don't want to change the
2111 command-line options your boot loader passes to the kernel.
2115 bool "Kernel Execute-In-Place from ROM"
2116 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
2118 Execute-In-Place allows the kernel to run from non-volatile storage
2119 directly addressable by the CPU, such as NOR flash. This saves RAM
2120 space since the text section of the kernel is not loaded from flash
2121 to RAM. Read-write sections, such as the data section and stack,
2122 are still copied to RAM. The XIP kernel is not compressed since
2123 it has to run directly from flash, so it will take more space to
2124 store it. The flash address used to link the kernel object files,
2125 and for storing it, is configuration dependent. Therefore, if you
2126 say Y here, you must know the proper physical address where to
2127 store the kernel image depending on your own flash memory usage.
2129 Also note that the make target becomes "make xipImage" rather than
2130 "make zImage" or "make Image". The final kernel binary to put in
2131 ROM memory will be arch/arm/boot/xipImage.
2135 config XIP_PHYS_ADDR
2136 hex "XIP Kernel Physical Location"
2137 depends on XIP_KERNEL
2138 default "0x00080000"
2140 This is the physical address in your flash memory the kernel will
2141 be linked for and stored to. This address is dependent on your
2145 bool "Kexec system call (EXPERIMENTAL)"
2146 depends on (!SMP || PM_SLEEP_SMP)
2148 kexec is a system call that implements the ability to shutdown your
2149 current kernel, and to start another kernel. It is like a reboot
2150 but it is independent of the system firmware. And like a reboot
2151 you can start any kernel with it, not just Linux.
2153 It is an ongoing process to be certain the hardware in a machine
2154 is properly shutdown, so do not be surprised if this code does not
2155 initially work for you.
2158 bool "Export atags in procfs"
2159 depends on ATAGS && KEXEC
2162 Should the atags used to boot the kernel be exported in an "atags"
2163 file in procfs. Useful with kexec.
2166 bool "Build kdump crash kernel (EXPERIMENTAL)"
2168 Generate crash dump after being started by kexec. This should
2169 be normally only set in special crash dump kernels which are
2170 loaded in the main kernel with kexec-tools into a specially
2171 reserved region and then later executed after a crash by
2172 kdump/kexec. The crash dump kernel must be compiled to a
2173 memory address not used by the main kernel
2175 For more details see Documentation/kdump/kdump.txt
2177 config AUTO_ZRELADDR
2178 bool "Auto calculation of the decompressed kernel image address"
2180 ZRELADDR is the physical address where the decompressed kernel
2181 image will be placed. If AUTO_ZRELADDR is selected, the address
2182 will be determined at run-time by masking the current IP with
2183 0xf8000000. This assumes the zImage being placed in the first 128MB
2184 from start of memory.
2188 menu "CPU Power Management"
2191 source "drivers/cpufreq/Kconfig"
2194 source "drivers/cpuidle/Kconfig"
2198 menu "Floating point emulation"
2200 comment "At least one emulation must be selected"
2203 bool "NWFPE math emulation"
2204 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2206 Say Y to include the NWFPE floating point emulator in the kernel.
2207 This is necessary to run most binaries. Linux does not currently
2208 support floating point hardware so you need to say Y here even if
2209 your machine has an FPA or floating point co-processor podule.
2211 You may say N here if you are going to load the Acorn FPEmulator
2212 early in the bootup.
2215 bool "Support extended precision"
2216 depends on FPE_NWFPE
2218 Say Y to include 80-bit support in the kernel floating-point
2219 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2220 Note that gcc does not generate 80-bit operations by default,
2221 so in most cases this option only enlarges the size of the
2222 floating point emulator without any good reason.
2224 You almost surely want to say N here.
2227 bool "FastFPE math emulation (EXPERIMENTAL)"
2228 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2230 Say Y here to include the FAST floating point emulator in the kernel.
2231 This is an experimental much faster emulator which now also has full
2232 precision for the mantissa. It does not support any exceptions.
2233 It is very simple, and approximately 3-6 times faster than NWFPE.
2235 It should be sufficient for most programs. It may be not suitable
2236 for scientific calculations, but you have to check this for yourself.
2237 If you do not feel you need a faster FP emulation you should better
2241 bool "VFP-format floating point maths"
2242 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2244 Say Y to include VFP support code in the kernel. This is needed
2245 if your hardware includes a VFP unit.
2247 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2248 release notes and additional status information.
2250 Say N if your target does not have VFP hardware.
2258 bool "Advanced SIMD (NEON) Extension support"
2259 depends on VFPv3 && CPU_V7
2261 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2264 config KERNEL_MODE_NEON
2265 bool "Support for NEON in kernel mode"
2266 depends on NEON && AEABI
2268 Say Y to include support for NEON in kernel mode.
2272 menu "Userspace binary formats"
2274 source "fs/Kconfig.binfmt"
2277 tristate "RISC OS personality"
2280 Say Y here to include the kernel code necessary if you want to run
2281 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2282 experimental; if this sounds frightening, say N and sleep in peace.
2283 You can also say M here to compile this support as a module (which
2284 will be called arthur).
2288 menu "Power management options"
2290 source "kernel/power/Kconfig"
2292 config ARCH_SUSPEND_POSSIBLE
2293 depends on !ARCH_S5PC100
2294 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2295 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2298 config ARM_CPU_SUSPEND
2303 source "net/Kconfig"
2305 source "drivers/Kconfig"
2309 source "arch/arm/Kconfig.debug"
2311 source "security/Kconfig"
2313 source "crypto/Kconfig"
2315 source "lib/Kconfig"
2317 source "arch/arm/kvm/Kconfig"