4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_MIGHT_HAVE_PC_PARPORT
9 select ARCH_SUPPORTS_ATOMIC_RMW
10 select ARCH_USE_BUILTIN_BSWAP
11 select ARCH_USE_CMPXCHG_LOCKREF
12 select ARCH_WANT_IPC_PARSE_VERSION
13 select BUILDTIME_EXTABLE_SORT if MMU
14 select CLONE_BACKWARDS
15 select CPU_PM if (SUSPEND || CPU_IDLE)
16 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
17 select GENERIC_ALLOCATOR
18 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
19 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
20 select GENERIC_IDLE_POLL_SETUP
21 select GENERIC_IRQ_PROBE
22 select GENERIC_IRQ_SHOW
23 select GENERIC_PCI_IOMAP
24 select GENERIC_SCHED_CLOCK
25 select GENERIC_SMP_IDLE_THREAD
26 select GENERIC_STRNCPY_FROM_USER
27 select GENERIC_STRNLEN_USER
28 select HANDLE_DOMAIN_IRQ
29 select HARDIRQS_SW_RESEND
30 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
31 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
33 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
34 select HAVE_ARCH_TRACEHOOK
36 select HAVE_CC_STACKPROTECTOR
37 select HAVE_CONTEXT_TRACKING
38 select HAVE_C_RECORDMCOUNT
39 select HAVE_DEBUG_KMEMLEAK
40 select HAVE_DMA_API_DEBUG
42 select HAVE_DMA_CONTIGUOUS if MMU
43 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
44 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
45 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
46 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
47 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
48 select HAVE_GENERIC_DMA_COHERENT
49 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
50 select HAVE_IDE if PCI || ISA || PCMCIA
51 select HAVE_IRQ_TIME_ACCOUNTING
52 select HAVE_KERNEL_GZIP
53 select HAVE_KERNEL_LZ4
54 select HAVE_KERNEL_LZMA
55 select HAVE_KERNEL_LZO
57 select HAVE_KPROBES if !XIP_KERNEL
58 select HAVE_KRETPROBES if (HAVE_KPROBES)
60 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
61 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
62 select HAVE_PERF_EVENTS
64 select HAVE_PERF_USER_STACK_DUMP
65 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
66 select HAVE_REGS_AND_STACK_ACCESS_API
67 select HAVE_SYSCALL_TRACEPOINTS
69 select HAVE_VIRT_CPU_ACCOUNTING_GEN
70 select IRQ_FORCED_THREADING
71 select MODULES_USE_ELF_REL
74 select OLD_SIGSUSPEND3
75 select PERF_USE_VMALLOC
77 select SYS_SUPPORTS_APM_EMULATION
78 # Above selects are sorted alphabetically; please add new ones
79 # according to that. Thanks.
81 The ARM series is a line of low-power-consumption RISC chip designs
82 licensed by ARM Ltd and targeted at embedded applications and
83 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
84 manufactured, but legacy ARM-based PC hardware remains popular in
85 Europe. There is an ARM Linux project with a web page at
86 <http://www.arm.linux.org.uk/>.
88 config ARM_HAS_SG_CHAIN
89 select ARCH_HAS_SG_CHAIN
92 config NEED_SG_DMA_LENGTH
95 config ARM_DMA_USE_IOMMU
97 select ARM_HAS_SG_CHAIN
98 select NEED_SG_DMA_LENGTH
102 config ARM_DMA_IOMMU_ALIGNMENT
103 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
107 DMA mapping framework by default aligns all buffers to the smallest
108 PAGE_SIZE order which is greater than or equal to the requested buffer
109 size. This works well for buffers up to a few hundreds kilobytes, but
110 for larger buffers it just a waste of address space. Drivers which has
111 relatively small addressing window (like 64Mib) might run out of
112 virtual space with just a few allocations.
114 With this parameter you can specify the maximum PAGE_SIZE order for
115 DMA IOMMU buffers. Larger buffers will be aligned only to this
116 specified order. The order is expressed as a power of two multiplied
121 config MIGHT_HAVE_PCI
124 config SYS_SUPPORTS_APM_EMULATION
129 select GENERIC_ALLOCATOR
140 The Extended Industry Standard Architecture (EISA) bus was
141 developed as an open alternative to the IBM MicroChannel bus.
143 The EISA bus provided some of the features of the IBM MicroChannel
144 bus while maintaining backward compatibility with cards made for
145 the older ISA bus. The EISA bus saw limited use between 1988 and
146 1995 when it was made obsolete by the PCI bus.
148 Say Y here if you are building a kernel for an EISA-based machine.
155 config STACKTRACE_SUPPORT
159 config HAVE_LATENCYTOP_SUPPORT
164 config LOCKDEP_SUPPORT
168 config TRACE_IRQFLAGS_SUPPORT
172 config RWSEM_XCHGADD_ALGORITHM
176 config ARCH_HAS_ILOG2_U32
179 config ARCH_HAS_ILOG2_U64
182 config ARCH_HAS_BANDGAP
185 config GENERIC_HWEIGHT
189 config GENERIC_CALIBRATE_DELAY
193 config ARCH_MAY_HAVE_PC_FDC
199 config NEED_DMA_MAP_STATE
202 config ARCH_SUPPORTS_UPROBES
205 config ARCH_HAS_DMA_SET_COHERENT_MASK
208 config GENERIC_ISA_DMA
214 config NEED_RET_TO_USER
222 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
223 default DRAM_BASE if REMAP_VECTORS_TO_RAM
226 The base address of exception vectors. This must be two pages
229 config ARM_PATCH_PHYS_VIRT
230 bool "Patch physical to virtual translations at runtime" if EMBEDDED
232 depends on !XIP_KERNEL && MMU
233 depends on !ARCH_REALVIEW || !SPARSEMEM
235 Patch phys-to-virt and virt-to-phys translation functions at
236 boot and module load time according to the position of the
237 kernel in system memory.
239 This can only be used with non-XIP MMU kernels where the base
240 of physical memory is at a 16MB boundary.
242 Only disable this option if you know that you do not require
243 this feature (eg, building a kernel for a single machine) and
244 you need to shrink the kernel to the minimal size.
246 config NEED_MACH_IO_H
249 Select this when mach/io.h is required to provide special
250 definitions for this platform. The need for mach/io.h should
251 be avoided when possible.
253 config NEED_MACH_MEMORY_H
256 Select this when mach/memory.h is required to provide special
257 definitions for this platform. The need for mach/memory.h should
258 be avoided when possible.
261 hex "Physical address of main memory" if MMU
262 depends on !ARM_PATCH_PHYS_VIRT
263 default DRAM_BASE if !MMU
264 default 0x00000000 if ARCH_EBSA110 || \
265 EP93XX_SDCE3_SYNC_PHYS_OFFSET || \
270 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
271 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
272 default 0x20000000 if ARCH_S5PV210
273 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
274 default 0xc0000000 if EP93XX_SDCE0_PHYS_OFFSET || ARCH_SA1100
275 default 0xd0000000 if EP93XX_SDCE1_PHYS_OFFSET
276 default 0xe0000000 if EP93XX_SDCE2_PHYS_OFFSET
277 default 0xf0000000 if EP93XX_SDCE3_ASYNC_PHYS_OFFSET
279 Please provide the physical address corresponding to the
280 location of main memory in your system.
286 source "init/Kconfig"
288 source "kernel/Kconfig.freezer"
293 bool "MMU-based Paged Memory Management Support"
296 Select if you want MMU-based virtualised addressing space
297 support by paged memory management. If unsure, say 'Y'.
300 # The "ARM system type" choice list is ordered alphabetically by option
301 # text. Please add new entries in the option alphabetic order.
304 prompt "ARM system type"
305 default ARCH_VERSATILE if !MMU
306 default ARCH_MULTIPLATFORM if MMU
308 config ARCH_MULTIPLATFORM
309 bool "Allow multiple platforms to be selected"
311 select ARCH_WANT_OPTIONAL_GPIOLIB
312 select ARM_HAS_SG_CHAIN
313 select ARM_PATCH_PHYS_VIRT
317 select GENERIC_CLOCKEVENTS
318 select MIGHT_HAVE_PCI
319 select MULTI_IRQ_HANDLER
323 config ARCH_INTEGRATOR
324 bool "ARM Ltd. Integrator family"
326 select ARM_PATCH_PHYS_VIRT if MMU
329 select COMMON_CLK_VERSATILE
330 select GENERIC_CLOCKEVENTS
333 select MULTI_IRQ_HANDLER
334 select PLAT_VERSATILE
337 select VERSATILE_FPGA_IRQ
339 Support for ARM's Integrator platform.
342 bool "ARM Ltd. RealView family"
343 select ARCH_WANT_OPTIONAL_GPIOLIB
345 select ARM_TIMER_SP804
347 select COMMON_CLK_VERSATILE
348 select GENERIC_CLOCKEVENTS
349 select GPIO_PL061 if GPIOLIB
351 select NEED_MACH_MEMORY_H
352 select PLAT_VERSATILE
354 This enables support for ARM Ltd RealView boards.
356 config ARCH_VERSATILE
357 bool "ARM Ltd. Versatile family"
358 select ARCH_WANT_OPTIONAL_GPIOLIB
360 select ARM_TIMER_SP804
363 select GENERIC_CLOCKEVENTS
364 select HAVE_MACH_CLKDEV
366 select PLAT_VERSATILE
367 select PLAT_VERSATILE_CLOCK
368 select VERSATILE_FPGA_IRQ
370 This enables support for ARM Ltd Versatile board.
374 select ARCH_REQUIRE_GPIOLIB
377 select NEED_MACH_IO_H if PCCARD
382 This enables support for systems based on Atmel
383 AT91RM9200, AT91SAM9 and SAMA5 processors.
386 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
387 select ARCH_REQUIRE_GPIOLIB
392 select GENERIC_CLOCKEVENTS
396 Support for Cirrus Logic 711x/721x/731x based boards.
399 bool "Cortina Systems Gemini"
400 select ARCH_REQUIRE_GPIOLIB
403 select GENERIC_CLOCKEVENTS
405 Support for the Cortina Systems Gemini family SoCs
409 select ARCH_USES_GETTIMEOFFSET
412 select NEED_MACH_IO_H
413 select NEED_MACH_MEMORY_H
416 This is an evaluation board for the StrongARM processor available
417 from Digital. It has limited hardware on-board, including an
418 Ethernet interface, two PCMCIA sockets, two serial ports and a
422 bool "Energy Micro efm32"
424 select ARCH_REQUIRE_GPIOLIB
430 select GENERIC_CLOCKEVENTS
436 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
441 select ARCH_HAS_HOLES_MEMORYMODEL
442 select ARCH_REQUIRE_GPIOLIB
443 select ARCH_USES_GETTIMEOFFSET
449 This enables support for the Cirrus EP93xx series of CPUs.
451 config ARCH_FOOTBRIDGE
455 select GENERIC_CLOCKEVENTS
457 select NEED_MACH_IO_H if !MMU
458 select NEED_MACH_MEMORY_H
460 Support for systems based on the DC21285 companion chip
461 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
464 bool "Hilscher NetX based"
468 select GENERIC_CLOCKEVENTS
470 This enables support for systems based on the Hilscher NetX Soc
476 select NEED_MACH_MEMORY_H
477 select NEED_RET_TO_USER
483 Support for Intel's IOP13XX (XScale) family of processors.
488 select ARCH_REQUIRE_GPIOLIB
491 select NEED_RET_TO_USER
495 Support for Intel's 80219 and IOP32X (XScale) family of
501 select ARCH_REQUIRE_GPIOLIB
504 select NEED_RET_TO_USER
508 Support for Intel's IOP33X (XScale) family of processors.
513 select ARCH_HAS_DMA_SET_COHERENT_MASK
514 select ARCH_REQUIRE_GPIOLIB
515 select ARCH_SUPPORTS_BIG_ENDIAN
518 select DMABOUNCE if PCI
519 select GENERIC_CLOCKEVENTS
520 select MIGHT_HAVE_PCI
521 select NEED_MACH_IO_H
522 select USB_EHCI_BIG_ENDIAN_DESC
523 select USB_EHCI_BIG_ENDIAN_MMIO
525 Support for Intel's IXP4XX (XScale) family of processors.
529 select ARCH_REQUIRE_GPIOLIB
531 select GENERIC_CLOCKEVENTS
532 select MIGHT_HAVE_PCI
536 select PLAT_ORION_LEGACY
538 Support for the Marvell Dove SoC 88AP510
541 bool "Marvell MV78xx0"
542 select ARCH_REQUIRE_GPIOLIB
544 select GENERIC_CLOCKEVENTS
547 select PLAT_ORION_LEGACY
549 Support for the following Marvell MV78xx0 series SoCs:
555 select ARCH_REQUIRE_GPIOLIB
557 select GENERIC_CLOCKEVENTS
560 select PLAT_ORION_LEGACY
562 Support for the following Marvell Orion 5x series SoCs:
563 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
564 Orion-2 (5281), Orion-1-90 (6183).
567 bool "Marvell PXA168/910/MMP2"
569 select ARCH_REQUIRE_GPIOLIB
571 select GENERIC_ALLOCATOR
572 select GENERIC_CLOCKEVENTS
575 select MULTI_IRQ_HANDLER
580 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
583 bool "Micrel/Kendin KS8695"
584 select ARCH_REQUIRE_GPIOLIB
587 select GENERIC_CLOCKEVENTS
588 select NEED_MACH_MEMORY_H
590 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
591 System-on-Chip devices.
594 bool "Nuvoton W90X900 CPU"
595 select ARCH_REQUIRE_GPIOLIB
599 select GENERIC_CLOCKEVENTS
601 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
602 At present, the w90x900 has been renamed nuc900, regarding
603 the ARM series product line, you can login the following
604 link address to know more.
606 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
607 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
611 select ARCH_REQUIRE_GPIOLIB
616 select GENERIC_CLOCKEVENTS
620 Support for the NXP LPC32XX family of processors
623 bool "PXA2xx/PXA3xx-based"
626 select ARCH_REQUIRE_GPIOLIB
627 select ARM_CPU_SUSPEND if PM
632 select GENERIC_CLOCKEVENTS
635 select MULTI_IRQ_HANDLER
639 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
642 bool "Qualcomm MSM (non-multiplatform)"
643 select ARCH_REQUIRE_GPIOLIB
645 select GENERIC_CLOCKEVENTS
647 Support for Qualcomm MSM/QSD based systems. This runs on the
648 apps processor of the MSM/QSD and depends on a shared memory
649 interface to the modem processor which runs the baseband
650 stack and controls some vital subsystems
651 (clock and power control, etc).
653 config ARCH_SHMOBILE_LEGACY
654 bool "Renesas ARM SoCs (non-multiplatform)"
656 select ARM_PATCH_PHYS_VIRT if MMU
659 select GENERIC_CLOCKEVENTS
660 select HAVE_ARM_SCU if SMP
661 select HAVE_ARM_TWD if SMP
662 select HAVE_MACH_CLKDEV
664 select MIGHT_HAVE_CACHE_L2X0
665 select MULTI_IRQ_HANDLER
668 select PM_GENERIC_DOMAINS if PM
672 Support for Renesas ARM SoC platforms using a non-multiplatform
673 kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
679 select ARCH_MAY_HAVE_PC_FDC
680 select ARCH_SPARSEMEM_ENABLE
681 select ARCH_USES_GETTIMEOFFSET
685 select HAVE_PATA_PLATFORM
687 select NEED_MACH_IO_H
688 select NEED_MACH_MEMORY_H
692 On the Acorn Risc-PC, Linux can support the internal IDE disk and
693 CD-ROM interface, serial and parallel port, and the floppy drive.
698 select ARCH_REQUIRE_GPIOLIB
699 select ARCH_SPARSEMEM_ENABLE
704 select GENERIC_CLOCKEVENTS
707 select NEED_MACH_MEMORY_H
710 Support for StrongARM 11x0 based boards.
713 bool "Samsung S3C24XX SoCs"
714 select ARCH_REQUIRE_GPIOLIB
717 select CLKSRC_SAMSUNG_PWM
718 select GENERIC_CLOCKEVENTS
720 select HAVE_S3C2410_I2C if I2C
721 select HAVE_S3C2410_WATCHDOG if WATCHDOG
722 select HAVE_S3C_RTC if RTC_CLASS
723 select MULTI_IRQ_HANDLER
724 select NEED_MACH_IO_H
727 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
728 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
729 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
730 Samsung SMDK2410 development board (and derivatives).
733 bool "Samsung S3C64XX"
734 select ARCH_REQUIRE_GPIOLIB
739 select CLKSRC_SAMSUNG_PWM
740 select COMMON_CLK_SAMSUNG
742 select GENERIC_CLOCKEVENTS
744 select HAVE_S3C2410_I2C if I2C
745 select HAVE_S3C2410_WATCHDOG if WATCHDOG
749 select PM_GENERIC_DOMAINS if PM
751 select S3C_GPIO_TRACK
753 select SAMSUNG_WAKEMASK
754 select SAMSUNG_WDT_RESET
756 Samsung S3C64XX series based systems
760 select ARCH_HAS_HOLES_MEMORYMODEL
761 select ARCH_REQUIRE_GPIOLIB
763 select GENERIC_ALLOCATOR
764 select GENERIC_CLOCKEVENTS
765 select GENERIC_IRQ_CHIP
771 Support for TI's DaVinci platform.
776 select ARCH_HAS_HOLES_MEMORYMODEL
778 select ARCH_REQUIRE_GPIOLIB
781 select GENERIC_CLOCKEVENTS
782 select GENERIC_IRQ_CHIP
785 select NEED_MACH_IO_H if PCCARD
786 select NEED_MACH_MEMORY_H
788 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
792 menu "Multiple platform selection"
793 depends on ARCH_MULTIPLATFORM
795 comment "CPU Core family selection"
798 bool "ARMv4 based platforms (FA526)"
799 depends on !ARCH_MULTI_V6_V7
800 select ARCH_MULTI_V4_V5
803 config ARCH_MULTI_V4T
804 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
805 depends on !ARCH_MULTI_V6_V7
806 select ARCH_MULTI_V4_V5
807 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
808 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
809 CPU_ARM925T || CPU_ARM940T)
812 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
813 depends on !ARCH_MULTI_V6_V7
814 select ARCH_MULTI_V4_V5
815 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
816 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
817 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
819 config ARCH_MULTI_V4_V5
823 bool "ARMv6 based platforms (ARM11)"
824 select ARCH_MULTI_V6_V7
828 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
830 select ARCH_MULTI_V6_V7
834 config ARCH_MULTI_V6_V7
836 select MIGHT_HAVE_CACHE_L2X0
838 config ARCH_MULTI_CPU_AUTO
839 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
845 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
849 select HAVE_ARM_ARCH_TIMER
852 # This is sorted alphabetically by mach-* pathname. However, plat-*
853 # Kconfigs may be included either alphabetically (according to the
854 # plat- suffix) or along side the corresponding mach-* source.
856 source "arch/arm/mach-mvebu/Kconfig"
858 source "arch/arm/mach-at91/Kconfig"
860 source "arch/arm/mach-axxia/Kconfig"
862 source "arch/arm/mach-bcm/Kconfig"
864 source "arch/arm/mach-berlin/Kconfig"
866 source "arch/arm/mach-clps711x/Kconfig"
868 source "arch/arm/mach-cns3xxx/Kconfig"
870 source "arch/arm/mach-davinci/Kconfig"
872 source "arch/arm/mach-dove/Kconfig"
874 source "arch/arm/mach-ep93xx/Kconfig"
876 source "arch/arm/mach-footbridge/Kconfig"
878 source "arch/arm/mach-gemini/Kconfig"
880 source "arch/arm/mach-highbank/Kconfig"
882 source "arch/arm/mach-hisi/Kconfig"
884 source "arch/arm/mach-integrator/Kconfig"
886 source "arch/arm/mach-iop32x/Kconfig"
888 source "arch/arm/mach-iop33x/Kconfig"
890 source "arch/arm/mach-iop13xx/Kconfig"
892 source "arch/arm/mach-ixp4xx/Kconfig"
894 source "arch/arm/mach-keystone/Kconfig"
896 source "arch/arm/mach-ks8695/Kconfig"
898 source "arch/arm/mach-meson/Kconfig"
900 source "arch/arm/mach-msm/Kconfig"
902 source "arch/arm/mach-moxart/Kconfig"
904 source "arch/arm/mach-mv78xx0/Kconfig"
906 source "arch/arm/mach-imx/Kconfig"
908 source "arch/arm/mach-mediatek/Kconfig"
910 source "arch/arm/mach-mxs/Kconfig"
912 source "arch/arm/mach-netx/Kconfig"
914 source "arch/arm/mach-nomadik/Kconfig"
916 source "arch/arm/mach-nspire/Kconfig"
918 source "arch/arm/plat-omap/Kconfig"
920 source "arch/arm/mach-omap1/Kconfig"
922 source "arch/arm/mach-omap2/Kconfig"
924 source "arch/arm/mach-orion5x/Kconfig"
926 source "arch/arm/mach-picoxcell/Kconfig"
928 source "arch/arm/mach-pxa/Kconfig"
929 source "arch/arm/plat-pxa/Kconfig"
931 source "arch/arm/mach-mmp/Kconfig"
933 source "arch/arm/mach-qcom/Kconfig"
935 source "arch/arm/mach-realview/Kconfig"
937 source "arch/arm/mach-rockchip/Kconfig"
939 source "arch/arm/mach-sa1100/Kconfig"
941 source "arch/arm/mach-socfpga/Kconfig"
943 source "arch/arm/mach-spear/Kconfig"
945 source "arch/arm/mach-sti/Kconfig"
947 source "arch/arm/mach-s3c24xx/Kconfig"
949 source "arch/arm/mach-s3c64xx/Kconfig"
951 source "arch/arm/mach-s5pv210/Kconfig"
953 source "arch/arm/mach-exynos/Kconfig"
954 source "arch/arm/plat-samsung/Kconfig"
956 source "arch/arm/mach-shmobile/Kconfig"
958 source "arch/arm/mach-sunxi/Kconfig"
960 source "arch/arm/mach-prima2/Kconfig"
962 source "arch/arm/mach-tegra/Kconfig"
964 source "arch/arm/mach-u300/Kconfig"
966 source "arch/arm/mach-ux500/Kconfig"
968 source "arch/arm/mach-versatile/Kconfig"
970 source "arch/arm/mach-vexpress/Kconfig"
971 source "arch/arm/plat-versatile/Kconfig"
973 source "arch/arm/mach-vt8500/Kconfig"
975 source "arch/arm/mach-w90x900/Kconfig"
977 source "arch/arm/mach-zynq/Kconfig"
979 # Definitions to make life easier
985 select GENERIC_CLOCKEVENTS
991 select GENERIC_IRQ_CHIP
994 config PLAT_ORION_LEGACY
1001 config PLAT_VERSATILE
1004 config ARM_TIMER_SP804
1007 select CLKSRC_OF if OF
1009 source "arch/arm/firmware/Kconfig"
1011 source arch/arm/mm/Kconfig
1014 bool "Enable iWMMXt support"
1015 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1016 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1018 Enable support for iWMMXt context switching at run time if
1019 running on a CPU that supports it.
1021 config MULTI_IRQ_HANDLER
1024 Allow each machine to specify it's own IRQ handler at run time.
1027 source "arch/arm/Kconfig-nommu"
1030 config PJ4B_ERRATA_4742
1031 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1032 depends on CPU_PJ4B && MACH_ARMADA_370
1035 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1036 Event (WFE) IDLE states, a specific timing sensitivity exists between
1037 the retiring WFI/WFE instructions and the newly issued subsequent
1038 instructions. This sensitivity can result in a CPU hang scenario.
1040 The software must insert either a Data Synchronization Barrier (DSB)
1041 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1044 config ARM_ERRATA_326103
1045 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1048 Executing a SWP instruction to read-only memory does not set bit 11
1049 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1050 treat the access as a read, preventing a COW from occurring and
1051 causing the faulting task to livelock.
1053 config ARM_ERRATA_411920
1054 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1055 depends on CPU_V6 || CPU_V6K
1057 Invalidation of the Instruction Cache operation can
1058 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1059 It does not affect the MPCore. This option enables the ARM Ltd.
1060 recommended workaround.
1062 config ARM_ERRATA_430973
1063 bool "ARM errata: Stale prediction on replaced interworking branch"
1066 This option enables the workaround for the 430973 Cortex-A8
1067 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1068 interworking branch is replaced with another code sequence at the
1069 same virtual address, whether due to self-modifying code or virtual
1070 to physical address re-mapping, Cortex-A8 does not recover from the
1071 stale interworking branch prediction. This results in Cortex-A8
1072 executing the new code sequence in the incorrect ARM or Thumb state.
1073 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1074 and also flushes the branch target cache at every context switch.
1075 Note that setting specific bits in the ACTLR register may not be
1076 available in non-secure mode.
1078 config ARM_ERRATA_458693
1079 bool "ARM errata: Processor deadlock when a false hazard is created"
1081 depends on !ARCH_MULTIPLATFORM
1083 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1084 erratum. For very specific sequences of memory operations, it is
1085 possible for a hazard condition intended for a cache line to instead
1086 be incorrectly associated with a different cache line. This false
1087 hazard might then cause a processor deadlock. The workaround enables
1088 the L1 caching of the NEON accesses and disables the PLD instruction
1089 in the ACTLR register. Note that setting specific bits in the ACTLR
1090 register may not be available in non-secure mode.
1092 config ARM_ERRATA_460075
1093 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1095 depends on !ARCH_MULTIPLATFORM
1097 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1098 erratum. Any asynchronous access to the L2 cache may encounter a
1099 situation in which recent store transactions to the L2 cache are lost
1100 and overwritten with stale memory contents from external memory. The
1101 workaround disables the write-allocate mode for the L2 cache via the
1102 ACTLR register. Note that setting specific bits in the ACTLR register
1103 may not be available in non-secure mode.
1105 config ARM_ERRATA_742230
1106 bool "ARM errata: DMB operation may be faulty"
1107 depends on CPU_V7 && SMP
1108 depends on !ARCH_MULTIPLATFORM
1110 This option enables the workaround for the 742230 Cortex-A9
1111 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1112 between two write operations may not ensure the correct visibility
1113 ordering of the two writes. This workaround sets a specific bit in
1114 the diagnostic register of the Cortex-A9 which causes the DMB
1115 instruction to behave as a DSB, ensuring the correct behaviour of
1118 config ARM_ERRATA_742231
1119 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1120 depends on CPU_V7 && SMP
1121 depends on !ARCH_MULTIPLATFORM
1123 This option enables the workaround for the 742231 Cortex-A9
1124 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1125 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1126 accessing some data located in the same cache line, may get corrupted
1127 data due to bad handling of the address hazard when the line gets
1128 replaced from one of the CPUs at the same time as another CPU is
1129 accessing it. This workaround sets specific bits in the diagnostic
1130 register of the Cortex-A9 which reduces the linefill issuing
1131 capabilities of the processor.
1133 config ARM_ERRATA_643719
1134 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1135 depends on CPU_V7 && SMP
1137 This option enables the workaround for the 643719 Cortex-A9 (prior to
1138 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1139 register returns zero when it should return one. The workaround
1140 corrects this value, ensuring cache maintenance operations which use
1141 it behave as intended and avoiding data corruption.
1143 config ARM_ERRATA_720789
1144 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1147 This option enables the workaround for the 720789 Cortex-A9 (prior to
1148 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1149 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1150 As a consequence of this erratum, some TLB entries which should be
1151 invalidated are not, resulting in an incoherency in the system page
1152 tables. The workaround changes the TLB flushing routines to invalidate
1153 entries regardless of the ASID.
1155 config ARM_ERRATA_743622
1156 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1158 depends on !ARCH_MULTIPLATFORM
1160 This option enables the workaround for the 743622 Cortex-A9
1161 (r2p*) erratum. Under very rare conditions, a faulty
1162 optimisation in the Cortex-A9 Store Buffer may lead to data
1163 corruption. This workaround sets a specific bit in the diagnostic
1164 register of the Cortex-A9 which disables the Store Buffer
1165 optimisation, preventing the defect from occurring. This has no
1166 visible impact on the overall performance or power consumption of the
1169 config ARM_ERRATA_751472
1170 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1172 depends on !ARCH_MULTIPLATFORM
1174 This option enables the workaround for the 751472 Cortex-A9 (prior
1175 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1176 completion of a following broadcasted operation if the second
1177 operation is received by a CPU before the ICIALLUIS has completed,
1178 potentially leading to corrupted entries in the cache or TLB.
1180 config ARM_ERRATA_754322
1181 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1184 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1185 r3p*) erratum. A speculative memory access may cause a page table walk
1186 which starts prior to an ASID switch but completes afterwards. This
1187 can populate the micro-TLB with a stale entry which may be hit with
1188 the new ASID. This workaround places two dsb instructions in the mm
1189 switching code so that no page table walks can cross the ASID switch.
1191 config ARM_ERRATA_754327
1192 bool "ARM errata: no automatic Store Buffer drain"
1193 depends on CPU_V7 && SMP
1195 This option enables the workaround for the 754327 Cortex-A9 (prior to
1196 r2p0) erratum. The Store Buffer does not have any automatic draining
1197 mechanism and therefore a livelock may occur if an external agent
1198 continuously polls a memory location waiting to observe an update.
1199 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1200 written polling loops from denying visibility of updates to memory.
1202 config ARM_ERRATA_364296
1203 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1206 This options enables the workaround for the 364296 ARM1136
1207 r0p2 erratum (possible cache data corruption with
1208 hit-under-miss enabled). It sets the undocumented bit 31 in
1209 the auxiliary control register and the FI bit in the control
1210 register, thus disabling hit-under-miss without putting the
1211 processor into full low interrupt latency mode. ARM11MPCore
1214 config ARM_ERRATA_764369
1215 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1216 depends on CPU_V7 && SMP
1218 This option enables the workaround for erratum 764369
1219 affecting Cortex-A9 MPCore with two or more processors (all
1220 current revisions). Under certain timing circumstances, a data
1221 cache line maintenance operation by MVA targeting an Inner
1222 Shareable memory region may fail to proceed up to either the
1223 Point of Coherency or to the Point of Unification of the
1224 system. This workaround adds a DSB instruction before the
1225 relevant cache maintenance functions and sets a specific bit
1226 in the diagnostic control register of the SCU.
1228 config ARM_ERRATA_775420
1229 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1232 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1233 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1234 operation aborts with MMU exception, it might cause the processor
1235 to deadlock. This workaround puts DSB before executing ISB if
1236 an abort may occur on cache maintenance.
1238 config ARM_ERRATA_798181
1239 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1240 depends on CPU_V7 && SMP
1242 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1243 adequately shooting down all use of the old entries. This
1244 option enables the Linux kernel workaround for this erratum
1245 which sends an IPI to the CPUs that are running the same ASID
1246 as the one being invalidated.
1248 config ARM_ERRATA_773022
1249 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1252 This option enables the workaround for the 773022 Cortex-A15
1253 (up to r0p4) erratum. In certain rare sequences of code, the
1254 loop buffer may deliver incorrect instructions. This
1255 workaround disables the loop buffer to avoid the erratum.
1259 source "arch/arm/common/Kconfig"
1266 Find out whether you have ISA slots on your motherboard. ISA is the
1267 name of a bus system, i.e. the way the CPU talks to the other stuff
1268 inside your box. Other bus systems are PCI, EISA, MicroChannel
1269 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1270 newer boards don't support it. If you have ISA, say Y, otherwise N.
1272 # Select ISA DMA controller support
1277 # Select ISA DMA interface
1282 bool "PCI support" if MIGHT_HAVE_PCI
1284 Find out whether you have a PCI motherboard. PCI is the name of a
1285 bus system, i.e. the way the CPU talks to the other stuff inside
1286 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1287 VESA. If you have PCI, say Y, otherwise N.
1293 config PCI_NANOENGINE
1294 bool "BSE nanoEngine PCI support"
1295 depends on SA1100_NANOENGINE
1297 Enable PCI on the BSE nanoEngine board.
1302 config PCI_HOST_ITE8152
1304 depends on PCI && MACH_ARMCORE
1308 source "drivers/pci/Kconfig"
1309 source "drivers/pci/pcie/Kconfig"
1311 source "drivers/pcmcia/Kconfig"
1315 menu "Kernel Features"
1320 This option should be selected by machines which have an SMP-
1323 The only effect of this option is to make the SMP-related
1324 options available to the user for configuration.
1327 bool "Symmetric Multi-Processing"
1328 depends on CPU_V6K || CPU_V7
1329 depends on GENERIC_CLOCKEVENTS
1331 depends on MMU || ARM_MPU
1333 This enables support for systems with more than one CPU. If you have
1334 a system with only one CPU, say N. If you have a system with more
1335 than one CPU, say Y.
1337 If you say N here, the kernel will run on uni- and multiprocessor
1338 machines, but will use only one CPU of a multiprocessor machine. If
1339 you say Y here, the kernel will run on many, but not all,
1340 uniprocessor machines. On a uniprocessor machine, the kernel
1341 will run faster if you say N here.
1343 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1344 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1345 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1347 If you don't know what to do here, say N.
1350 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1351 depends on SMP && !XIP_KERNEL && MMU
1354 SMP kernels contain instructions which fail on non-SMP processors.
1355 Enabling this option allows the kernel to modify itself to make
1356 these instructions safe. Disabling it allows about 1K of space
1359 If you don't know what to do here, say Y.
1361 config ARM_CPU_TOPOLOGY
1362 bool "Support cpu topology definition"
1363 depends on SMP && CPU_V7
1366 Support ARM cpu topology definition. The MPIDR register defines
1367 affinity between processors which is then used to describe the cpu
1368 topology of an ARM System.
1371 bool "Multi-core scheduler support"
1372 depends on ARM_CPU_TOPOLOGY
1374 Multi-core scheduler support improves the CPU scheduler's decision
1375 making when dealing with multi-core CPU chips at a cost of slightly
1376 increased overhead in some places. If unsure say N here.
1379 bool "SMT scheduler support"
1380 depends on ARM_CPU_TOPOLOGY
1382 Improves the CPU scheduler's decision making when dealing with
1383 MultiThreading at a cost of slightly increased overhead in some
1384 places. If unsure say N here.
1389 This option enables support for the ARM system coherency unit
1391 config HAVE_ARM_ARCH_TIMER
1392 bool "Architected timer support"
1394 select ARM_ARCH_TIMER
1395 select GENERIC_CLOCKEVENTS
1397 This option enables support for the ARM architected timer
1402 select CLKSRC_OF if OF
1404 This options enables support for the ARM timer and watchdog unit
1407 bool "Multi-Cluster Power Management"
1408 depends on CPU_V7 && SMP
1410 This option provides the common power management infrastructure
1411 for (multi-)cluster based systems, such as big.LITTLE based
1414 config MCPM_QUAD_CLUSTER
1418 To avoid wasting resources unnecessarily, MCPM only supports up
1419 to 2 clusters by default.
1420 Platforms with 3 or 4 clusters that use MCPM must select this
1421 option to allow the additional clusters to be managed.
1424 bool "big.LITTLE support (Experimental)"
1425 depends on CPU_V7 && SMP
1428 This option enables support selections for the big.LITTLE
1429 system architecture.
1432 bool "big.LITTLE switcher support"
1433 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1434 select ARM_CPU_SUSPEND
1437 The big.LITTLE "switcher" provides the core functionality to
1438 transparently handle transition between a cluster of A15's
1439 and a cluster of A7's in a big.LITTLE system.
1441 config BL_SWITCHER_DUMMY_IF
1442 tristate "Simple big.LITTLE switcher user interface"
1443 depends on BL_SWITCHER && DEBUG_KERNEL
1445 This is a simple and dummy char dev interface to control
1446 the big.LITTLE switcher core code. It is meant for
1447 debugging purposes only.
1450 prompt "Memory split"
1454 Select the desired split between kernel and user memory.
1456 If you are not absolutely sure what you are doing, leave this
1460 bool "3G/1G user/kernel split"
1462 bool "2G/2G user/kernel split"
1464 bool "1G/3G user/kernel split"
1469 default PHYS_OFFSET if !MMU
1470 default 0x40000000 if VMSPLIT_1G
1471 default 0x80000000 if VMSPLIT_2G
1475 int "Maximum number of CPUs (2-32)"
1481 bool "Support for hot-pluggable CPUs"
1484 Say Y here to experiment with turning CPUs off and on. CPUs
1485 can be controlled through /sys/devices/system/cpu.
1488 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1491 Say Y here if you want Linux to communicate with system firmware
1492 implementing the PSCI specification for CPU-centric power
1493 management operations described in ARM document number ARM DEN
1494 0022A ("Power State Coordination Interface System Software on
1497 # The GPIO number here must be sorted by descending number. In case of
1498 # a multiplatform kernel, we just want the highest value required by the
1499 # selected platforms.
1502 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1503 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1504 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1505 default 416 if ARCH_SUNXI
1506 default 392 if ARCH_U8500
1507 default 352 if ARCH_VT8500
1508 default 288 if ARCH_ROCKCHIP
1509 default 264 if MACH_H4700
1512 Maximum number of GPIOs in the system.
1514 If unsure, leave the default value.
1516 source kernel/Kconfig.preempt
1520 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1521 ARCH_S5PV210 || ARCH_EXYNOS4
1522 default AT91_TIMER_HZ if ARCH_AT91
1523 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1527 depends on HZ_FIXED = 0
1528 prompt "Timer frequency"
1552 default HZ_FIXED if HZ_FIXED != 0
1553 default 100 if HZ_100
1554 default 200 if HZ_200
1555 default 250 if HZ_250
1556 default 300 if HZ_300
1557 default 500 if HZ_500
1561 def_bool HIGH_RES_TIMERS
1563 config THUMB2_KERNEL
1564 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1565 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1566 default y if CPU_THUMBONLY
1568 select ARM_ASM_UNIFIED
1571 By enabling this option, the kernel will be compiled in
1572 Thumb-2 mode. A compiler/assembler that understand the unified
1573 ARM-Thumb syntax is needed.
1577 config THUMB2_AVOID_R_ARM_THM_JUMP11
1578 bool "Work around buggy Thumb-2 short branch relocations in gas"
1579 depends on THUMB2_KERNEL && MODULES
1582 Various binutils versions can resolve Thumb-2 branches to
1583 locally-defined, preemptible global symbols as short-range "b.n"
1584 branch instructions.
1586 This is a problem, because there's no guarantee the final
1587 destination of the symbol, or any candidate locations for a
1588 trampoline, are within range of the branch. For this reason, the
1589 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1590 relocation in modules at all, and it makes little sense to add
1593 The symptom is that the kernel fails with an "unsupported
1594 relocation" error when loading some modules.
1596 Until fixed tools are available, passing
1597 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1598 code which hits this problem, at the cost of a bit of extra runtime
1599 stack usage in some cases.
1601 The problem is described in more detail at:
1602 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1604 Only Thumb-2 kernels are affected.
1606 Unless you are sure your tools don't have this problem, say Y.
1608 config ARM_ASM_UNIFIED
1612 bool "Use the ARM EABI to compile the kernel"
1614 This option allows for the kernel to be compiled using the latest
1615 ARM ABI (aka EABI). This is only useful if you are using a user
1616 space environment that is also compiled with EABI.
1618 Since there are major incompatibilities between the legacy ABI and
1619 EABI, especially with regard to structure member alignment, this
1620 option also changes the kernel syscall calling convention to
1621 disambiguate both ABIs and allow for backward compatibility support
1622 (selected with CONFIG_OABI_COMPAT).
1624 To use this you need GCC version 4.0.0 or later.
1627 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1628 depends on AEABI && !THUMB2_KERNEL
1630 This option preserves the old syscall interface along with the
1631 new (ARM EABI) one. It also provides a compatibility layer to
1632 intercept syscalls that have structure arguments which layout
1633 in memory differs between the legacy ABI and the new ARM EABI
1634 (only for non "thumb" binaries). This option adds a tiny
1635 overhead to all syscalls and produces a slightly larger kernel.
1637 The seccomp filter system will not be available when this is
1638 selected, since there is no way yet to sensibly distinguish
1639 between calling conventions during filtering.
1641 If you know you'll be using only pure EABI user space then you
1642 can say N here. If this option is not selected and you attempt
1643 to execute a legacy ABI binary then the result will be
1644 UNPREDICTABLE (in fact it can be predicted that it won't work
1645 at all). If in doubt say N.
1647 config ARCH_HAS_HOLES_MEMORYMODEL
1650 config ARCH_SPARSEMEM_ENABLE
1653 config ARCH_SPARSEMEM_DEFAULT
1654 def_bool ARCH_SPARSEMEM_ENABLE
1656 config ARCH_SELECT_MEMORY_MODEL
1657 def_bool ARCH_SPARSEMEM_ENABLE
1659 config HAVE_ARCH_PFN_VALID
1660 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1662 config HAVE_GENERIC_RCU_GUP
1667 bool "High Memory Support"
1670 The address space of ARM processors is only 4 Gigabytes large
1671 and it has to accommodate user address space, kernel address
1672 space as well as some memory mapped IO. That means that, if you
1673 have a large amount of physical memory and/or IO, not all of the
1674 memory can be "permanently mapped" by the kernel. The physical
1675 memory that is not permanently mapped is called "high memory".
1677 Depending on the selected kernel/user memory split, minimum
1678 vmalloc space and actual amount of RAM, you may not need this
1679 option which should result in a slightly faster kernel.
1684 bool "Allocate 2nd-level pagetables from highmem"
1687 config HW_PERF_EVENTS
1688 bool "Enable hardware performance counter support for perf events"
1689 depends on PERF_EVENTS
1692 Enable hardware performance counter support for perf events. If
1693 disabled, perf events will use software events only.
1695 config SYS_SUPPORTS_HUGETLBFS
1699 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1703 config ARCH_WANT_GENERAL_HUGETLB
1708 config FORCE_MAX_ZONEORDER
1709 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1710 range 11 64 if ARCH_SHMOBILE_LEGACY
1711 default "12" if SOC_AM33XX
1712 default "9" if SA1111 || ARCH_EFM32
1715 The kernel memory allocator divides physically contiguous memory
1716 blocks into "zones", where each zone is a power of two number of
1717 pages. This option selects the largest power of two that the kernel
1718 keeps in the memory allocator. If you need to allocate very large
1719 blocks of physically contiguous memory, then you may need to
1720 increase this value.
1722 This config option is actually maximum order plus one. For example,
1723 a value of 11 means that the largest free memory block is 2^10 pages.
1725 config ALIGNMENT_TRAP
1727 depends on CPU_CP15_MMU
1728 default y if !ARCH_EBSA110
1729 select HAVE_PROC_CPU if PROC_FS
1731 ARM processors cannot fetch/store information which is not
1732 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1733 address divisible by 4. On 32-bit ARM processors, these non-aligned
1734 fetch/store instructions will be emulated in software if you say
1735 here, which has a severe performance impact. This is necessary for
1736 correct operation of some network protocols. With an IP-only
1737 configuration it is safe to say N, otherwise say Y.
1739 config UACCESS_WITH_MEMCPY
1740 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1742 default y if CPU_FEROCEON
1744 Implement faster copy_to_user and clear_user methods for CPU
1745 cores where a 8-word STM instruction give significantly higher
1746 memory write throughput than a sequence of individual 32bit stores.
1748 A possible side effect is a slight increase in scheduling latency
1749 between threads sharing the same address space if they invoke
1750 such copy operations with large buffers.
1752 However, if the CPU data cache is using a write-allocate mode,
1753 this option is unlikely to provide any performance gain.
1757 prompt "Enable seccomp to safely compute untrusted bytecode"
1759 This kernel feature is useful for number crunching applications
1760 that may need to compute untrusted bytecode during their
1761 execution. By using pipes or other transports made available to
1762 the process as file descriptors supporting the read/write
1763 syscalls, it's possible to isolate those applications in
1764 their own address space using seccomp. Once seccomp is
1765 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1766 and the task is only allowed to execute a few safe syscalls
1767 defined by each seccomp mode.
1780 bool "Xen guest support on ARM"
1781 depends on ARM && AEABI && OF
1782 depends on CPU_V7 && !CPU_V6
1783 depends on !GENERIC_ATOMIC64
1785 select ARCH_DMA_ADDR_T_64BIT
1789 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1796 bool "Flattened Device Tree support"
1799 select OF_EARLY_FLATTREE
1800 select OF_RESERVED_MEM
1802 Include support for flattened device tree machine descriptions.
1805 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1808 This is the traditional way of passing data to the kernel at boot
1809 time. If you are solely relying on the flattened device tree (or
1810 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1811 to remove ATAGS support from your kernel binary. If unsure,
1814 config DEPRECATED_PARAM_STRUCT
1815 bool "Provide old way to pass kernel parameters"
1818 This was deprecated in 2001 and announced to live on for 5 years.
1819 Some old boot loaders still use this way.
1821 # Compressed boot loader in ROM. Yes, we really want to ask about
1822 # TEXT and BSS so we preserve their values in the config files.
1823 config ZBOOT_ROM_TEXT
1824 hex "Compressed ROM boot loader base address"
1827 The physical address at which the ROM-able zImage is to be
1828 placed in the target. Platforms which normally make use of
1829 ROM-able zImage formats normally set this to a suitable
1830 value in their defconfig file.
1832 If ZBOOT_ROM is not enabled, this has no effect.
1834 config ZBOOT_ROM_BSS
1835 hex "Compressed ROM boot loader BSS address"
1838 The base address of an area of read/write memory in the target
1839 for the ROM-able zImage which must be available while the
1840 decompressor is running. It must be large enough to hold the
1841 entire decompressed kernel plus an additional 128 KiB.
1842 Platforms which normally make use of ROM-able zImage formats
1843 normally set this to a suitable value in their defconfig file.
1845 If ZBOOT_ROM is not enabled, this has no effect.
1848 bool "Compressed boot loader in ROM/flash"
1849 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1850 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1852 Say Y here if you intend to execute your compressed kernel image
1853 (zImage) directly from ROM or flash. If unsure, say N.
1856 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1857 depends on ZBOOT_ROM && ARCH_SH7372
1858 default ZBOOT_ROM_NONE
1860 Include experimental SD/MMC loading code in the ROM-able zImage.
1861 With this enabled it is possible to write the ROM-able zImage
1862 kernel image to an MMC or SD card and boot the kernel straight
1863 from the reset vector. At reset the processor Mask ROM will load
1864 the first part of the ROM-able zImage which in turn loads the
1865 rest the kernel image to RAM.
1867 config ZBOOT_ROM_NONE
1868 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1870 Do not load image from SD or MMC
1872 config ZBOOT_ROM_MMCIF
1873 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1875 Load image from MMCIF hardware block.
1877 config ZBOOT_ROM_SH_MOBILE_SDHI
1878 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1880 Load image from SDHI hardware block
1884 config ARM_APPENDED_DTB
1885 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1888 With this option, the boot code will look for a device tree binary
1889 (DTB) appended to zImage
1890 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1892 This is meant as a backward compatibility convenience for those
1893 systems with a bootloader that can't be upgraded to accommodate
1894 the documented boot protocol using a device tree.
1896 Beware that there is very little in terms of protection against
1897 this option being confused by leftover garbage in memory that might
1898 look like a DTB header after a reboot if no actual DTB is appended
1899 to zImage. Do not leave this option active in a production kernel
1900 if you don't intend to always append a DTB. Proper passing of the
1901 location into r2 of a bootloader provided DTB is always preferable
1904 config ARM_ATAG_DTB_COMPAT
1905 bool "Supplement the appended DTB with traditional ATAG information"
1906 depends on ARM_APPENDED_DTB
1908 Some old bootloaders can't be updated to a DTB capable one, yet
1909 they provide ATAGs with memory configuration, the ramdisk address,
1910 the kernel cmdline string, etc. Such information is dynamically
1911 provided by the bootloader and can't always be stored in a static
1912 DTB. To allow a device tree enabled kernel to be used with such
1913 bootloaders, this option allows zImage to extract the information
1914 from the ATAG list and store it at run time into the appended DTB.
1917 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1918 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1920 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1921 bool "Use bootloader kernel arguments if available"
1923 Uses the command-line options passed by the boot loader instead of
1924 the device tree bootargs property. If the boot loader doesn't provide
1925 any, the device tree bootargs property will be used.
1927 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1928 bool "Extend with bootloader kernel arguments"
1930 The command-line arguments provided by the boot loader will be
1931 appended to the the device tree bootargs property.
1936 string "Default kernel command string"
1939 On some architectures (EBSA110 and CATS), there is currently no way
1940 for the boot loader to pass arguments to the kernel. For these
1941 architectures, you should supply some command-line options at build
1942 time by entering them here. As a minimum, you should specify the
1943 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1946 prompt "Kernel command line type" if CMDLINE != ""
1947 default CMDLINE_FROM_BOOTLOADER
1950 config CMDLINE_FROM_BOOTLOADER
1951 bool "Use bootloader kernel arguments if available"
1953 Uses the command-line options passed by the boot loader. If
1954 the boot loader doesn't provide any, the default kernel command
1955 string provided in CMDLINE will be used.
1957 config CMDLINE_EXTEND
1958 bool "Extend bootloader kernel arguments"
1960 The command-line arguments provided by the boot loader will be
1961 appended to the default kernel command string.
1963 config CMDLINE_FORCE
1964 bool "Always use the default kernel command string"
1966 Always use the default kernel command string, even if the boot
1967 loader passes other arguments to the kernel.
1968 This is useful if you cannot or don't want to change the
1969 command-line options your boot loader passes to the kernel.
1973 bool "Kernel Execute-In-Place from ROM"
1974 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1976 Execute-In-Place allows the kernel to run from non-volatile storage
1977 directly addressable by the CPU, such as NOR flash. This saves RAM
1978 space since the text section of the kernel is not loaded from flash
1979 to RAM. Read-write sections, such as the data section and stack,
1980 are still copied to RAM. The XIP kernel is not compressed since
1981 it has to run directly from flash, so it will take more space to
1982 store it. The flash address used to link the kernel object files,
1983 and for storing it, is configuration dependent. Therefore, if you
1984 say Y here, you must know the proper physical address where to
1985 store the kernel image depending on your own flash memory usage.
1987 Also note that the make target becomes "make xipImage" rather than
1988 "make zImage" or "make Image". The final kernel binary to put in
1989 ROM memory will be arch/arm/boot/xipImage.
1993 config XIP_PHYS_ADDR
1994 hex "XIP Kernel Physical Location"
1995 depends on XIP_KERNEL
1996 default "0x00080000"
1998 This is the physical address in your flash memory the kernel will
1999 be linked for and stored to. This address is dependent on your
2003 bool "Kexec system call (EXPERIMENTAL)"
2004 depends on (!SMP || PM_SLEEP_SMP)
2006 kexec is a system call that implements the ability to shutdown your
2007 current kernel, and to start another kernel. It is like a reboot
2008 but it is independent of the system firmware. And like a reboot
2009 you can start any kernel with it, not just Linux.
2011 It is an ongoing process to be certain the hardware in a machine
2012 is properly shutdown, so do not be surprised if this code does not
2013 initially work for you.
2016 bool "Export atags in procfs"
2017 depends on ATAGS && KEXEC
2020 Should the atags used to boot the kernel be exported in an "atags"
2021 file in procfs. Useful with kexec.
2024 bool "Build kdump crash kernel (EXPERIMENTAL)"
2026 Generate crash dump after being started by kexec. This should
2027 be normally only set in special crash dump kernels which are
2028 loaded in the main kernel with kexec-tools into a specially
2029 reserved region and then later executed after a crash by
2030 kdump/kexec. The crash dump kernel must be compiled to a
2031 memory address not used by the main kernel
2033 For more details see Documentation/kdump/kdump.txt
2035 config AUTO_ZRELADDR
2036 bool "Auto calculation of the decompressed kernel image address"
2038 ZRELADDR is the physical address where the decompressed kernel
2039 image will be placed. If AUTO_ZRELADDR is selected, the address
2040 will be determined at run-time by masking the current IP with
2041 0xf8000000. This assumes the zImage being placed in the first 128MB
2042 from start of memory.
2046 menu "CPU Power Management"
2048 source "drivers/cpufreq/Kconfig"
2050 source "drivers/cpuidle/Kconfig"
2054 menu "Floating point emulation"
2056 comment "At least one emulation must be selected"
2059 bool "NWFPE math emulation"
2060 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2062 Say Y to include the NWFPE floating point emulator in the kernel.
2063 This is necessary to run most binaries. Linux does not currently
2064 support floating point hardware so you need to say Y here even if
2065 your machine has an FPA or floating point co-processor podule.
2067 You may say N here if you are going to load the Acorn FPEmulator
2068 early in the bootup.
2071 bool "Support extended precision"
2072 depends on FPE_NWFPE
2074 Say Y to include 80-bit support in the kernel floating-point
2075 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2076 Note that gcc does not generate 80-bit operations by default,
2077 so in most cases this option only enlarges the size of the
2078 floating point emulator without any good reason.
2080 You almost surely want to say N here.
2083 bool "FastFPE math emulation (EXPERIMENTAL)"
2084 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2086 Say Y here to include the FAST floating point emulator in the kernel.
2087 This is an experimental much faster emulator which now also has full
2088 precision for the mantissa. It does not support any exceptions.
2089 It is very simple, and approximately 3-6 times faster than NWFPE.
2091 It should be sufficient for most programs. It may be not suitable
2092 for scientific calculations, but you have to check this for yourself.
2093 If you do not feel you need a faster FP emulation you should better
2097 bool "VFP-format floating point maths"
2098 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2100 Say Y to include VFP support code in the kernel. This is needed
2101 if your hardware includes a VFP unit.
2103 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2104 release notes and additional status information.
2106 Say N if your target does not have VFP hardware.
2114 bool "Advanced SIMD (NEON) Extension support"
2115 depends on VFPv3 && CPU_V7
2117 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2120 config KERNEL_MODE_NEON
2121 bool "Support for NEON in kernel mode"
2122 depends on NEON && AEABI
2124 Say Y to include support for NEON in kernel mode.
2128 menu "Userspace binary formats"
2130 source "fs/Kconfig.binfmt"
2133 tristate "RISC OS personality"
2136 Say Y here to include the kernel code necessary if you want to run
2137 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2138 experimental; if this sounds frightening, say N and sleep in peace.
2139 You can also say M here to compile this support as a module (which
2140 will be called arthur).
2144 menu "Power management options"
2146 source "kernel/power/Kconfig"
2148 config ARCH_SUSPEND_POSSIBLE
2149 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2150 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2153 config ARM_CPU_SUSPEND
2156 config ARCH_HIBERNATION_POSSIBLE
2159 default y if ARCH_SUSPEND_POSSIBLE
2163 source "net/Kconfig"
2165 source "drivers/Kconfig"
2169 source "arch/arm/Kconfig.debug"
2171 source "security/Kconfig"
2173 source "crypto/Kconfig"
2175 source "lib/Kconfig"
2177 source "arch/arm/kvm/Kconfig"