5 select HAVE_DMA_API_DEBUG
6 select HAVE_IDE if PCI || ISA || PCMCIA
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if !XIP_KERNEL
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
32 select CPU_PM if (SUSPEND || CPU_IDLE)
34 The ARM series is a line of low-power-consumption RISC chip designs
35 licensed by ARM Ltd and targeted at embedded applications and
36 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
37 manufactured, but legacy ARM-based PC hardware remains popular in
38 Europe. There is an ARM Linux project with a web page at
39 <http://www.arm.linux.org.uk/>.
41 config ARM_HAS_SG_CHAIN
50 config SYS_SUPPORTS_APM_EMULATION
53 config HAVE_SCHED_CLOCK
59 config ARCH_USES_GETTIMEOFFSET
63 config GENERIC_CLOCKEVENTS
66 config GENERIC_CLOCKEVENTS_BROADCAST
68 depends on GENERIC_CLOCKEVENTS
77 select GENERIC_ALLOCATOR
88 The Extended Industry Standard Architecture (EISA) bus was
89 developed as an open alternative to the IBM MicroChannel bus.
91 The EISA bus provided some of the features of the IBM MicroChannel
92 bus while maintaining backward compatibility with cards made for
93 the older ISA bus. The EISA bus saw limited use between 1988 and
94 1995 when it was made obsolete by the PCI bus.
96 Say Y here if you are building a kernel for an EISA-based machine.
106 MicroChannel Architecture is found in some IBM PS/2 machines and
107 laptops. It is a bus system similar to PCI or ISA. See
108 <file:Documentation/mca.txt> (and especially the web page given
109 there) before attempting to build an MCA bus kernel.
111 config STACKTRACE_SUPPORT
115 config HAVE_LATENCYTOP_SUPPORT
120 config LOCKDEP_SUPPORT
124 config TRACE_IRQFLAGS_SUPPORT
128 config HARDIRQS_SW_RESEND
132 config GENERIC_IRQ_PROBE
136 config GENERIC_LOCKBREAK
139 depends on SMP && PREEMPT
141 config RWSEM_GENERIC_SPINLOCK
145 config RWSEM_XCHGADD_ALGORITHM
148 config ARCH_HAS_ILOG2_U32
151 config ARCH_HAS_ILOG2_U64
154 config ARCH_HAS_CPUFREQ
157 Internal node to signify that the ARCH has CPUFREQ support
158 and that the relevant menu configurations are displayed for
161 config ARCH_HAS_CPU_IDLE_WAIT
164 config GENERIC_HWEIGHT
168 config GENERIC_CALIBRATE_DELAY
172 config ARCH_MAY_HAVE_PC_FDC
178 config NEED_DMA_MAP_STATE
181 config GENERIC_ISA_DMA
192 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
193 default DRAM_BASE if REMAP_VECTORS_TO_RAM
196 The base address of exception vectors.
198 config ARM_PATCH_PHYS_VIRT
199 bool "Patch physical to virtual translations at runtime" if EMBEDDED
201 depends on !XIP_KERNEL && MMU
202 depends on !ARCH_REALVIEW || !SPARSEMEM
204 Patch phys-to-virt and virt-to-phys translation functions at
205 boot and module load time according to the position of the
206 kernel in system memory.
208 This can only be used with non-XIP MMU kernels where the base
209 of physical memory is at a 16MB boundary.
211 Only disable this option if you know that you do not require
212 this feature (eg, building a kernel for a single machine) and
213 you need to shrink the kernel to the minimal size.
215 config NEED_MACH_MEMORY_H
218 Select this when mach/memory.h is required to provide special
219 definitions for this platform. The need for mach/memory.h should
220 be avoided when possible.
223 hex "Physical address of main memory"
224 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
226 Please provide the physical address corresponding to the
227 location of main memory in your system.
233 source "init/Kconfig"
235 source "kernel/Kconfig.freezer"
240 bool "MMU-based Paged Memory Management Support"
243 Select if you want MMU-based virtualised addressing space
244 support by paged memory management. If unsure, say 'Y'.
247 # The "ARM system type" choice list is ordered alphabetically by option
248 # text. Please add new entries in the option alphabetic order.
251 prompt "ARM system type"
252 default ARCH_VERSATILE
254 config ARCH_INTEGRATOR
255 bool "ARM Ltd. Integrator family"
257 select ARCH_HAS_CPUFREQ
259 select HAVE_MACH_CLKDEV
261 select GENERIC_CLOCKEVENTS
262 select PLAT_VERSATILE
263 select PLAT_VERSATILE_FPGA_IRQ
264 select NEED_MACH_MEMORY_H
266 Support for ARM's Integrator platform.
269 bool "ARM Ltd. RealView family"
272 select HAVE_MACH_CLKDEV
274 select GENERIC_CLOCKEVENTS
275 select ARCH_WANT_OPTIONAL_GPIOLIB
276 select PLAT_VERSATILE
277 select PLAT_VERSATILE_CLCD
278 select ARM_TIMER_SP804
279 select GPIO_PL061 if GPIOLIB
280 select NEED_MACH_MEMORY_H
282 This enables support for ARM Ltd RealView boards.
284 config ARCH_VERSATILE
285 bool "ARM Ltd. Versatile family"
289 select HAVE_MACH_CLKDEV
291 select GENERIC_CLOCKEVENTS
292 select ARCH_WANT_OPTIONAL_GPIOLIB
293 select PLAT_VERSATILE
294 select PLAT_VERSATILE_CLCD
295 select PLAT_VERSATILE_FPGA_IRQ
296 select ARM_TIMER_SP804
298 This enables support for ARM Ltd Versatile board.
301 bool "ARM Ltd. Versatile Express family"
302 select ARCH_WANT_OPTIONAL_GPIOLIB
304 select ARM_TIMER_SP804
306 select HAVE_MACH_CLKDEV
307 select GENERIC_CLOCKEVENTS
309 select HAVE_PATA_PLATFORM
311 select PLAT_VERSATILE
312 select PLAT_VERSATILE_CLCD
314 This enables support for the ARM Ltd Versatile Express boards.
318 select ARCH_REQUIRE_GPIOLIB
322 This enables support for systems based on the Atmel AT91RM9200,
323 AT91SAM9 and AT91CAP9 processors.
326 bool "Broadcom BCMRING"
330 select ARM_TIMER_SP804
332 select GENERIC_CLOCKEVENTS
333 select ARCH_WANT_OPTIONAL_GPIOLIB
335 Support for Broadcom's BCMRing platform.
338 bool "Cirrus Logic CLPS711x/EP721x-based"
340 select ARCH_USES_GETTIMEOFFSET
341 select NEED_MACH_MEMORY_H
343 Support for Cirrus Logic 711x/721x based boards.
346 bool "Cavium Networks CNS3XXX family"
348 select GENERIC_CLOCKEVENTS
350 select MIGHT_HAVE_PCI
351 select PCI_DOMAINS if PCI
353 Support for Cavium Networks CNS3XXX platform.
356 bool "Cortina Systems Gemini"
358 select ARCH_REQUIRE_GPIOLIB
359 select ARCH_USES_GETTIMEOFFSET
361 Support for the Cortina Systems Gemini family SoCs
364 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
367 select GENERIC_CLOCKEVENTS
369 select GENERIC_IRQ_CHIP
373 Support for CSR SiRFSoC ARM Cortex A9 Platform
380 select ARCH_USES_GETTIMEOFFSET
381 select NEED_MACH_MEMORY_H
383 This is an evaluation board for the StrongARM processor available
384 from Digital. It has limited hardware on-board, including an
385 Ethernet interface, two PCMCIA sockets, two serial ports and a
394 select ARCH_REQUIRE_GPIOLIB
395 select ARCH_HAS_HOLES_MEMORYMODEL
396 select ARCH_USES_GETTIMEOFFSET
399 This enables support for the Cirrus EP93xx series of CPUs.
401 config ARCH_FOOTBRIDGE
405 select GENERIC_CLOCKEVENTS
407 select NEED_MACH_MEMORY_H
409 Support for systems based on the DC21285 companion chip
410 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
413 bool "Freescale MXC/iMX-based"
414 select GENERIC_CLOCKEVENTS
415 select ARCH_REQUIRE_GPIOLIB
418 select GENERIC_IRQ_CHIP
419 select HAVE_SCHED_CLOCK
421 Support for Freescale MXC/iMX-based family of processors
424 bool "Freescale MXS-based"
425 select GENERIC_CLOCKEVENTS
426 select ARCH_REQUIRE_GPIOLIB
430 Support for Freescale MXS-based family of processors
433 bool "Hilscher NetX based"
437 select GENERIC_CLOCKEVENTS
439 This enables support for systems based on the Hilscher NetX Soc
442 bool "Hynix HMS720x-based"
445 select ARCH_USES_GETTIMEOFFSET
447 This enables support for systems based on the Hynix HMS720x
455 select ARCH_SUPPORTS_MSI
457 select NEED_MACH_MEMORY_H
459 Support for Intel's IOP13XX (XScale) family of processors.
467 select ARCH_REQUIRE_GPIOLIB
469 Support for Intel's 80219 and IOP32X (XScale) family of
478 select ARCH_REQUIRE_GPIOLIB
480 Support for Intel's IOP33X (XScale) family of processors.
487 select ARCH_USES_GETTIMEOFFSET
488 select NEED_MACH_MEMORY_H
490 Support for Intel's IXP23xx (XScale) family of processors.
493 bool "IXP2400/2800-based"
497 select ARCH_USES_GETTIMEOFFSET
498 select NEED_MACH_MEMORY_H
500 Support for Intel's IXP2400/2800 (XScale) family of processors.
508 select GENERIC_CLOCKEVENTS
509 select HAVE_SCHED_CLOCK
510 select MIGHT_HAVE_PCI
511 select DMABOUNCE if PCI
513 Support for Intel's IXP4XX (XScale) family of processors.
519 select ARCH_REQUIRE_GPIOLIB
520 select GENERIC_CLOCKEVENTS
523 Support for the Marvell Dove SoC 88AP510
526 bool "Marvell Kirkwood"
529 select ARCH_REQUIRE_GPIOLIB
530 select GENERIC_CLOCKEVENTS
533 Support for the following Marvell Kirkwood series SoCs:
534 88F6180, 88F6192 and 88F6281.
540 select ARCH_REQUIRE_GPIOLIB
543 select USB_ARCH_HAS_OHCI
545 select GENERIC_CLOCKEVENTS
547 Support for the NXP LPC32XX family of processors
550 bool "Marvell MV78xx0"
553 select ARCH_REQUIRE_GPIOLIB
554 select GENERIC_CLOCKEVENTS
557 Support for the following Marvell MV78xx0 series SoCs:
565 select ARCH_REQUIRE_GPIOLIB
566 select GENERIC_CLOCKEVENTS
569 Support for the following Marvell Orion 5x series SoCs:
570 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
571 Orion-2 (5281), Orion-1-90 (6183).
574 bool "Marvell PXA168/910/MMP2"
576 select ARCH_REQUIRE_GPIOLIB
578 select GENERIC_CLOCKEVENTS
579 select HAVE_SCHED_CLOCK
584 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
587 bool "Micrel/Kendin KS8695"
589 select ARCH_REQUIRE_GPIOLIB
590 select ARCH_USES_GETTIMEOFFSET
591 select NEED_MACH_MEMORY_H
593 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
594 System-on-Chip devices.
597 bool "Nuvoton W90X900 CPU"
599 select ARCH_REQUIRE_GPIOLIB
602 select GENERIC_CLOCKEVENTS
604 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
605 At present, the w90x900 has been renamed nuc900, regarding
606 the ARM series product line, you can login the following
607 link address to know more.
609 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
610 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
613 bool "Nuvoton NUC93X CPU"
617 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
618 low-power and high performance MPEG-4/JPEG multimedia controller chip.
624 select GENERIC_CLOCKEVENTS
627 select HAVE_SCHED_CLOCK
628 select ARCH_HAS_CPUFREQ
630 This enables support for NVIDIA Tegra based systems (Tegra APX,
631 Tegra 6xx and Tegra 2 series).
634 bool "Philips Nexperia PNX4008 Mobile"
637 select ARCH_USES_GETTIMEOFFSET
639 This enables support for Philips PNX4008 mobile platform.
642 bool "PXA2xx/PXA3xx-based"
645 select ARCH_HAS_CPUFREQ
648 select ARCH_REQUIRE_GPIOLIB
649 select GENERIC_CLOCKEVENTS
650 select HAVE_SCHED_CLOCK
655 select MULTI_IRQ_HANDLER
656 select ARM_CPU_SUSPEND if PM
659 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
664 select GENERIC_CLOCKEVENTS
665 select ARCH_REQUIRE_GPIOLIB
668 Support for Qualcomm MSM/QSD based systems. This runs on the
669 apps processor of the MSM/QSD and depends on a shared memory
670 interface to the modem processor which runs the baseband
671 stack and controls some vital subsystems
672 (clock and power control, etc).
675 bool "Renesas SH-Mobile / R-Mobile"
678 select HAVE_MACH_CLKDEV
679 select GENERIC_CLOCKEVENTS
682 select MULTI_IRQ_HANDLER
683 select PM_GENERIC_DOMAINS if PM
684 select NEED_MACH_MEMORY_H
686 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
693 select ARCH_MAY_HAVE_PC_FDC
694 select HAVE_PATA_PLATFORM
697 select ARCH_SPARSEMEM_ENABLE
698 select ARCH_USES_GETTIMEOFFSET
700 select NEED_MACH_MEMORY_H
702 On the Acorn Risc-PC, Linux can support the internal IDE disk and
703 CD-ROM interface, serial and parallel port, and the floppy drive.
710 select ARCH_SPARSEMEM_ENABLE
712 select ARCH_HAS_CPUFREQ
714 select GENERIC_CLOCKEVENTS
716 select HAVE_SCHED_CLOCK
718 select ARCH_REQUIRE_GPIOLIB
720 select NEED_MACH_MEMORY_H
722 Support for StrongARM 11x0 based boards.
725 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
727 select ARCH_HAS_CPUFREQ
730 select ARCH_USES_GETTIMEOFFSET
731 select HAVE_S3C2410_I2C if I2C
733 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
734 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
735 the Samsung SMDK2410 development board (and derivatives).
737 Note, the S3C2416 and the S3C2450 are so close that they even share
738 the same SoC ID code. This means that there is no separate machine
739 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
742 bool "Samsung S3C64XX"
749 select ARCH_USES_GETTIMEOFFSET
750 select ARCH_HAS_CPUFREQ
751 select ARCH_REQUIRE_GPIOLIB
752 select SAMSUNG_CLKSRC
753 select SAMSUNG_IRQ_VIC_TIMER
754 select S3C_GPIO_TRACK
755 select S3C_GPIO_PULL_UPDOWN
756 select S3C_GPIO_CFG_S3C24XX
757 select S3C_GPIO_CFG_S3C64XX
759 select USB_ARCH_HAS_OHCI
760 select SAMSUNG_GPIOLIB_4BIT
761 select HAVE_S3C2410_I2C if I2C
762 select HAVE_S3C2410_WATCHDOG if WATCHDOG
764 Samsung S3C64XX series based systems
767 bool "Samsung S5P6440 S5P6450"
773 select HAVE_S3C2410_WATCHDOG if WATCHDOG
774 select GENERIC_CLOCKEVENTS
775 select HAVE_SCHED_CLOCK
776 select HAVE_S3C2410_I2C if I2C
777 select HAVE_S3C_RTC if RTC_CLASS
779 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
783 bool "Samsung S5PC100"
788 select ARM_L1_CACHE_SHIFT_6
789 select ARCH_USES_GETTIMEOFFSET
790 select HAVE_S3C2410_I2C if I2C
791 select HAVE_S3C_RTC if RTC_CLASS
792 select HAVE_S3C2410_WATCHDOG if WATCHDOG
794 Samsung S5PC100 series based systems
797 bool "Samsung S5PV210/S5PC110"
799 select ARCH_SPARSEMEM_ENABLE
800 select ARCH_HAS_HOLES_MEMORYMODEL
805 select ARM_L1_CACHE_SHIFT_6
806 select ARCH_HAS_CPUFREQ
807 select GENERIC_CLOCKEVENTS
808 select HAVE_SCHED_CLOCK
809 select HAVE_S3C2410_I2C if I2C
810 select HAVE_S3C_RTC if RTC_CLASS
811 select HAVE_S3C2410_WATCHDOG if WATCHDOG
812 select NEED_MACH_MEMORY_H
814 Samsung S5PV210/S5PC110 series based systems
817 bool "Samsung EXYNOS4"
819 select ARCH_SPARSEMEM_ENABLE
820 select ARCH_HAS_HOLES_MEMORYMODEL
824 select ARCH_HAS_CPUFREQ
825 select GENERIC_CLOCKEVENTS
826 select HAVE_S3C_RTC if RTC_CLASS
827 select HAVE_S3C2410_I2C if I2C
828 select HAVE_S3C2410_WATCHDOG if WATCHDOG
829 select NEED_MACH_MEMORY_H
831 Samsung EXYNOS4 series based systems
840 select ARCH_USES_GETTIMEOFFSET
841 select NEED_MACH_MEMORY_H
843 Support for the StrongARM based Digital DNARD machine, also known
844 as "Shark" (<http://www.shark-linux.de/shark.html>).
847 bool "Telechips TCC ARM926-based systems"
852 select GENERIC_CLOCKEVENTS
854 Support for Telechips TCC ARM926-based systems.
857 bool "ST-Ericsson U300 Series"
861 select HAVE_SCHED_CLOCK
865 select GENERIC_CLOCKEVENTS
867 select HAVE_MACH_CLKDEV
869 select ARCH_REQUIRE_GPIOLIB
870 select NEED_MACH_MEMORY_H
872 Support for ST-Ericsson U300 series mobile platforms.
875 bool "ST-Ericsson U8500 Series"
878 select GENERIC_CLOCKEVENTS
880 select ARCH_REQUIRE_GPIOLIB
881 select ARCH_HAS_CPUFREQ
883 Support for ST-Ericsson's Ux500 architecture
886 bool "STMicroelectronics Nomadik"
891 select GENERIC_CLOCKEVENTS
892 select ARCH_REQUIRE_GPIOLIB
894 Support for the Nomadik platform by ST-Ericsson
898 select GENERIC_CLOCKEVENTS
899 select ARCH_REQUIRE_GPIOLIB
903 select GENERIC_ALLOCATOR
904 select GENERIC_IRQ_CHIP
905 select ARCH_HAS_HOLES_MEMORYMODEL
907 Support for TI's DaVinci platform.
912 select ARCH_REQUIRE_GPIOLIB
913 select ARCH_HAS_CPUFREQ
915 select GENERIC_CLOCKEVENTS
916 select HAVE_SCHED_CLOCK
917 select ARCH_HAS_HOLES_MEMORYMODEL
919 Support for TI's OMAP platform (OMAP1/2/3/4).
924 select ARCH_REQUIRE_GPIOLIB
927 select GENERIC_CLOCKEVENTS
930 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
933 bool "VIA/WonderMedia 85xx"
936 select ARCH_HAS_CPUFREQ
937 select GENERIC_CLOCKEVENTS
938 select ARCH_REQUIRE_GPIOLIB
941 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
944 bool "Xilinx Zynq ARM Cortex A9 Platform"
946 select GENERIC_CLOCKEVENTS
953 Support for Xilinx Zynq ARM Cortex A9 Platform
957 # This is sorted alphabetically by mach-* pathname. However, plat-*
958 # Kconfigs may be included either alphabetically (according to the
959 # plat- suffix) or along side the corresponding mach-* source.
961 source "arch/arm/mach-at91/Kconfig"
963 source "arch/arm/mach-bcmring/Kconfig"
965 source "arch/arm/mach-clps711x/Kconfig"
967 source "arch/arm/mach-cns3xxx/Kconfig"
969 source "arch/arm/mach-davinci/Kconfig"
971 source "arch/arm/mach-dove/Kconfig"
973 source "arch/arm/mach-ep93xx/Kconfig"
975 source "arch/arm/mach-footbridge/Kconfig"
977 source "arch/arm/mach-gemini/Kconfig"
979 source "arch/arm/mach-h720x/Kconfig"
981 source "arch/arm/mach-integrator/Kconfig"
983 source "arch/arm/mach-iop32x/Kconfig"
985 source "arch/arm/mach-iop33x/Kconfig"
987 source "arch/arm/mach-iop13xx/Kconfig"
989 source "arch/arm/mach-ixp4xx/Kconfig"
991 source "arch/arm/mach-ixp2000/Kconfig"
993 source "arch/arm/mach-ixp23xx/Kconfig"
995 source "arch/arm/mach-kirkwood/Kconfig"
997 source "arch/arm/mach-ks8695/Kconfig"
999 source "arch/arm/mach-lpc32xx/Kconfig"
1001 source "arch/arm/mach-msm/Kconfig"
1003 source "arch/arm/mach-mv78xx0/Kconfig"
1005 source "arch/arm/plat-mxc/Kconfig"
1007 source "arch/arm/mach-mxs/Kconfig"
1009 source "arch/arm/mach-netx/Kconfig"
1011 source "arch/arm/mach-nomadik/Kconfig"
1012 source "arch/arm/plat-nomadik/Kconfig"
1014 source "arch/arm/mach-nuc93x/Kconfig"
1016 source "arch/arm/plat-omap/Kconfig"
1018 source "arch/arm/mach-omap1/Kconfig"
1020 source "arch/arm/mach-omap2/Kconfig"
1022 source "arch/arm/mach-orion5x/Kconfig"
1024 source "arch/arm/mach-pxa/Kconfig"
1025 source "arch/arm/plat-pxa/Kconfig"
1027 source "arch/arm/mach-mmp/Kconfig"
1029 source "arch/arm/mach-realview/Kconfig"
1031 source "arch/arm/mach-sa1100/Kconfig"
1033 source "arch/arm/plat-samsung/Kconfig"
1034 source "arch/arm/plat-s3c24xx/Kconfig"
1035 source "arch/arm/plat-s5p/Kconfig"
1037 source "arch/arm/plat-spear/Kconfig"
1039 source "arch/arm/plat-tcc/Kconfig"
1042 source "arch/arm/mach-s3c2410/Kconfig"
1043 source "arch/arm/mach-s3c2412/Kconfig"
1044 source "arch/arm/mach-s3c2416/Kconfig"
1045 source "arch/arm/mach-s3c2440/Kconfig"
1046 source "arch/arm/mach-s3c2443/Kconfig"
1050 source "arch/arm/mach-s3c64xx/Kconfig"
1053 source "arch/arm/mach-s5p64x0/Kconfig"
1055 source "arch/arm/mach-s5pc100/Kconfig"
1057 source "arch/arm/mach-s5pv210/Kconfig"
1059 source "arch/arm/mach-exynos4/Kconfig"
1061 source "arch/arm/mach-shmobile/Kconfig"
1063 source "arch/arm/mach-tegra/Kconfig"
1065 source "arch/arm/mach-u300/Kconfig"
1067 source "arch/arm/mach-ux500/Kconfig"
1069 source "arch/arm/mach-versatile/Kconfig"
1071 source "arch/arm/mach-vexpress/Kconfig"
1072 source "arch/arm/plat-versatile/Kconfig"
1074 source "arch/arm/mach-vt8500/Kconfig"
1076 source "arch/arm/mach-w90x900/Kconfig"
1078 # Definitions to make life easier
1084 select GENERIC_CLOCKEVENTS
1085 select HAVE_SCHED_CLOCK
1090 select GENERIC_IRQ_CHIP
1091 select HAVE_SCHED_CLOCK
1096 config PLAT_VERSATILE
1099 config ARM_TIMER_SP804
1103 source arch/arm/mm/Kconfig
1106 bool "Enable iWMMXt support"
1107 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1108 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1110 Enable support for iWMMXt context switching at run time if
1111 running on a CPU that supports it.
1113 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1116 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1120 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1121 (!ARCH_OMAP3 || OMAP3_EMU)
1125 config MULTI_IRQ_HANDLER
1128 Allow each machine to specify it's own IRQ handler at run time.
1131 source "arch/arm/Kconfig-nommu"
1134 config ARM_ERRATA_411920
1135 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1136 depends on CPU_V6 || CPU_V6K
1138 Invalidation of the Instruction Cache operation can
1139 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1140 It does not affect the MPCore. This option enables the ARM Ltd.
1141 recommended workaround.
1143 config ARM_ERRATA_430973
1144 bool "ARM errata: Stale prediction on replaced interworking branch"
1147 This option enables the workaround for the 430973 Cortex-A8
1148 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1149 interworking branch is replaced with another code sequence at the
1150 same virtual address, whether due to self-modifying code or virtual
1151 to physical address re-mapping, Cortex-A8 does not recover from the
1152 stale interworking branch prediction. This results in Cortex-A8
1153 executing the new code sequence in the incorrect ARM or Thumb state.
1154 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1155 and also flushes the branch target cache at every context switch.
1156 Note that setting specific bits in the ACTLR register may not be
1157 available in non-secure mode.
1159 config ARM_ERRATA_458693
1160 bool "ARM errata: Processor deadlock when a false hazard is created"
1163 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1164 erratum. For very specific sequences of memory operations, it is
1165 possible for a hazard condition intended for a cache line to instead
1166 be incorrectly associated with a different cache line. This false
1167 hazard might then cause a processor deadlock. The workaround enables
1168 the L1 caching of the NEON accesses and disables the PLD instruction
1169 in the ACTLR register. Note that setting specific bits in the ACTLR
1170 register may not be available in non-secure mode.
1172 config ARM_ERRATA_460075
1173 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1176 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1177 erratum. Any asynchronous access to the L2 cache may encounter a
1178 situation in which recent store transactions to the L2 cache are lost
1179 and overwritten with stale memory contents from external memory. The
1180 workaround disables the write-allocate mode for the L2 cache via the
1181 ACTLR register. Note that setting specific bits in the ACTLR register
1182 may not be available in non-secure mode.
1184 config ARM_ERRATA_742230
1185 bool "ARM errata: DMB operation may be faulty"
1186 depends on CPU_V7 && SMP
1188 This option enables the workaround for the 742230 Cortex-A9
1189 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1190 between two write operations may not ensure the correct visibility
1191 ordering of the two writes. This workaround sets a specific bit in
1192 the diagnostic register of the Cortex-A9 which causes the DMB
1193 instruction to behave as a DSB, ensuring the correct behaviour of
1196 config ARM_ERRATA_742231
1197 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1198 depends on CPU_V7 && SMP
1200 This option enables the workaround for the 742231 Cortex-A9
1201 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1202 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1203 accessing some data located in the same cache line, may get corrupted
1204 data due to bad handling of the address hazard when the line gets
1205 replaced from one of the CPUs at the same time as another CPU is
1206 accessing it. This workaround sets specific bits in the diagnostic
1207 register of the Cortex-A9 which reduces the linefill issuing
1208 capabilities of the processor.
1210 config PL310_ERRATA_588369
1211 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1212 depends on CACHE_L2X0
1214 The PL310 L2 cache controller implements three types of Clean &
1215 Invalidate maintenance operations: by Physical Address
1216 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1217 They are architecturally defined to behave as the execution of a
1218 clean operation followed immediately by an invalidate operation,
1219 both performing to the same memory location. This functionality
1220 is not correctly implemented in PL310 as clean lines are not
1221 invalidated as a result of these operations.
1223 config ARM_ERRATA_720789
1224 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1225 depends on CPU_V7 && SMP
1227 This option enables the workaround for the 720789 Cortex-A9 (prior to
1228 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1229 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1230 As a consequence of this erratum, some TLB entries which should be
1231 invalidated are not, resulting in an incoherency in the system page
1232 tables. The workaround changes the TLB flushing routines to invalidate
1233 entries regardless of the ASID.
1235 config PL310_ERRATA_727915
1236 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1237 depends on CACHE_L2X0
1239 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1240 operation (offset 0x7FC). This operation runs in background so that
1241 PL310 can handle normal accesses while it is in progress. Under very
1242 rare circumstances, due to this erratum, write data can be lost when
1243 PL310 treats a cacheable write transaction during a Clean &
1244 Invalidate by Way operation.
1246 config ARM_ERRATA_743622
1247 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1250 This option enables the workaround for the 743622 Cortex-A9
1251 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1252 optimisation in the Cortex-A9 Store Buffer may lead to data
1253 corruption. This workaround sets a specific bit in the diagnostic
1254 register of the Cortex-A9 which disables the Store Buffer
1255 optimisation, preventing the defect from occurring. This has no
1256 visible impact on the overall performance or power consumption of the
1259 config ARM_ERRATA_751472
1260 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1261 depends on CPU_V7 && SMP
1263 This option enables the workaround for the 751472 Cortex-A9 (prior
1264 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1265 completion of a following broadcasted operation if the second
1266 operation is received by a CPU before the ICIALLUIS has completed,
1267 potentially leading to corrupted entries in the cache or TLB.
1269 config ARM_ERRATA_753970
1270 bool "ARM errata: cache sync operation may be faulty"
1271 depends on CACHE_PL310
1273 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1275 Under some condition the effect of cache sync operation on
1276 the store buffer still remains when the operation completes.
1277 This means that the store buffer is always asked to drain and
1278 this prevents it from merging any further writes. The workaround
1279 is to replace the normal offset of cache sync operation (0x730)
1280 by another offset targeting an unmapped PL310 register 0x740.
1281 This has the same effect as the cache sync operation: store buffer
1282 drain and waiting for all buffers empty.
1284 config ARM_ERRATA_754322
1285 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1288 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1289 r3p*) erratum. A speculative memory access may cause a page table walk
1290 which starts prior to an ASID switch but completes afterwards. This
1291 can populate the micro-TLB with a stale entry which may be hit with
1292 the new ASID. This workaround places two dsb instructions in the mm
1293 switching code so that no page table walks can cross the ASID switch.
1295 config ARM_ERRATA_754327
1296 bool "ARM errata: no automatic Store Buffer drain"
1297 depends on CPU_V7 && SMP
1299 This option enables the workaround for the 754327 Cortex-A9 (prior to
1300 r2p0) erratum. The Store Buffer does not have any automatic draining
1301 mechanism and therefore a livelock may occur if an external agent
1302 continuously polls a memory location waiting to observe an update.
1303 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1304 written polling loops from denying visibility of updates to memory.
1306 config ARM_ERRATA_364296
1307 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1308 depends on CPU_V6 && !SMP
1310 This options enables the workaround for the 364296 ARM1136
1311 r0p2 erratum (possible cache data corruption with
1312 hit-under-miss enabled). It sets the undocumented bit 31 in
1313 the auxiliary control register and the FI bit in the control
1314 register, thus disabling hit-under-miss without putting the
1315 processor into full low interrupt latency mode. ARM11MPCore
1318 config ARM_ERRATA_764369
1319 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1320 depends on CPU_V7 && SMP
1322 This option enables the workaround for erratum 764369
1323 affecting Cortex-A9 MPCore with two or more processors (all
1324 current revisions). Under certain timing circumstances, a data
1325 cache line maintenance operation by MVA targeting an Inner
1326 Shareable memory region may fail to proceed up to either the
1327 Point of Coherency or to the Point of Unification of the
1328 system. This workaround adds a DSB instruction before the
1329 relevant cache maintenance functions and sets a specific bit
1330 in the diagnostic control register of the SCU.
1334 source "arch/arm/common/Kconfig"
1344 Find out whether you have ISA slots on your motherboard. ISA is the
1345 name of a bus system, i.e. the way the CPU talks to the other stuff
1346 inside your box. Other bus systems are PCI, EISA, MicroChannel
1347 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1348 newer boards don't support it. If you have ISA, say Y, otherwise N.
1350 # Select ISA DMA controller support
1355 # Select ISA DMA interface
1360 bool "PCI support" if MIGHT_HAVE_PCI
1362 Find out whether you have a PCI motherboard. PCI is the name of a
1363 bus system, i.e. the way the CPU talks to the other stuff inside
1364 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1365 VESA. If you have PCI, say Y, otherwise N.
1371 config PCI_NANOENGINE
1372 bool "BSE nanoEngine PCI support"
1373 depends on SA1100_NANOENGINE
1375 Enable PCI on the BSE nanoEngine board.
1380 # Select the host bridge type
1381 config PCI_HOST_VIA82C505
1383 depends on PCI && ARCH_SHARK
1386 config PCI_HOST_ITE8152
1388 depends on PCI && MACH_ARMCORE
1392 source "drivers/pci/Kconfig"
1394 source "drivers/pcmcia/Kconfig"
1398 menu "Kernel Features"
1400 source "kernel/time/Kconfig"
1403 bool "Symmetric Multi-Processing"
1404 depends on CPU_V6K || CPU_V7
1405 depends on GENERIC_CLOCKEVENTS
1406 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1407 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1408 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1409 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1411 select USE_GENERIC_SMP_HELPERS
1412 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1414 This enables support for systems with more than one CPU. If you have
1415 a system with only one CPU, like most personal computers, say N. If
1416 you have a system with more than one CPU, say Y.
1418 If you say N here, the kernel will run on single and multiprocessor
1419 machines, but will use only one CPU of a multiprocessor machine. If
1420 you say Y here, the kernel will run on many, but not all, single
1421 processor machines. On a single processor machine, the kernel will
1422 run faster if you say N here.
1424 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1425 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1426 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1428 If you don't know what to do here, say N.
1431 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1432 depends on EXPERIMENTAL
1433 depends on SMP && !XIP_KERNEL
1436 SMP kernels contain instructions which fail on non-SMP processors.
1437 Enabling this option allows the kernel to modify itself to make
1438 these instructions safe. Disabling it allows about 1K of space
1441 If you don't know what to do here, say Y.
1443 config ARM_CPU_TOPOLOGY
1444 bool "Support cpu topology definition"
1445 depends on SMP && CPU_V7
1448 Support ARM cpu topology definition. The MPIDR register defines
1449 affinity between processors which is then used to describe the cpu
1450 topology of an ARM System.
1453 bool "Multi-core scheduler support"
1454 depends on ARM_CPU_TOPOLOGY
1456 Multi-core scheduler support improves the CPU scheduler's decision
1457 making when dealing with multi-core CPU chips at a cost of slightly
1458 increased overhead in some places. If unsure say N here.
1461 bool "SMT scheduler support"
1462 depends on ARM_CPU_TOPOLOGY
1464 Improves the CPU scheduler's decision making when dealing with
1465 MultiThreading at a cost of slightly increased overhead in some
1466 places. If unsure say N here.
1471 This option enables support for the ARM system coherency unit
1478 This options enables support for the ARM timer and watchdog unit
1481 prompt "Memory split"
1484 Select the desired split between kernel and user memory.
1486 If you are not absolutely sure what you are doing, leave this
1490 bool "3G/1G user/kernel split"
1492 bool "2G/2G user/kernel split"
1494 bool "1G/3G user/kernel split"
1499 default 0x40000000 if VMSPLIT_1G
1500 default 0x80000000 if VMSPLIT_2G
1504 int "Maximum number of CPUs (2-32)"
1510 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1511 depends on SMP && HOTPLUG && EXPERIMENTAL
1513 Say Y here to experiment with turning CPUs off and on. CPUs
1514 can be controlled through /sys/devices/system/cpu.
1517 bool "Use local timer interrupts"
1520 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1522 Enable support for local timers on SMP platforms, rather then the
1523 legacy IPI broadcast method. Local timers allows the system
1524 accounting to be spread across the timer interval, preventing a
1525 "thundering herd" at every timer tick.
1527 source kernel/Kconfig.preempt
1531 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1532 ARCH_S5PV210 || ARCH_EXYNOS4
1533 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1534 default AT91_TIMER_HZ if ARCH_AT91
1535 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1538 config THUMB2_KERNEL
1539 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1540 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1542 select ARM_ASM_UNIFIED
1545 By enabling this option, the kernel will be compiled in
1546 Thumb-2 mode. A compiler/assembler that understand the unified
1547 ARM-Thumb syntax is needed.
1551 config THUMB2_AVOID_R_ARM_THM_JUMP11
1552 bool "Work around buggy Thumb-2 short branch relocations in gas"
1553 depends on THUMB2_KERNEL && MODULES
1556 Various binutils versions can resolve Thumb-2 branches to
1557 locally-defined, preemptible global symbols as short-range "b.n"
1558 branch instructions.
1560 This is a problem, because there's no guarantee the final
1561 destination of the symbol, or any candidate locations for a
1562 trampoline, are within range of the branch. For this reason, the
1563 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1564 relocation in modules at all, and it makes little sense to add
1567 The symptom is that the kernel fails with an "unsupported
1568 relocation" error when loading some modules.
1570 Until fixed tools are available, passing
1571 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1572 code which hits this problem, at the cost of a bit of extra runtime
1573 stack usage in some cases.
1575 The problem is described in more detail at:
1576 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1578 Only Thumb-2 kernels are affected.
1580 Unless you are sure your tools don't have this problem, say Y.
1582 config ARM_ASM_UNIFIED
1586 bool "Use the ARM EABI to compile the kernel"
1588 This option allows for the kernel to be compiled using the latest
1589 ARM ABI (aka EABI). This is only useful if you are using a user
1590 space environment that is also compiled with EABI.
1592 Since there are major incompatibilities between the legacy ABI and
1593 EABI, especially with regard to structure member alignment, this
1594 option also changes the kernel syscall calling convention to
1595 disambiguate both ABIs and allow for backward compatibility support
1596 (selected with CONFIG_OABI_COMPAT).
1598 To use this you need GCC version 4.0.0 or later.
1601 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1602 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1605 This option preserves the old syscall interface along with the
1606 new (ARM EABI) one. It also provides a compatibility layer to
1607 intercept syscalls that have structure arguments which layout
1608 in memory differs between the legacy ABI and the new ARM EABI
1609 (only for non "thumb" binaries). This option adds a tiny
1610 overhead to all syscalls and produces a slightly larger kernel.
1611 If you know you'll be using only pure EABI user space then you
1612 can say N here. If this option is not selected and you attempt
1613 to execute a legacy ABI binary then the result will be
1614 UNPREDICTABLE (in fact it can be predicted that it won't work
1615 at all). If in doubt say Y.
1617 config ARCH_HAS_HOLES_MEMORYMODEL
1620 config ARCH_SPARSEMEM_ENABLE
1623 config ARCH_SPARSEMEM_DEFAULT
1624 def_bool ARCH_SPARSEMEM_ENABLE
1626 config ARCH_SELECT_MEMORY_MODEL
1627 def_bool ARCH_SPARSEMEM_ENABLE
1629 config HAVE_ARCH_PFN_VALID
1630 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1633 bool "High Memory Support"
1636 The address space of ARM processors is only 4 Gigabytes large
1637 and it has to accommodate user address space, kernel address
1638 space as well as some memory mapped IO. That means that, if you
1639 have a large amount of physical memory and/or IO, not all of the
1640 memory can be "permanently mapped" by the kernel. The physical
1641 memory that is not permanently mapped is called "high memory".
1643 Depending on the selected kernel/user memory split, minimum
1644 vmalloc space and actual amount of RAM, you may not need this
1645 option which should result in a slightly faster kernel.
1650 bool "Allocate 2nd-level pagetables from highmem"
1653 config HW_PERF_EVENTS
1654 bool "Enable hardware performance counter support for perf events"
1655 depends on PERF_EVENTS && CPU_HAS_PMU
1658 Enable hardware performance counter support for perf events. If
1659 disabled, perf events will use software events only.
1663 config FORCE_MAX_ZONEORDER
1664 int "Maximum zone order" if ARCH_SHMOBILE
1665 range 11 64 if ARCH_SHMOBILE
1666 default "9" if SA1111
1669 The kernel memory allocator divides physically contiguous memory
1670 blocks into "zones", where each zone is a power of two number of
1671 pages. This option selects the largest power of two that the kernel
1672 keeps in the memory allocator. If you need to allocate very large
1673 blocks of physically contiguous memory, then you may need to
1674 increase this value.
1676 This config option is actually maximum order plus one. For example,
1677 a value of 11 means that the largest free memory block is 2^10 pages.
1680 bool "Timer and CPU usage LEDs"
1681 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1682 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1683 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1684 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1685 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1686 ARCH_AT91 || ARCH_DAVINCI || \
1687 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1689 If you say Y here, the LEDs on your machine will be used
1690 to provide useful information about your current system status.
1692 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1693 be able to select which LEDs are active using the options below. If
1694 you are compiling a kernel for the EBSA-110 or the LART however, the
1695 red LED will simply flash regularly to indicate that the system is
1696 still functional. It is safe to say Y here if you have a CATS
1697 system, but the driver will do nothing.
1700 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1701 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1702 || MACH_OMAP_PERSEUS2
1704 depends on !GENERIC_CLOCKEVENTS
1705 default y if ARCH_EBSA110
1707 If you say Y here, one of the system LEDs (the green one on the
1708 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1709 will flash regularly to indicate that the system is still
1710 operational. This is mainly useful to kernel hackers who are
1711 debugging unstable kernels.
1713 The LART uses the same LED for both Timer LED and CPU usage LED
1714 functions. You may choose to use both, but the Timer LED function
1715 will overrule the CPU usage LED.
1718 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1720 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1721 || MACH_OMAP_PERSEUS2
1724 If you say Y here, the red LED will be used to give a good real
1725 time indication of CPU usage, by lighting whenever the idle task
1726 is not currently executing.
1728 The LART uses the same LED for both Timer LED and CPU usage LED
1729 functions. You may choose to use both, but the Timer LED function
1730 will overrule the CPU usage LED.
1732 config ALIGNMENT_TRAP
1734 depends on CPU_CP15_MMU
1735 default y if !ARCH_EBSA110
1736 select HAVE_PROC_CPU if PROC_FS
1738 ARM processors cannot fetch/store information which is not
1739 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1740 address divisible by 4. On 32-bit ARM processors, these non-aligned
1741 fetch/store instructions will be emulated in software if you say
1742 here, which has a severe performance impact. This is necessary for
1743 correct operation of some network protocols. With an IP-only
1744 configuration it is safe to say N, otherwise say Y.
1746 config UACCESS_WITH_MEMCPY
1747 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1748 depends on MMU && EXPERIMENTAL
1749 default y if CPU_FEROCEON
1751 Implement faster copy_to_user and clear_user methods for CPU
1752 cores where a 8-word STM instruction give significantly higher
1753 memory write throughput than a sequence of individual 32bit stores.
1755 A possible side effect is a slight increase in scheduling latency
1756 between threads sharing the same address space if they invoke
1757 such copy operations with large buffers.
1759 However, if the CPU data cache is using a write-allocate mode,
1760 this option is unlikely to provide any performance gain.
1764 prompt "Enable seccomp to safely compute untrusted bytecode"
1766 This kernel feature is useful for number crunching applications
1767 that may need to compute untrusted bytecode during their
1768 execution. By using pipes or other transports made available to
1769 the process as file descriptors supporting the read/write
1770 syscalls, it's possible to isolate those applications in
1771 their own address space using seccomp. Once seccomp is
1772 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1773 and the task is only allowed to execute a few safe syscalls
1774 defined by each seccomp mode.
1776 config CC_STACKPROTECTOR
1777 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1778 depends on EXPERIMENTAL
1780 This option turns on the -fstack-protector GCC feature. This
1781 feature puts, at the beginning of functions, a canary value on
1782 the stack just before the return address, and validates
1783 the value just before actually returning. Stack based buffer
1784 overflows (that need to overwrite this return address) now also
1785 overwrite the canary, which gets detected and the attack is then
1786 neutralized via a kernel panic.
1787 This feature requires gcc version 4.2 or above.
1789 config DEPRECATED_PARAM_STRUCT
1790 bool "Provide old way to pass kernel parameters"
1792 This was deprecated in 2001 and announced to live on for 5 years.
1793 Some old boot loaders still use this way.
1800 bool "Flattened Device Tree support"
1802 select OF_EARLY_FLATTREE
1805 Include support for flattened device tree machine descriptions.
1807 # Compressed boot loader in ROM. Yes, we really want to ask about
1808 # TEXT and BSS so we preserve their values in the config files.
1809 config ZBOOT_ROM_TEXT
1810 hex "Compressed ROM boot loader base address"
1813 The physical address at which the ROM-able zImage is to be
1814 placed in the target. Platforms which normally make use of
1815 ROM-able zImage formats normally set this to a suitable
1816 value in their defconfig file.
1818 If ZBOOT_ROM is not enabled, this has no effect.
1820 config ZBOOT_ROM_BSS
1821 hex "Compressed ROM boot loader BSS address"
1824 The base address of an area of read/write memory in the target
1825 for the ROM-able zImage which must be available while the
1826 decompressor is running. It must be large enough to hold the
1827 entire decompressed kernel plus an additional 128 KiB.
1828 Platforms which normally make use of ROM-able zImage formats
1829 normally set this to a suitable value in their defconfig file.
1831 If ZBOOT_ROM is not enabled, this has no effect.
1834 bool "Compressed boot loader in ROM/flash"
1835 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1837 Say Y here if you intend to execute your compressed kernel image
1838 (zImage) directly from ROM or flash. If unsure, say N.
1841 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1842 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1843 default ZBOOT_ROM_NONE
1845 Include experimental SD/MMC loading code in the ROM-able zImage.
1846 With this enabled it is possible to write the the ROM-able zImage
1847 kernel image to an MMC or SD card and boot the kernel straight
1848 from the reset vector. At reset the processor Mask ROM will load
1849 the first part of the the ROM-able zImage which in turn loads the
1850 rest the kernel image to RAM.
1852 config ZBOOT_ROM_NONE
1853 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1855 Do not load image from SD or MMC
1857 config ZBOOT_ROM_MMCIF
1858 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1860 Load image from MMCIF hardware block.
1862 config ZBOOT_ROM_SH_MOBILE_SDHI
1863 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1865 Load image from SDHI hardware block
1869 config ARM_APPENDED_DTB
1870 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1871 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1873 With this option, the boot code will look for a device tree binary
1874 (DTB) appended to zImage
1875 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1877 This is meant as a backward compatibility convenience for those
1878 systems with a bootloader that can't be upgraded to accommodate
1879 the documented boot protocol using a device tree.
1881 Beware that there is very little in terms of protection against
1882 this option being confused by leftover garbage in memory that might
1883 look like a DTB header after a reboot if no actual DTB is appended
1884 to zImage. Do not leave this option active in a production kernel
1885 if you don't intend to always append a DTB. Proper passing of the
1886 location into r2 of a bootloader provided DTB is always preferable
1889 config ARM_ATAG_DTB_COMPAT
1890 bool "Supplement the appended DTB with traditional ATAG information"
1891 depends on ARM_APPENDED_DTB
1893 Some old bootloaders can't be updated to a DTB capable one, yet
1894 they provide ATAGs with memory configuration, the ramdisk address,
1895 the kernel cmdline string, etc. Such information is dynamically
1896 provided by the bootloader and can't always be stored in a static
1897 DTB. To allow a device tree enabled kernel to be used with such
1898 bootloaders, this option allows zImage to extract the information
1899 from the ATAG list and store it at run time into the appended DTB.
1902 string "Default kernel command string"
1905 On some architectures (EBSA110 and CATS), there is currently no way
1906 for the boot loader to pass arguments to the kernel. For these
1907 architectures, you should supply some command-line options at build
1908 time by entering them here. As a minimum, you should specify the
1909 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1912 prompt "Kernel command line type" if CMDLINE != ""
1913 default CMDLINE_FROM_BOOTLOADER
1915 config CMDLINE_FROM_BOOTLOADER
1916 bool "Use bootloader kernel arguments if available"
1918 Uses the command-line options passed by the boot loader. If
1919 the boot loader doesn't provide any, the default kernel command
1920 string provided in CMDLINE will be used.
1922 config CMDLINE_EXTEND
1923 bool "Extend bootloader kernel arguments"
1925 The command-line arguments provided by the boot loader will be
1926 appended to the default kernel command string.
1928 config CMDLINE_FORCE
1929 bool "Always use the default kernel command string"
1931 Always use the default kernel command string, even if the boot
1932 loader passes other arguments to the kernel.
1933 This is useful if you cannot or don't want to change the
1934 command-line options your boot loader passes to the kernel.
1938 bool "Kernel Execute-In-Place from ROM"
1939 depends on !ZBOOT_ROM
1941 Execute-In-Place allows the kernel to run from non-volatile storage
1942 directly addressable by the CPU, such as NOR flash. This saves RAM
1943 space since the text section of the kernel is not loaded from flash
1944 to RAM. Read-write sections, such as the data section and stack,
1945 are still copied to RAM. The XIP kernel is not compressed since
1946 it has to run directly from flash, so it will take more space to
1947 store it. The flash address used to link the kernel object files,
1948 and for storing it, is configuration dependent. Therefore, if you
1949 say Y here, you must know the proper physical address where to
1950 store the kernel image depending on your own flash memory usage.
1952 Also note that the make target becomes "make xipImage" rather than
1953 "make zImage" or "make Image". The final kernel binary to put in
1954 ROM memory will be arch/arm/boot/xipImage.
1958 config XIP_PHYS_ADDR
1959 hex "XIP Kernel Physical Location"
1960 depends on XIP_KERNEL
1961 default "0x00080000"
1963 This is the physical address in your flash memory the kernel will
1964 be linked for and stored to. This address is dependent on your
1968 bool "Kexec system call (EXPERIMENTAL)"
1969 depends on EXPERIMENTAL
1971 kexec is a system call that implements the ability to shutdown your
1972 current kernel, and to start another kernel. It is like a reboot
1973 but it is independent of the system firmware. And like a reboot
1974 you can start any kernel with it, not just Linux.
1976 It is an ongoing process to be certain the hardware in a machine
1977 is properly shutdown, so do not be surprised if this code does not
1978 initially work for you. It may help to enable device hotplugging
1982 bool "Export atags in procfs"
1986 Should the atags used to boot the kernel be exported in an "atags"
1987 file in procfs. Useful with kexec.
1990 bool "Build kdump crash kernel (EXPERIMENTAL)"
1991 depends on EXPERIMENTAL
1993 Generate crash dump after being started by kexec. This should
1994 be normally only set in special crash dump kernels which are
1995 loaded in the main kernel with kexec-tools into a specially
1996 reserved region and then later executed after a crash by
1997 kdump/kexec. The crash dump kernel must be compiled to a
1998 memory address not used by the main kernel
2000 For more details see Documentation/kdump/kdump.txt
2002 config AUTO_ZRELADDR
2003 bool "Auto calculation of the decompressed kernel image address"
2004 depends on !ZBOOT_ROM && !ARCH_U300
2006 ZRELADDR is the physical address where the decompressed kernel
2007 image will be placed. If AUTO_ZRELADDR is selected, the address
2008 will be determined at run-time by masking the current IP with
2009 0xf8000000. This assumes the zImage being placed in the first 128MB
2010 from start of memory.
2014 menu "CPU Power Management"
2018 source "drivers/cpufreq/Kconfig"
2021 tristate "CPUfreq driver for i.MX CPUs"
2022 depends on ARCH_MXC && CPU_FREQ
2024 This enables the CPUfreq driver for i.MX CPUs.
2026 config CPU_FREQ_SA1100
2029 config CPU_FREQ_SA1110
2032 config CPU_FREQ_INTEGRATOR
2033 tristate "CPUfreq driver for ARM Integrator CPUs"
2034 depends on ARCH_INTEGRATOR && CPU_FREQ
2037 This enables the CPUfreq driver for ARM Integrator CPUs.
2039 For details, take a look at <file:Documentation/cpu-freq>.
2045 depends on CPU_FREQ && ARCH_PXA && PXA25x
2047 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2052 Internal configuration node for common cpufreq on Samsung SoC
2054 config CPU_FREQ_S3C24XX
2055 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2056 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
2059 This enables the CPUfreq driver for the Samsung S3C24XX family
2062 For details, take a look at <file:Documentation/cpu-freq>.
2066 config CPU_FREQ_S3C24XX_PLL
2067 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2068 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2070 Compile in support for changing the PLL frequency from the
2071 S3C24XX series CPUfreq driver. The PLL takes time to settle
2072 after a frequency change, so by default it is not enabled.
2074 This also means that the PLL tables for the selected CPU(s) will
2075 be built which may increase the size of the kernel image.
2077 config CPU_FREQ_S3C24XX_DEBUG
2078 bool "Debug CPUfreq Samsung driver core"
2079 depends on CPU_FREQ_S3C24XX
2081 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2083 config CPU_FREQ_S3C24XX_IODEBUG
2084 bool "Debug CPUfreq Samsung driver IO timing"
2085 depends on CPU_FREQ_S3C24XX
2087 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2089 config CPU_FREQ_S3C24XX_DEBUGFS
2090 bool "Export debugfs for CPUFreq"
2091 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2093 Export status information via debugfs.
2097 source "drivers/cpuidle/Kconfig"
2101 menu "Floating point emulation"
2103 comment "At least one emulation must be selected"
2106 bool "NWFPE math emulation"
2107 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2109 Say Y to include the NWFPE floating point emulator in the kernel.
2110 This is necessary to run most binaries. Linux does not currently
2111 support floating point hardware so you need to say Y here even if
2112 your machine has an FPA or floating point co-processor podule.
2114 You may say N here if you are going to load the Acorn FPEmulator
2115 early in the bootup.
2118 bool "Support extended precision"
2119 depends on FPE_NWFPE
2121 Say Y to include 80-bit support in the kernel floating-point
2122 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2123 Note that gcc does not generate 80-bit operations by default,
2124 so in most cases this option only enlarges the size of the
2125 floating point emulator without any good reason.
2127 You almost surely want to say N here.
2130 bool "FastFPE math emulation (EXPERIMENTAL)"
2131 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2133 Say Y here to include the FAST floating point emulator in the kernel.
2134 This is an experimental much faster emulator which now also has full
2135 precision for the mantissa. It does not support any exceptions.
2136 It is very simple, and approximately 3-6 times faster than NWFPE.
2138 It should be sufficient for most programs. It may be not suitable
2139 for scientific calculations, but you have to check this for yourself.
2140 If you do not feel you need a faster FP emulation you should better
2144 bool "VFP-format floating point maths"
2145 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2147 Say Y to include VFP support code in the kernel. This is needed
2148 if your hardware includes a VFP unit.
2150 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2151 release notes and additional status information.
2153 Say N if your target does not have VFP hardware.
2161 bool "Advanced SIMD (NEON) Extension support"
2162 depends on VFPv3 && CPU_V7
2164 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2169 menu "Userspace binary formats"
2171 source "fs/Kconfig.binfmt"
2174 tristate "RISC OS personality"
2177 Say Y here to include the kernel code necessary if you want to run
2178 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2179 experimental; if this sounds frightening, say N and sleep in peace.
2180 You can also say M here to compile this support as a module (which
2181 will be called arthur).
2185 menu "Power management options"
2187 source "kernel/power/Kconfig"
2189 config ARCH_SUSPEND_POSSIBLE
2190 depends on !ARCH_S5P64X0 && !ARCH_S5PC100
2191 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2192 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2195 config ARM_CPU_SUSPEND
2200 source "net/Kconfig"
2202 source "drivers/Kconfig"
2206 source "arch/arm/Kconfig.debug"
2208 source "security/Kconfig"
2210 source "crypto/Kconfig"
2212 source "lib/Kconfig"