5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if !XIP_KERNEL
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
32 select CPU_PM if (SUSPEND || CPU_IDLE)
34 The ARM series is a line of low-power-consumption RISC chip designs
35 licensed by ARM Ltd and targeted at embedded applications and
36 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
37 manufactured, but legacy ARM-based PC hardware remains popular in
38 Europe. There is an ARM Linux project with a web page at
39 <http://www.arm.linux.org.uk/>.
41 config ARM_HAS_SG_CHAIN
50 config SYS_SUPPORTS_APM_EMULATION
53 config HAVE_SCHED_CLOCK
59 config ARCH_USES_GETTIMEOFFSET
63 config GENERIC_CLOCKEVENTS
66 config GENERIC_CLOCKEVENTS_BROADCAST
68 depends on GENERIC_CLOCKEVENTS
77 select GENERIC_ALLOCATOR
88 The Extended Industry Standard Architecture (EISA) bus was
89 developed as an open alternative to the IBM MicroChannel bus.
91 The EISA bus provided some of the features of the IBM MicroChannel
92 bus while maintaining backward compatibility with cards made for
93 the older ISA bus. The EISA bus saw limited use between 1988 and
94 1995 when it was made obsolete by the PCI bus.
96 Say Y here if you are building a kernel for an EISA-based machine.
106 MicroChannel Architecture is found in some IBM PS/2 machines and
107 laptops. It is a bus system similar to PCI or ISA. See
108 <file:Documentation/mca.txt> (and especially the web page given
109 there) before attempting to build an MCA bus kernel.
111 config STACKTRACE_SUPPORT
115 config HAVE_LATENCYTOP_SUPPORT
120 config LOCKDEP_SUPPORT
124 config TRACE_IRQFLAGS_SUPPORT
128 config HARDIRQS_SW_RESEND
132 config GENERIC_IRQ_PROBE
136 config GENERIC_LOCKBREAK
139 depends on SMP && PREEMPT
141 config RWSEM_GENERIC_SPINLOCK
145 config RWSEM_XCHGADD_ALGORITHM
148 config ARCH_HAS_ILOG2_U32
151 config ARCH_HAS_ILOG2_U64
154 config ARCH_HAS_CPUFREQ
157 Internal node to signify that the ARCH has CPUFREQ support
158 and that the relevant menu configurations are displayed for
161 config ARCH_HAS_CPU_IDLE_WAIT
164 config GENERIC_HWEIGHT
168 config GENERIC_CALIBRATE_DELAY
172 config ARCH_MAY_HAVE_PC_FDC
178 config NEED_DMA_MAP_STATE
181 config GENERIC_ISA_DMA
192 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
193 default DRAM_BASE if REMAP_VECTORS_TO_RAM
196 The base address of exception vectors.
198 config ARM_PATCH_PHYS_VIRT
199 bool "Patch physical to virtual translations at runtime" if EMBEDDED
201 depends on !XIP_KERNEL && MMU
202 depends on !ARCH_REALVIEW || !SPARSEMEM
204 Patch phys-to-virt and virt-to-phys translation functions at
205 boot and module load time according to the position of the
206 kernel in system memory.
208 This can only be used with non-XIP MMU kernels where the base
209 of physical memory is at a 16MB boundary.
211 Only disable this option if you know that you do not require
212 this feature (eg, building a kernel for a single machine) and
213 you need to shrink the kernel to the minimal size.
215 config NEED_MACH_MEMORY_H
218 Select this when mach/memory.h is required to provide special
219 definitions for this platform. The need for mach/memory.h should
220 be avoided when possible.
223 hex "Physical address of main memory"
224 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
226 Please provide the physical address corresponding to the
227 location of main memory in your system.
229 source "init/Kconfig"
231 source "kernel/Kconfig.freezer"
236 bool "MMU-based Paged Memory Management Support"
239 Select if you want MMU-based virtualised addressing space
240 support by paged memory management. If unsure, say 'Y'.
243 # The "ARM system type" choice list is ordered alphabetically by option
244 # text. Please add new entries in the option alphabetic order.
247 prompt "ARM system type"
248 default ARCH_VERSATILE
250 config ARCH_INTEGRATOR
251 bool "ARM Ltd. Integrator family"
253 select ARCH_HAS_CPUFREQ
255 select HAVE_MACH_CLKDEV
257 select GENERIC_CLOCKEVENTS
258 select PLAT_VERSATILE
259 select PLAT_VERSATILE_FPGA_IRQ
260 select NEED_MACH_MEMORY_H
262 Support for ARM's Integrator platform.
265 bool "ARM Ltd. RealView family"
268 select HAVE_MACH_CLKDEV
270 select GENERIC_CLOCKEVENTS
271 select ARCH_WANT_OPTIONAL_GPIOLIB
272 select PLAT_VERSATILE
273 select PLAT_VERSATILE_CLCD
274 select ARM_TIMER_SP804
275 select GPIO_PL061 if GPIOLIB
276 select NEED_MACH_MEMORY_H
278 This enables support for ARM Ltd RealView boards.
280 config ARCH_VERSATILE
281 bool "ARM Ltd. Versatile family"
285 select HAVE_MACH_CLKDEV
287 select GENERIC_CLOCKEVENTS
288 select ARCH_WANT_OPTIONAL_GPIOLIB
289 select PLAT_VERSATILE
290 select PLAT_VERSATILE_CLCD
291 select PLAT_VERSATILE_FPGA_IRQ
292 select ARM_TIMER_SP804
294 This enables support for ARM Ltd Versatile board.
297 bool "ARM Ltd. Versatile Express family"
298 select ARCH_WANT_OPTIONAL_GPIOLIB
300 select ARM_TIMER_SP804
302 select HAVE_MACH_CLKDEV
303 select GENERIC_CLOCKEVENTS
305 select HAVE_PATA_PLATFORM
307 select PLAT_VERSATILE
308 select PLAT_VERSATILE_CLCD
310 This enables support for the ARM Ltd Versatile Express boards.
314 select ARCH_REQUIRE_GPIOLIB
318 This enables support for systems based on the Atmel AT91RM9200,
319 AT91SAM9 and AT91CAP9 processors.
322 bool "Broadcom BCMRING"
326 select ARM_TIMER_SP804
328 select GENERIC_CLOCKEVENTS
329 select ARCH_WANT_OPTIONAL_GPIOLIB
331 Support for Broadcom's BCMRing platform.
334 bool "Calxeda Highbank-based"
335 select ARCH_WANT_OPTIONAL_GPIOLIB
338 select ARM_TIMER_SP804
341 select GENERIC_CLOCKEVENTS
345 Support for the Calxeda Highbank SoC based boards.
348 bool "Cirrus Logic CLPS711x/EP721x-based"
350 select ARCH_USES_GETTIMEOFFSET
351 select NEED_MACH_MEMORY_H
353 Support for Cirrus Logic 711x/721x based boards.
356 bool "Cavium Networks CNS3XXX family"
358 select GENERIC_CLOCKEVENTS
360 select MIGHT_HAVE_PCI
361 select PCI_DOMAINS if PCI
363 Support for Cavium Networks CNS3XXX platform.
366 bool "Cortina Systems Gemini"
368 select ARCH_REQUIRE_GPIOLIB
369 select ARCH_USES_GETTIMEOFFSET
371 Support for the Cortina Systems Gemini family SoCs
374 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
378 select GENERIC_CLOCKEVENTS
380 select GENERIC_IRQ_CHIP
384 Support for CSR SiRFSoC ARM Cortex A9 Platform
391 select ARCH_USES_GETTIMEOFFSET
392 select NEED_MACH_MEMORY_H
394 This is an evaluation board for the StrongARM processor available
395 from Digital. It has limited hardware on-board, including an
396 Ethernet interface, two PCMCIA sockets, two serial ports and a
405 select ARCH_REQUIRE_GPIOLIB
406 select ARCH_HAS_HOLES_MEMORYMODEL
407 select ARCH_USES_GETTIMEOFFSET
410 This enables support for the Cirrus EP93xx series of CPUs.
412 config ARCH_FOOTBRIDGE
416 select GENERIC_CLOCKEVENTS
417 select NEED_MACH_MEMORY_H
419 Support for systems based on the DC21285 companion chip
420 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
423 bool "Freescale MXC/iMX-based"
424 select GENERIC_CLOCKEVENTS
425 select ARCH_REQUIRE_GPIOLIB
428 select GENERIC_IRQ_CHIP
429 select HAVE_SCHED_CLOCK
430 select MULTI_IRQ_HANDLER
432 Support for Freescale MXC/iMX-based family of processors
435 bool "Freescale MXS-based"
436 select GENERIC_CLOCKEVENTS
437 select ARCH_REQUIRE_GPIOLIB
441 Support for Freescale MXS-based family of processors
444 bool "Hilscher NetX based"
448 select GENERIC_CLOCKEVENTS
450 This enables support for systems based on the Hilscher NetX Soc
453 bool "Hynix HMS720x-based"
456 select ARCH_USES_GETTIMEOFFSET
458 This enables support for systems based on the Hynix HMS720x
466 select ARCH_SUPPORTS_MSI
468 select NEED_MACH_MEMORY_H
470 Support for Intel's IOP13XX (XScale) family of processors.
478 select ARCH_REQUIRE_GPIOLIB
480 Support for Intel's 80219 and IOP32X (XScale) family of
489 select ARCH_REQUIRE_GPIOLIB
491 Support for Intel's IOP33X (XScale) family of processors.
498 select ARCH_USES_GETTIMEOFFSET
499 select NEED_MACH_MEMORY_H
501 Support for Intel's IXP23xx (XScale) family of processors.
504 bool "IXP2400/2800-based"
508 select ARCH_USES_GETTIMEOFFSET
509 select NEED_MACH_MEMORY_H
511 Support for Intel's IXP2400/2800 (XScale) family of processors.
519 select GENERIC_CLOCKEVENTS
520 select HAVE_SCHED_CLOCK
521 select MIGHT_HAVE_PCI
522 select DMABOUNCE if PCI
524 Support for Intel's IXP4XX (XScale) family of processors.
530 select ARCH_REQUIRE_GPIOLIB
531 select GENERIC_CLOCKEVENTS
534 Support for the Marvell Dove SoC 88AP510
537 bool "Marvell Kirkwood"
540 select ARCH_REQUIRE_GPIOLIB
541 select GENERIC_CLOCKEVENTS
544 Support for the following Marvell Kirkwood series SoCs:
545 88F6180, 88F6192 and 88F6281.
551 select ARCH_REQUIRE_GPIOLIB
554 select USB_ARCH_HAS_OHCI
557 select GENERIC_CLOCKEVENTS
559 Support for the NXP LPC32XX family of processors
562 bool "Marvell MV78xx0"
565 select ARCH_REQUIRE_GPIOLIB
566 select GENERIC_CLOCKEVENTS
569 Support for the following Marvell MV78xx0 series SoCs:
577 select ARCH_REQUIRE_GPIOLIB
578 select GENERIC_CLOCKEVENTS
581 Support for the following Marvell Orion 5x series SoCs:
582 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
583 Orion-2 (5281), Orion-1-90 (6183).
586 bool "Marvell PXA168/910/MMP2"
588 select ARCH_REQUIRE_GPIOLIB
590 select GENERIC_CLOCKEVENTS
591 select HAVE_SCHED_CLOCK
596 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
599 bool "Micrel/Kendin KS8695"
601 select ARCH_REQUIRE_GPIOLIB
602 select ARCH_USES_GETTIMEOFFSET
603 select NEED_MACH_MEMORY_H
605 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
606 System-on-Chip devices.
609 bool "Nuvoton W90X900 CPU"
611 select ARCH_REQUIRE_GPIOLIB
614 select GENERIC_CLOCKEVENTS
616 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
617 At present, the w90x900 has been renamed nuc900, regarding
618 the ARM series product line, you can login the following
619 link address to know more.
621 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
622 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
625 bool "Nuvoton NUC93X CPU"
629 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
630 low-power and high performance MPEG-4/JPEG multimedia controller chip.
637 select GENERIC_CLOCKEVENTS
640 select HAVE_SCHED_CLOCK
641 select ARCH_HAS_CPUFREQ
643 This enables support for NVIDIA Tegra based systems (Tegra APX,
644 Tegra 6xx and Tegra 2 series).
646 config ARCH_PICOXCELL
647 bool "Picochip picoXcell"
648 select ARCH_REQUIRE_GPIOLIB
649 select ARM_PATCH_PHYS_VIRT
653 select GENERIC_CLOCKEVENTS
655 select HAVE_SCHED_CLOCK
660 This enables support for systems based on the Picochip picoXcell
661 family of Femtocell devices. The picoxcell support requires device tree
665 bool "Philips Nexperia PNX4008 Mobile"
668 select ARCH_USES_GETTIMEOFFSET
670 This enables support for Philips PNX4008 mobile platform.
673 bool "PXA2xx/PXA3xx-based"
676 select ARCH_HAS_CPUFREQ
679 select ARCH_REQUIRE_GPIOLIB
680 select GENERIC_CLOCKEVENTS
681 select HAVE_SCHED_CLOCK
686 select MULTI_IRQ_HANDLER
688 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
693 select GENERIC_CLOCKEVENTS
694 select ARCH_REQUIRE_GPIOLIB
697 Support for Qualcomm MSM/QSD based systems. This runs on the
698 apps processor of the MSM/QSD and depends on a shared memory
699 interface to the modem processor which runs the baseband
700 stack and controls some vital subsystems
701 (clock and power control, etc).
704 bool "Renesas SH-Mobile / R-Mobile"
707 select HAVE_MACH_CLKDEV
708 select GENERIC_CLOCKEVENTS
711 select MULTI_IRQ_HANDLER
712 select PM_GENERIC_DOMAINS if PM
713 select NEED_MACH_MEMORY_H
715 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
722 select ARCH_MAY_HAVE_PC_FDC
723 select HAVE_PATA_PLATFORM
726 select ARCH_SPARSEMEM_ENABLE
727 select ARCH_USES_GETTIMEOFFSET
728 select NEED_MACH_MEMORY_H
730 On the Acorn Risc-PC, Linux can support the internal IDE disk and
731 CD-ROM interface, serial and parallel port, and the floppy drive.
738 select ARCH_SPARSEMEM_ENABLE
740 select ARCH_HAS_CPUFREQ
742 select GENERIC_CLOCKEVENTS
744 select HAVE_SCHED_CLOCK
746 select ARCH_REQUIRE_GPIOLIB
747 select NEED_MACH_MEMORY_H
749 Support for StrongARM 11x0 based boards.
752 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
754 select ARCH_HAS_CPUFREQ
757 select ARCH_USES_GETTIMEOFFSET
758 select HAVE_S3C2410_I2C if I2C
760 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
761 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
762 the Samsung SMDK2410 development board (and derivatives).
764 Note, the S3C2416 and the S3C2450 are so close that they even share
765 the same SoC ID code. This means that there is no separate machine
766 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
769 bool "Samsung S3C64XX"
776 select ARCH_USES_GETTIMEOFFSET
777 select ARCH_HAS_CPUFREQ
778 select ARCH_REQUIRE_GPIOLIB
779 select SAMSUNG_CLKSRC
780 select SAMSUNG_IRQ_VIC_TIMER
781 select SAMSUNG_IRQ_UART
782 select S3C_GPIO_TRACK
783 select S3C_GPIO_PULL_UPDOWN
784 select S3C_GPIO_CFG_S3C24XX
785 select S3C_GPIO_CFG_S3C64XX
787 select USB_ARCH_HAS_OHCI
788 select SAMSUNG_GPIOLIB_4BIT
789 select HAVE_S3C2410_I2C if I2C
790 select HAVE_S3C2410_WATCHDOG if WATCHDOG
792 Samsung S3C64XX series based systems
795 bool "Samsung S5P6440 S5P6450"
801 select HAVE_S3C2410_WATCHDOG if WATCHDOG
802 select GENERIC_CLOCKEVENTS
803 select HAVE_SCHED_CLOCK
804 select HAVE_S3C2410_I2C if I2C
805 select HAVE_S3C_RTC if RTC_CLASS
807 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
811 bool "Samsung S5PC100"
816 select ARM_L1_CACHE_SHIFT_6
817 select ARCH_USES_GETTIMEOFFSET
818 select HAVE_S3C2410_I2C if I2C
819 select HAVE_S3C_RTC if RTC_CLASS
820 select HAVE_S3C2410_WATCHDOG if WATCHDOG
822 Samsung S5PC100 series based systems
825 bool "Samsung S5PV210/S5PC110"
827 select ARCH_SPARSEMEM_ENABLE
828 select ARCH_HAS_HOLES_MEMORYMODEL
833 select ARM_L1_CACHE_SHIFT_6
834 select ARCH_HAS_CPUFREQ
835 select GENERIC_CLOCKEVENTS
836 select HAVE_SCHED_CLOCK
837 select HAVE_S3C2410_I2C if I2C
838 select HAVE_S3C_RTC if RTC_CLASS
839 select HAVE_S3C2410_WATCHDOG if WATCHDOG
840 select NEED_MACH_MEMORY_H
842 Samsung S5PV210/S5PC110 series based systems
845 bool "Samsung EXYNOS4"
847 select ARCH_SPARSEMEM_ENABLE
848 select ARCH_HAS_HOLES_MEMORYMODEL
852 select ARCH_HAS_CPUFREQ
853 select GENERIC_CLOCKEVENTS
854 select HAVE_S3C_RTC if RTC_CLASS
855 select HAVE_S3C2410_I2C if I2C
856 select HAVE_S3C2410_WATCHDOG if WATCHDOG
857 select NEED_MACH_MEMORY_H
859 Samsung EXYNOS4 series based systems
868 select ARCH_USES_GETTIMEOFFSET
869 select NEED_MACH_MEMORY_H
871 Support for the StrongARM based Digital DNARD machine, also known
872 as "Shark" (<http://www.shark-linux.de/shark.html>).
875 bool "Telechips TCC ARM926-based systems"
880 select GENERIC_CLOCKEVENTS
882 Support for Telechips TCC ARM926-based systems.
885 bool "ST-Ericsson U300 Series"
889 select HAVE_SCHED_CLOCK
893 select GENERIC_CLOCKEVENTS
895 select HAVE_MACH_CLKDEV
897 select ARCH_REQUIRE_GPIOLIB
898 select NEED_MACH_MEMORY_H
900 Support for ST-Ericsson U300 series mobile platforms.
903 bool "ST-Ericsson U8500 Series"
906 select GENERIC_CLOCKEVENTS
908 select ARCH_REQUIRE_GPIOLIB
909 select ARCH_HAS_CPUFREQ
911 Support for ST-Ericsson's Ux500 architecture
914 bool "STMicroelectronics Nomadik"
919 select GENERIC_CLOCKEVENTS
920 select ARCH_REQUIRE_GPIOLIB
922 Support for the Nomadik platform by ST-Ericsson
926 select GENERIC_CLOCKEVENTS
927 select ARCH_REQUIRE_GPIOLIB
931 select GENERIC_ALLOCATOR
932 select GENERIC_IRQ_CHIP
933 select ARCH_HAS_HOLES_MEMORYMODEL
935 Support for TI's DaVinci platform.
940 select ARCH_REQUIRE_GPIOLIB
941 select ARCH_HAS_CPUFREQ
943 select GENERIC_CLOCKEVENTS
944 select HAVE_SCHED_CLOCK
945 select ARCH_HAS_HOLES_MEMORYMODEL
947 Support for TI's OMAP platform (OMAP1/2/3/4).
952 select ARCH_REQUIRE_GPIOLIB
955 select GENERIC_CLOCKEVENTS
958 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
961 bool "VIA/WonderMedia 85xx"
964 select ARCH_HAS_CPUFREQ
965 select GENERIC_CLOCKEVENTS
966 select ARCH_REQUIRE_GPIOLIB
969 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
972 bool "Xilinx Zynq ARM Cortex A9 Platform"
975 select GENERIC_CLOCKEVENTS
982 Support for Xilinx Zynq ARM Cortex A9 Platform
986 # This is sorted alphabetically by mach-* pathname. However, plat-*
987 # Kconfigs may be included either alphabetically (according to the
988 # plat- suffix) or along side the corresponding mach-* source.
990 source "arch/arm/mach-at91/Kconfig"
992 source "arch/arm/mach-bcmring/Kconfig"
994 source "arch/arm/mach-clps711x/Kconfig"
996 source "arch/arm/mach-cns3xxx/Kconfig"
998 source "arch/arm/mach-davinci/Kconfig"
1000 source "arch/arm/mach-dove/Kconfig"
1002 source "arch/arm/mach-ep93xx/Kconfig"
1004 source "arch/arm/mach-footbridge/Kconfig"
1006 source "arch/arm/mach-gemini/Kconfig"
1008 source "arch/arm/mach-h720x/Kconfig"
1010 source "arch/arm/mach-integrator/Kconfig"
1012 source "arch/arm/mach-iop32x/Kconfig"
1014 source "arch/arm/mach-iop33x/Kconfig"
1016 source "arch/arm/mach-iop13xx/Kconfig"
1018 source "arch/arm/mach-ixp4xx/Kconfig"
1020 source "arch/arm/mach-ixp2000/Kconfig"
1022 source "arch/arm/mach-ixp23xx/Kconfig"
1024 source "arch/arm/mach-kirkwood/Kconfig"
1026 source "arch/arm/mach-ks8695/Kconfig"
1028 source "arch/arm/mach-lpc32xx/Kconfig"
1030 source "arch/arm/mach-msm/Kconfig"
1032 source "arch/arm/mach-mv78xx0/Kconfig"
1034 source "arch/arm/plat-mxc/Kconfig"
1036 source "arch/arm/mach-mxs/Kconfig"
1038 source "arch/arm/mach-netx/Kconfig"
1040 source "arch/arm/mach-nomadik/Kconfig"
1041 source "arch/arm/plat-nomadik/Kconfig"
1043 source "arch/arm/mach-nuc93x/Kconfig"
1045 source "arch/arm/plat-omap/Kconfig"
1047 source "arch/arm/mach-omap1/Kconfig"
1049 source "arch/arm/mach-omap2/Kconfig"
1051 source "arch/arm/mach-orion5x/Kconfig"
1053 source "arch/arm/mach-pxa/Kconfig"
1054 source "arch/arm/plat-pxa/Kconfig"
1056 source "arch/arm/mach-mmp/Kconfig"
1058 source "arch/arm/mach-realview/Kconfig"
1060 source "arch/arm/mach-sa1100/Kconfig"
1062 source "arch/arm/plat-samsung/Kconfig"
1063 source "arch/arm/plat-s3c24xx/Kconfig"
1064 source "arch/arm/plat-s5p/Kconfig"
1066 source "arch/arm/plat-spear/Kconfig"
1068 source "arch/arm/plat-tcc/Kconfig"
1071 source "arch/arm/mach-s3c2410/Kconfig"
1072 source "arch/arm/mach-s3c2412/Kconfig"
1073 source "arch/arm/mach-s3c2416/Kconfig"
1074 source "arch/arm/mach-s3c2440/Kconfig"
1075 source "arch/arm/mach-s3c2443/Kconfig"
1079 source "arch/arm/mach-s3c64xx/Kconfig"
1082 source "arch/arm/mach-s5p64x0/Kconfig"
1084 source "arch/arm/mach-s5pc100/Kconfig"
1086 source "arch/arm/mach-s5pv210/Kconfig"
1088 source "arch/arm/mach-exynos4/Kconfig"
1090 source "arch/arm/mach-shmobile/Kconfig"
1092 source "arch/arm/mach-tegra/Kconfig"
1094 source "arch/arm/mach-u300/Kconfig"
1096 source "arch/arm/mach-ux500/Kconfig"
1098 source "arch/arm/mach-versatile/Kconfig"
1100 source "arch/arm/mach-vexpress/Kconfig"
1101 source "arch/arm/plat-versatile/Kconfig"
1103 source "arch/arm/mach-vt8500/Kconfig"
1105 source "arch/arm/mach-w90x900/Kconfig"
1107 # Definitions to make life easier
1113 select GENERIC_CLOCKEVENTS
1114 select HAVE_SCHED_CLOCK
1119 select GENERIC_IRQ_CHIP
1120 select HAVE_SCHED_CLOCK
1125 config PLAT_VERSATILE
1128 config ARM_TIMER_SP804
1132 source arch/arm/mm/Kconfig
1135 bool "Enable iWMMXt support"
1136 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1137 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1139 Enable support for iWMMXt context switching at run time if
1140 running on a CPU that supports it.
1142 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1145 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1149 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1150 (!ARCH_OMAP3 || OMAP3_EMU)
1154 config MULTI_IRQ_HANDLER
1157 Allow each machine to specify it's own IRQ handler at run time.
1160 source "arch/arm/Kconfig-nommu"
1163 config ARM_ERRATA_411920
1164 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1165 depends on CPU_V6 || CPU_V6K
1167 Invalidation of the Instruction Cache operation can
1168 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1169 It does not affect the MPCore. This option enables the ARM Ltd.
1170 recommended workaround.
1172 config ARM_ERRATA_430973
1173 bool "ARM errata: Stale prediction on replaced interworking branch"
1176 This option enables the workaround for the 430973 Cortex-A8
1177 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1178 interworking branch is replaced with another code sequence at the
1179 same virtual address, whether due to self-modifying code or virtual
1180 to physical address re-mapping, Cortex-A8 does not recover from the
1181 stale interworking branch prediction. This results in Cortex-A8
1182 executing the new code sequence in the incorrect ARM or Thumb state.
1183 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1184 and also flushes the branch target cache at every context switch.
1185 Note that setting specific bits in the ACTLR register may not be
1186 available in non-secure mode.
1188 config ARM_ERRATA_458693
1189 bool "ARM errata: Processor deadlock when a false hazard is created"
1192 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1193 erratum. For very specific sequences of memory operations, it is
1194 possible for a hazard condition intended for a cache line to instead
1195 be incorrectly associated with a different cache line. This false
1196 hazard might then cause a processor deadlock. The workaround enables
1197 the L1 caching of the NEON accesses and disables the PLD instruction
1198 in the ACTLR register. Note that setting specific bits in the ACTLR
1199 register may not be available in non-secure mode.
1201 config ARM_ERRATA_460075
1202 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1205 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1206 erratum. Any asynchronous access to the L2 cache may encounter a
1207 situation in which recent store transactions to the L2 cache are lost
1208 and overwritten with stale memory contents from external memory. The
1209 workaround disables the write-allocate mode for the L2 cache via the
1210 ACTLR register. Note that setting specific bits in the ACTLR register
1211 may not be available in non-secure mode.
1213 config ARM_ERRATA_742230
1214 bool "ARM errata: DMB operation may be faulty"
1215 depends on CPU_V7 && SMP
1217 This option enables the workaround for the 742230 Cortex-A9
1218 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1219 between two write operations may not ensure the correct visibility
1220 ordering of the two writes. This workaround sets a specific bit in
1221 the diagnostic register of the Cortex-A9 which causes the DMB
1222 instruction to behave as a DSB, ensuring the correct behaviour of
1225 config ARM_ERRATA_742231
1226 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1227 depends on CPU_V7 && SMP
1229 This option enables the workaround for the 742231 Cortex-A9
1230 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1231 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1232 accessing some data located in the same cache line, may get corrupted
1233 data due to bad handling of the address hazard when the line gets
1234 replaced from one of the CPUs at the same time as another CPU is
1235 accessing it. This workaround sets specific bits in the diagnostic
1236 register of the Cortex-A9 which reduces the linefill issuing
1237 capabilities of the processor.
1239 config PL310_ERRATA_588369
1240 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1241 depends on CACHE_L2X0
1243 The PL310 L2 cache controller implements three types of Clean &
1244 Invalidate maintenance operations: by Physical Address
1245 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1246 They are architecturally defined to behave as the execution of a
1247 clean operation followed immediately by an invalidate operation,
1248 both performing to the same memory location. This functionality
1249 is not correctly implemented in PL310 as clean lines are not
1250 invalidated as a result of these operations.
1252 config ARM_ERRATA_720789
1253 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1254 depends on CPU_V7 && SMP
1256 This option enables the workaround for the 720789 Cortex-A9 (prior to
1257 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1258 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1259 As a consequence of this erratum, some TLB entries which should be
1260 invalidated are not, resulting in an incoherency in the system page
1261 tables. The workaround changes the TLB flushing routines to invalidate
1262 entries regardless of the ASID.
1264 config PL310_ERRATA_727915
1265 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1266 depends on CACHE_L2X0
1268 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1269 operation (offset 0x7FC). This operation runs in background so that
1270 PL310 can handle normal accesses while it is in progress. Under very
1271 rare circumstances, due to this erratum, write data can be lost when
1272 PL310 treats a cacheable write transaction during a Clean &
1273 Invalidate by Way operation.
1275 config ARM_ERRATA_743622
1276 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1279 This option enables the workaround for the 743622 Cortex-A9
1280 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1281 optimisation in the Cortex-A9 Store Buffer may lead to data
1282 corruption. This workaround sets a specific bit in the diagnostic
1283 register of the Cortex-A9 which disables the Store Buffer
1284 optimisation, preventing the defect from occurring. This has no
1285 visible impact on the overall performance or power consumption of the
1288 config ARM_ERRATA_751472
1289 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1290 depends on CPU_V7 && SMP
1292 This option enables the workaround for the 751472 Cortex-A9 (prior
1293 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1294 completion of a following broadcasted operation if the second
1295 operation is received by a CPU before the ICIALLUIS has completed,
1296 potentially leading to corrupted entries in the cache or TLB.
1298 config ARM_ERRATA_753970
1299 bool "ARM errata: cache sync operation may be faulty"
1300 depends on CACHE_PL310
1302 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1304 Under some condition the effect of cache sync operation on
1305 the store buffer still remains when the operation completes.
1306 This means that the store buffer is always asked to drain and
1307 this prevents it from merging any further writes. The workaround
1308 is to replace the normal offset of cache sync operation (0x730)
1309 by another offset targeting an unmapped PL310 register 0x740.
1310 This has the same effect as the cache sync operation: store buffer
1311 drain and waiting for all buffers empty.
1313 config ARM_ERRATA_754322
1314 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1317 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1318 r3p*) erratum. A speculative memory access may cause a page table walk
1319 which starts prior to an ASID switch but completes afterwards. This
1320 can populate the micro-TLB with a stale entry which may be hit with
1321 the new ASID. This workaround places two dsb instructions in the mm
1322 switching code so that no page table walks can cross the ASID switch.
1324 config ARM_ERRATA_754327
1325 bool "ARM errata: no automatic Store Buffer drain"
1326 depends on CPU_V7 && SMP
1328 This option enables the workaround for the 754327 Cortex-A9 (prior to
1329 r2p0) erratum. The Store Buffer does not have any automatic draining
1330 mechanism and therefore a livelock may occur if an external agent
1331 continuously polls a memory location waiting to observe an update.
1332 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1333 written polling loops from denying visibility of updates to memory.
1335 config ARM_ERRATA_364296
1336 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1337 depends on CPU_V6 && !SMP
1339 This options enables the workaround for the 364296 ARM1136
1340 r0p2 erratum (possible cache data corruption with
1341 hit-under-miss enabled). It sets the undocumented bit 31 in
1342 the auxiliary control register and the FI bit in the control
1343 register, thus disabling hit-under-miss without putting the
1344 processor into full low interrupt latency mode. ARM11MPCore
1347 config ARM_ERRATA_764369
1348 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1349 depends on CPU_V7 && SMP
1351 This option enables the workaround for erratum 764369
1352 affecting Cortex-A9 MPCore with two or more processors (all
1353 current revisions). Under certain timing circumstances, a data
1354 cache line maintenance operation by MVA targeting an Inner
1355 Shareable memory region may fail to proceed up to either the
1356 Point of Coherency or to the Point of Unification of the
1357 system. This workaround adds a DSB instruction before the
1358 relevant cache maintenance functions and sets a specific bit
1359 in the diagnostic control register of the SCU.
1363 source "arch/arm/common/Kconfig"
1373 Find out whether you have ISA slots on your motherboard. ISA is the
1374 name of a bus system, i.e. the way the CPU talks to the other stuff
1375 inside your box. Other bus systems are PCI, EISA, MicroChannel
1376 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1377 newer boards don't support it. If you have ISA, say Y, otherwise N.
1379 # Select ISA DMA controller support
1384 # Select ISA DMA interface
1389 bool "PCI support" if MIGHT_HAVE_PCI
1391 Find out whether you have a PCI motherboard. PCI is the name of a
1392 bus system, i.e. the way the CPU talks to the other stuff inside
1393 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1394 VESA. If you have PCI, say Y, otherwise N.
1400 config PCI_NANOENGINE
1401 bool "BSE nanoEngine PCI support"
1402 depends on SA1100_NANOENGINE
1404 Enable PCI on the BSE nanoEngine board.
1409 # Select the host bridge type
1410 config PCI_HOST_VIA82C505
1412 depends on PCI && ARCH_SHARK
1415 config PCI_HOST_ITE8152
1417 depends on PCI && MACH_ARMCORE
1421 source "drivers/pci/Kconfig"
1423 source "drivers/pcmcia/Kconfig"
1427 menu "Kernel Features"
1429 source "kernel/time/Kconfig"
1432 bool "Symmetric Multi-Processing"
1433 depends on CPU_V6K || CPU_V7
1434 depends on GENERIC_CLOCKEVENTS
1435 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1436 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1437 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1438 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE || ARCH_HIGHBANK
1439 select USE_GENERIC_SMP_HELPERS
1440 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1442 This enables support for systems with more than one CPU. If you have
1443 a system with only one CPU, like most personal computers, say N. If
1444 you have a system with more than one CPU, say Y.
1446 If you say N here, the kernel will run on single and multiprocessor
1447 machines, but will use only one CPU of a multiprocessor machine. If
1448 you say Y here, the kernel will run on many, but not all, single
1449 processor machines. On a single processor machine, the kernel will
1450 run faster if you say N here.
1452 See also <file:Documentation/i386/IO-APIC.txt>,
1453 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1454 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1456 If you don't know what to do here, say N.
1459 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1460 depends on EXPERIMENTAL
1461 depends on SMP && !XIP_KERNEL
1464 SMP kernels contain instructions which fail on non-SMP processors.
1465 Enabling this option allows the kernel to modify itself to make
1466 these instructions safe. Disabling it allows about 1K of space
1469 If you don't know what to do here, say Y.
1471 config ARM_CPU_TOPOLOGY
1472 bool "Support cpu topology definition"
1473 depends on SMP && CPU_V7
1476 Support ARM cpu topology definition. The MPIDR register defines
1477 affinity between processors which is then used to describe the cpu
1478 topology of an ARM System.
1481 bool "Multi-core scheduler support"
1482 depends on ARM_CPU_TOPOLOGY
1484 Multi-core scheduler support improves the CPU scheduler's decision
1485 making when dealing with multi-core CPU chips at a cost of slightly
1486 increased overhead in some places. If unsure say N here.
1489 bool "SMT scheduler support"
1490 depends on ARM_CPU_TOPOLOGY
1492 Improves the CPU scheduler's decision making when dealing with
1493 MultiThreading at a cost of slightly increased overhead in some
1494 places. If unsure say N here.
1499 This option enables support for the ARM system coherency unit
1506 This options enables support for the ARM timer and watchdog unit
1509 prompt "Memory split"
1512 Select the desired split between kernel and user memory.
1514 If you are not absolutely sure what you are doing, leave this
1518 bool "3G/1G user/kernel split"
1520 bool "2G/2G user/kernel split"
1522 bool "1G/3G user/kernel split"
1527 default 0x40000000 if VMSPLIT_1G
1528 default 0x80000000 if VMSPLIT_2G
1532 int "Maximum number of CPUs (2-32)"
1538 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1539 depends on SMP && HOTPLUG && EXPERIMENTAL
1541 Say Y here to experiment with turning CPUs off and on. CPUs
1542 can be controlled through /sys/devices/system/cpu.
1545 bool "Use local timer interrupts"
1548 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1550 Enable support for local timers on SMP platforms, rather then the
1551 legacy IPI broadcast method. Local timers allows the system
1552 accounting to be spread across the timer interval, preventing a
1553 "thundering herd" at every timer tick.
1555 source kernel/Kconfig.preempt
1559 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1560 ARCH_S5PV210 || ARCH_EXYNOS4
1561 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1562 default AT91_TIMER_HZ if ARCH_AT91
1563 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1566 config THUMB2_KERNEL
1567 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1568 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1570 select ARM_ASM_UNIFIED
1572 By enabling this option, the kernel will be compiled in
1573 Thumb-2 mode. A compiler/assembler that understand the unified
1574 ARM-Thumb syntax is needed.
1578 config THUMB2_AVOID_R_ARM_THM_JUMP11
1579 bool "Work around buggy Thumb-2 short branch relocations in gas"
1580 depends on THUMB2_KERNEL && MODULES
1583 Various binutils versions can resolve Thumb-2 branches to
1584 locally-defined, preemptible global symbols as short-range "b.n"
1585 branch instructions.
1587 This is a problem, because there's no guarantee the final
1588 destination of the symbol, or any candidate locations for a
1589 trampoline, are within range of the branch. For this reason, the
1590 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1591 relocation in modules at all, and it makes little sense to add
1594 The symptom is that the kernel fails with an "unsupported
1595 relocation" error when loading some modules.
1597 Until fixed tools are available, passing
1598 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1599 code which hits this problem, at the cost of a bit of extra runtime
1600 stack usage in some cases.
1602 The problem is described in more detail at:
1603 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1605 Only Thumb-2 kernels are affected.
1607 Unless you are sure your tools don't have this problem, say Y.
1609 config ARM_ASM_UNIFIED
1613 bool "Use the ARM EABI to compile the kernel"
1615 This option allows for the kernel to be compiled using the latest
1616 ARM ABI (aka EABI). This is only useful if you are using a user
1617 space environment that is also compiled with EABI.
1619 Since there are major incompatibilities between the legacy ABI and
1620 EABI, especially with regard to structure member alignment, this
1621 option also changes the kernel syscall calling convention to
1622 disambiguate both ABIs and allow for backward compatibility support
1623 (selected with CONFIG_OABI_COMPAT).
1625 To use this you need GCC version 4.0.0 or later.
1628 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1629 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1632 This option preserves the old syscall interface along with the
1633 new (ARM EABI) one. It also provides a compatibility layer to
1634 intercept syscalls that have structure arguments which layout
1635 in memory differs between the legacy ABI and the new ARM EABI
1636 (only for non "thumb" binaries). This option adds a tiny
1637 overhead to all syscalls and produces a slightly larger kernel.
1638 If you know you'll be using only pure EABI user space then you
1639 can say N here. If this option is not selected and you attempt
1640 to execute a legacy ABI binary then the result will be
1641 UNPREDICTABLE (in fact it can be predicted that it won't work
1642 at all). If in doubt say Y.
1644 config ARCH_HAS_HOLES_MEMORYMODEL
1647 config ARCH_SPARSEMEM_ENABLE
1650 config ARCH_SPARSEMEM_DEFAULT
1651 def_bool ARCH_SPARSEMEM_ENABLE
1653 config ARCH_SELECT_MEMORY_MODEL
1654 def_bool ARCH_SPARSEMEM_ENABLE
1656 config HAVE_ARCH_PFN_VALID
1657 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1660 bool "High Memory Support"
1663 The address space of ARM processors is only 4 Gigabytes large
1664 and it has to accommodate user address space, kernel address
1665 space as well as some memory mapped IO. That means that, if you
1666 have a large amount of physical memory and/or IO, not all of the
1667 memory can be "permanently mapped" by the kernel. The physical
1668 memory that is not permanently mapped is called "high memory".
1670 Depending on the selected kernel/user memory split, minimum
1671 vmalloc space and actual amount of RAM, you may not need this
1672 option which should result in a slightly faster kernel.
1677 bool "Allocate 2nd-level pagetables from highmem"
1680 config HW_PERF_EVENTS
1681 bool "Enable hardware performance counter support for perf events"
1682 depends on PERF_EVENTS && CPU_HAS_PMU
1685 Enable hardware performance counter support for perf events. If
1686 disabled, perf events will use software events only.
1690 config FORCE_MAX_ZONEORDER
1691 int "Maximum zone order" if ARCH_SHMOBILE
1692 range 11 64 if ARCH_SHMOBILE
1693 default "9" if SA1111
1696 The kernel memory allocator divides physically contiguous memory
1697 blocks into "zones", where each zone is a power of two number of
1698 pages. This option selects the largest power of two that the kernel
1699 keeps in the memory allocator. If you need to allocate very large
1700 blocks of physically contiguous memory, then you may need to
1701 increase this value.
1703 This config option is actually maximum order plus one. For example,
1704 a value of 11 means that the largest free memory block is 2^10 pages.
1707 bool "Timer and CPU usage LEDs"
1708 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1709 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1710 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1711 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1712 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1713 ARCH_AT91 || ARCH_DAVINCI || \
1714 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1716 If you say Y here, the LEDs on your machine will be used
1717 to provide useful information about your current system status.
1719 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1720 be able to select which LEDs are active using the options below. If
1721 you are compiling a kernel for the EBSA-110 or the LART however, the
1722 red LED will simply flash regularly to indicate that the system is
1723 still functional. It is safe to say Y here if you have a CATS
1724 system, but the driver will do nothing.
1727 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1728 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1729 || MACH_OMAP_PERSEUS2
1731 depends on !GENERIC_CLOCKEVENTS
1732 default y if ARCH_EBSA110
1734 If you say Y here, one of the system LEDs (the green one on the
1735 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1736 will flash regularly to indicate that the system is still
1737 operational. This is mainly useful to kernel hackers who are
1738 debugging unstable kernels.
1740 The LART uses the same LED for both Timer LED and CPU usage LED
1741 functions. You may choose to use both, but the Timer LED function
1742 will overrule the CPU usage LED.
1745 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1747 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1748 || MACH_OMAP_PERSEUS2
1751 If you say Y here, the red LED will be used to give a good real
1752 time indication of CPU usage, by lighting whenever the idle task
1753 is not currently executing.
1755 The LART uses the same LED for both Timer LED and CPU usage LED
1756 functions. You may choose to use both, but the Timer LED function
1757 will overrule the CPU usage LED.
1759 config ALIGNMENT_TRAP
1761 depends on CPU_CP15_MMU
1762 default y if !ARCH_EBSA110
1763 select HAVE_PROC_CPU if PROC_FS
1765 ARM processors cannot fetch/store information which is not
1766 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1767 address divisible by 4. On 32-bit ARM processors, these non-aligned
1768 fetch/store instructions will be emulated in software if you say
1769 here, which has a severe performance impact. This is necessary for
1770 correct operation of some network protocols. With an IP-only
1771 configuration it is safe to say N, otherwise say Y.
1773 config UACCESS_WITH_MEMCPY
1774 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1775 depends on MMU && EXPERIMENTAL
1776 default y if CPU_FEROCEON
1778 Implement faster copy_to_user and clear_user methods for CPU
1779 cores where a 8-word STM instruction give significantly higher
1780 memory write throughput than a sequence of individual 32bit stores.
1782 A possible side effect is a slight increase in scheduling latency
1783 between threads sharing the same address space if they invoke
1784 such copy operations with large buffers.
1786 However, if the CPU data cache is using a write-allocate mode,
1787 this option is unlikely to provide any performance gain.
1791 prompt "Enable seccomp to safely compute untrusted bytecode"
1793 This kernel feature is useful for number crunching applications
1794 that may need to compute untrusted bytecode during their
1795 execution. By using pipes or other transports made available to
1796 the process as file descriptors supporting the read/write
1797 syscalls, it's possible to isolate those applications in
1798 their own address space using seccomp. Once seccomp is
1799 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1800 and the task is only allowed to execute a few safe syscalls
1801 defined by each seccomp mode.
1803 config CC_STACKPROTECTOR
1804 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1805 depends on EXPERIMENTAL
1807 This option turns on the -fstack-protector GCC feature. This
1808 feature puts, at the beginning of functions, a canary value on
1809 the stack just before the return address, and validates
1810 the value just before actually returning. Stack based buffer
1811 overflows (that need to overwrite this return address) now also
1812 overwrite the canary, which gets detected and the attack is then
1813 neutralized via a kernel panic.
1814 This feature requires gcc version 4.2 or above.
1816 config DEPRECATED_PARAM_STRUCT
1817 bool "Provide old way to pass kernel parameters"
1819 This was deprecated in 2001 and announced to live on for 5 years.
1820 Some old boot loaders still use this way.
1827 bool "Flattened Device Tree support"
1829 select OF_EARLY_FLATTREE
1832 Include support for flattened device tree machine descriptions.
1834 # Compressed boot loader in ROM. Yes, we really want to ask about
1835 # TEXT and BSS so we preserve their values in the config files.
1836 config ZBOOT_ROM_TEXT
1837 hex "Compressed ROM boot loader base address"
1840 The physical address at which the ROM-able zImage is to be
1841 placed in the target. Platforms which normally make use of
1842 ROM-able zImage formats normally set this to a suitable
1843 value in their defconfig file.
1845 If ZBOOT_ROM is not enabled, this has no effect.
1847 config ZBOOT_ROM_BSS
1848 hex "Compressed ROM boot loader BSS address"
1851 The base address of an area of read/write memory in the target
1852 for the ROM-able zImage which must be available while the
1853 decompressor is running. It must be large enough to hold the
1854 entire decompressed kernel plus an additional 128 KiB.
1855 Platforms which normally make use of ROM-able zImage formats
1856 normally set this to a suitable value in their defconfig file.
1858 If ZBOOT_ROM is not enabled, this has no effect.
1861 bool "Compressed boot loader in ROM/flash"
1862 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1864 Say Y here if you intend to execute your compressed kernel image
1865 (zImage) directly from ROM or flash. If unsure, say N.
1868 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1869 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1870 default ZBOOT_ROM_NONE
1872 Include experimental SD/MMC loading code in the ROM-able zImage.
1873 With this enabled it is possible to write the the ROM-able zImage
1874 kernel image to an MMC or SD card and boot the kernel straight
1875 from the reset vector. At reset the processor Mask ROM will load
1876 the first part of the the ROM-able zImage which in turn loads the
1877 rest the kernel image to RAM.
1879 config ZBOOT_ROM_NONE
1880 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1882 Do not load image from SD or MMC
1884 config ZBOOT_ROM_MMCIF
1885 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1887 Load image from MMCIF hardware block.
1889 config ZBOOT_ROM_SH_MOBILE_SDHI
1890 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1892 Load image from SDHI hardware block
1896 config ARM_APPENDED_DTB
1897 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1898 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1900 With this option, the boot code will look for a device tree binary
1901 (DTB) appended to zImage
1902 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1904 This is meant as a backward compatibility convenience for those
1905 systems with a bootloader that can't be upgraded to accommodate
1906 the documented boot protocol using a device tree.
1908 Beware that there is very little in terms of protection against
1909 this option being confused by leftover garbage in memory that might
1910 look like a DTB header after a reboot if no actual DTB is appended
1911 to zImage. Do not leave this option active in a production kernel
1912 if you don't intend to always append a DTB. Proper passing of the
1913 location into r2 of a bootloader provided DTB is always preferable
1916 config ARM_ATAG_DTB_COMPAT
1917 bool "Supplement the appended DTB with traditional ATAG information"
1918 depends on ARM_APPENDED_DTB
1920 Some old bootloaders can't be updated to a DTB capable one, yet
1921 they provide ATAGs with memory configuration, the ramdisk address,
1922 the kernel cmdline string, etc. Such information is dynamically
1923 provided by the bootloader and can't always be stored in a static
1924 DTB. To allow a device tree enabled kernel to be used with such
1925 bootloaders, this option allows zImage to extract the information
1926 from the ATAG list and store it at run time into the appended DTB.
1929 string "Default kernel command string"
1932 On some architectures (EBSA110 and CATS), there is currently no way
1933 for the boot loader to pass arguments to the kernel. For these
1934 architectures, you should supply some command-line options at build
1935 time by entering them here. As a minimum, you should specify the
1936 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1939 prompt "Kernel command line type" if CMDLINE != ""
1940 default CMDLINE_FROM_BOOTLOADER
1942 config CMDLINE_FROM_BOOTLOADER
1943 bool "Use bootloader kernel arguments if available"
1945 Uses the command-line options passed by the boot loader. If
1946 the boot loader doesn't provide any, the default kernel command
1947 string provided in CMDLINE will be used.
1949 config CMDLINE_EXTEND
1950 bool "Extend bootloader kernel arguments"
1952 The command-line arguments provided by the boot loader will be
1953 appended to the default kernel command string.
1955 config CMDLINE_FORCE
1956 bool "Always use the default kernel command string"
1958 Always use the default kernel command string, even if the boot
1959 loader passes other arguments to the kernel.
1960 This is useful if you cannot or don't want to change the
1961 command-line options your boot loader passes to the kernel.
1965 bool "Kernel Execute-In-Place from ROM"
1966 depends on !ZBOOT_ROM
1968 Execute-In-Place allows the kernel to run from non-volatile storage
1969 directly addressable by the CPU, such as NOR flash. This saves RAM
1970 space since the text section of the kernel is not loaded from flash
1971 to RAM. Read-write sections, such as the data section and stack,
1972 are still copied to RAM. The XIP kernel is not compressed since
1973 it has to run directly from flash, so it will take more space to
1974 store it. The flash address used to link the kernel object files,
1975 and for storing it, is configuration dependent. Therefore, if you
1976 say Y here, you must know the proper physical address where to
1977 store the kernel image depending on your own flash memory usage.
1979 Also note that the make target becomes "make xipImage" rather than
1980 "make zImage" or "make Image". The final kernel binary to put in
1981 ROM memory will be arch/arm/boot/xipImage.
1985 config XIP_PHYS_ADDR
1986 hex "XIP Kernel Physical Location"
1987 depends on XIP_KERNEL
1988 default "0x00080000"
1990 This is the physical address in your flash memory the kernel will
1991 be linked for and stored to. This address is dependent on your
1995 bool "Kexec system call (EXPERIMENTAL)"
1996 depends on EXPERIMENTAL
1998 kexec is a system call that implements the ability to shutdown your
1999 current kernel, and to start another kernel. It is like a reboot
2000 but it is independent of the system firmware. And like a reboot
2001 you can start any kernel with it, not just Linux.
2003 It is an ongoing process to be certain the hardware in a machine
2004 is properly shutdown, so do not be surprised if this code does not
2005 initially work for you. It may help to enable device hotplugging
2009 bool "Export atags in procfs"
2013 Should the atags used to boot the kernel be exported in an "atags"
2014 file in procfs. Useful with kexec.
2017 bool "Build kdump crash kernel (EXPERIMENTAL)"
2018 depends on EXPERIMENTAL
2020 Generate crash dump after being started by kexec. This should
2021 be normally only set in special crash dump kernels which are
2022 loaded in the main kernel with kexec-tools into a specially
2023 reserved region and then later executed after a crash by
2024 kdump/kexec. The crash dump kernel must be compiled to a
2025 memory address not used by the main kernel
2027 For more details see Documentation/kdump/kdump.txt
2029 config AUTO_ZRELADDR
2030 bool "Auto calculation of the decompressed kernel image address"
2031 depends on !ZBOOT_ROM && !ARCH_U300
2033 ZRELADDR is the physical address where the decompressed kernel
2034 image will be placed. If AUTO_ZRELADDR is selected, the address
2035 will be determined at run-time by masking the current IP with
2036 0xf8000000. This assumes the zImage being placed in the first 128MB
2037 from start of memory.
2041 menu "CPU Power Management"
2045 source "drivers/cpufreq/Kconfig"
2048 tristate "CPUfreq driver for i.MX CPUs"
2049 depends on ARCH_MXC && CPU_FREQ
2051 This enables the CPUfreq driver for i.MX CPUs.
2053 config CPU_FREQ_SA1100
2056 config CPU_FREQ_SA1110
2059 config CPU_FREQ_INTEGRATOR
2060 tristate "CPUfreq driver for ARM Integrator CPUs"
2061 depends on ARCH_INTEGRATOR && CPU_FREQ
2064 This enables the CPUfreq driver for ARM Integrator CPUs.
2066 For details, take a look at <file:Documentation/cpu-freq>.
2072 depends on CPU_FREQ && ARCH_PXA && PXA25x
2074 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2079 Internal configuration node for common cpufreq on Samsung SoC
2081 config CPU_FREQ_S3C24XX
2082 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2083 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
2086 This enables the CPUfreq driver for the Samsung S3C24XX family
2089 For details, take a look at <file:Documentation/cpu-freq>.
2093 config CPU_FREQ_S3C24XX_PLL
2094 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2095 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2097 Compile in support for changing the PLL frequency from the
2098 S3C24XX series CPUfreq driver. The PLL takes time to settle
2099 after a frequency change, so by default it is not enabled.
2101 This also means that the PLL tables for the selected CPU(s) will
2102 be built which may increase the size of the kernel image.
2104 config CPU_FREQ_S3C24XX_DEBUG
2105 bool "Debug CPUfreq Samsung driver core"
2106 depends on CPU_FREQ_S3C24XX
2108 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2110 config CPU_FREQ_S3C24XX_IODEBUG
2111 bool "Debug CPUfreq Samsung driver IO timing"
2112 depends on CPU_FREQ_S3C24XX
2114 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2116 config CPU_FREQ_S3C24XX_DEBUGFS
2117 bool "Export debugfs for CPUFreq"
2118 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2120 Export status information via debugfs.
2124 source "drivers/cpuidle/Kconfig"
2128 menu "Floating point emulation"
2130 comment "At least one emulation must be selected"
2133 bool "NWFPE math emulation"
2134 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2136 Say Y to include the NWFPE floating point emulator in the kernel.
2137 This is necessary to run most binaries. Linux does not currently
2138 support floating point hardware so you need to say Y here even if
2139 your machine has an FPA or floating point co-processor podule.
2141 You may say N here if you are going to load the Acorn FPEmulator
2142 early in the bootup.
2145 bool "Support extended precision"
2146 depends on FPE_NWFPE
2148 Say Y to include 80-bit support in the kernel floating-point
2149 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2150 Note that gcc does not generate 80-bit operations by default,
2151 so in most cases this option only enlarges the size of the
2152 floating point emulator without any good reason.
2154 You almost surely want to say N here.
2157 bool "FastFPE math emulation (EXPERIMENTAL)"
2158 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2160 Say Y here to include the FAST floating point emulator in the kernel.
2161 This is an experimental much faster emulator which now also has full
2162 precision for the mantissa. It does not support any exceptions.
2163 It is very simple, and approximately 3-6 times faster than NWFPE.
2165 It should be sufficient for most programs. It may be not suitable
2166 for scientific calculations, but you have to check this for yourself.
2167 If you do not feel you need a faster FP emulation you should better
2171 bool "VFP-format floating point maths"
2172 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2174 Say Y to include VFP support code in the kernel. This is needed
2175 if your hardware includes a VFP unit.
2177 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2178 release notes and additional status information.
2180 Say N if your target does not have VFP hardware.
2188 bool "Advanced SIMD (NEON) Extension support"
2189 depends on VFPv3 && CPU_V7
2191 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2196 menu "Userspace binary formats"
2198 source "fs/Kconfig.binfmt"
2201 tristate "RISC OS personality"
2204 Say Y here to include the kernel code necessary if you want to run
2205 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2206 experimental; if this sounds frightening, say N and sleep in peace.
2207 You can also say M here to compile this support as a module (which
2208 will be called arthur).
2212 menu "Power management options"
2214 source "kernel/power/Kconfig"
2216 config ARCH_SUSPEND_POSSIBLE
2217 depends on !ARCH_S5P64X0 && !ARCH_S5PC100
2218 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2219 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2224 source "net/Kconfig"
2226 source "drivers/Kconfig"
2230 source "arch/arm/Kconfig.debug"
2232 source "security/Kconfig"
2234 source "crypto/Kconfig"
2236 source "lib/Kconfig"