5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if !XIP_KERNEL
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
33 The ARM series is a line of low-power-consumption RISC chip designs
34 licensed by ARM Ltd and targeted at embedded applications and
35 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
36 manufactured, but legacy ARM-based PC hardware remains popular in
37 Europe. There is an ARM Linux project with a web page at
38 <http://www.arm.linux.org.uk/>.
40 config ARM_HAS_SG_CHAIN
49 config SYS_SUPPORTS_APM_EMULATION
52 config HAVE_SCHED_CLOCK
58 config ARCH_USES_GETTIMEOFFSET
62 config GENERIC_CLOCKEVENTS
65 config GENERIC_CLOCKEVENTS_BROADCAST
67 depends on GENERIC_CLOCKEVENTS
76 select GENERIC_ALLOCATOR
87 The Extended Industry Standard Architecture (EISA) bus was
88 developed as an open alternative to the IBM MicroChannel bus.
90 The EISA bus provided some of the features of the IBM MicroChannel
91 bus while maintaining backward compatibility with cards made for
92 the older ISA bus. The EISA bus saw limited use between 1988 and
93 1995 when it was made obsolete by the PCI bus.
95 Say Y here if you are building a kernel for an EISA-based machine.
105 MicroChannel Architecture is found in some IBM PS/2 machines and
106 laptops. It is a bus system similar to PCI or ISA. See
107 <file:Documentation/mca.txt> (and especially the web page given
108 there) before attempting to build an MCA bus kernel.
110 config STACKTRACE_SUPPORT
114 config HAVE_LATENCYTOP_SUPPORT
119 config LOCKDEP_SUPPORT
123 config TRACE_IRQFLAGS_SUPPORT
127 config HARDIRQS_SW_RESEND
131 config GENERIC_IRQ_PROBE
135 config GENERIC_LOCKBREAK
138 depends on SMP && PREEMPT
140 config RWSEM_GENERIC_SPINLOCK
144 config RWSEM_XCHGADD_ALGORITHM
147 config ARCH_HAS_ILOG2_U32
150 config ARCH_HAS_ILOG2_U64
153 config ARCH_HAS_CPUFREQ
156 Internal node to signify that the ARCH has CPUFREQ support
157 and that the relevant menu configurations are displayed for
160 config ARCH_HAS_CPU_IDLE_WAIT
163 config GENERIC_HWEIGHT
167 config GENERIC_CALIBRATE_DELAY
171 config ARCH_MAY_HAVE_PC_FDC
177 config NEED_DMA_MAP_STATE
180 config GENERIC_ISA_DMA
191 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
192 default DRAM_BASE if REMAP_VECTORS_TO_RAM
195 The base address of exception vectors.
197 config ARM_PATCH_PHYS_VIRT
198 bool "Patch physical to virtual translations at runtime (EXPERIMENTAL)"
199 depends on EXPERIMENTAL
200 depends on !XIP_KERNEL && MMU
201 depends on !ARCH_REALVIEW || !SPARSEMEM
203 Patch phys-to-virt and virt-to-phys translation functions at
204 boot and module load time according to the position of the
205 kernel in system memory.
207 This can only be used with non-XIP MMU kernels where the base
208 of physical memory is at a 16MB boundary, or theoretically 64K
209 for the MSM machine class.
211 config ARM_PATCH_PHYS_VIRT_16BIT
213 depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM
215 This option extends the physical to virtual translation patching
216 to allow physical memory down to a theoretical minimum of 64K
219 source "init/Kconfig"
221 source "kernel/Kconfig.freezer"
226 bool "MMU-based Paged Memory Management Support"
229 Select if you want MMU-based virtualised addressing space
230 support by paged memory management. If unsure, say 'Y'.
233 # The "ARM system type" choice list is ordered alphabetically by option
234 # text. Please add new entries in the option alphabetic order.
237 prompt "ARM system type"
238 default ARCH_VERSATILE
240 config ARCH_INTEGRATOR
241 bool "ARM Ltd. Integrator family"
243 select ARCH_HAS_CPUFREQ
246 select GENERIC_CLOCKEVENTS
247 select PLAT_VERSATILE
248 select PLAT_VERSATILE_FPGA_IRQ
250 Support for ARM's Integrator platform.
253 bool "ARM Ltd. RealView family"
257 select GENERIC_CLOCKEVENTS
258 select ARCH_WANT_OPTIONAL_GPIOLIB
259 select PLAT_VERSATILE
260 select PLAT_VERSATILE_CLCD
261 select ARM_TIMER_SP804
262 select GPIO_PL061 if GPIOLIB
264 This enables support for ARM Ltd RealView boards.
266 config ARCH_VERSATILE
267 bool "ARM Ltd. Versatile family"
272 select GENERIC_CLOCKEVENTS
273 select ARCH_WANT_OPTIONAL_GPIOLIB
274 select PLAT_VERSATILE
275 select PLAT_VERSATILE_CLCD
276 select PLAT_VERSATILE_FPGA_IRQ
277 select ARM_TIMER_SP804
279 This enables support for ARM Ltd Versatile board.
282 bool "ARM Ltd. Versatile Express family"
283 select ARCH_WANT_OPTIONAL_GPIOLIB
285 select ARM_TIMER_SP804
287 select GENERIC_CLOCKEVENTS
289 select HAVE_PATA_PLATFORM
291 select PLAT_VERSATILE
292 select PLAT_VERSATILE_CLCD
294 This enables support for the ARM Ltd Versatile Express boards.
298 select ARCH_REQUIRE_GPIOLIB
301 select ARM_PATCH_PHYS_VIRT if MMU
303 This enables support for systems based on the Atmel AT91RM9200,
304 AT91SAM9 and AT91CAP9 processors.
307 bool "Broadcom BCMRING"
311 select ARM_TIMER_SP804
313 select GENERIC_CLOCKEVENTS
314 select ARCH_WANT_OPTIONAL_GPIOLIB
316 Support for Broadcom's BCMRing platform.
319 bool "Cirrus Logic CLPS711x/EP721x-based"
321 select ARCH_USES_GETTIMEOFFSET
323 Support for Cirrus Logic 711x/721x based boards.
326 bool "Cavium Networks CNS3XXX family"
328 select GENERIC_CLOCKEVENTS
330 select MIGHT_HAVE_PCI
331 select PCI_DOMAINS if PCI
333 Support for Cavium Networks CNS3XXX platform.
336 bool "Cortina Systems Gemini"
338 select ARCH_REQUIRE_GPIOLIB
339 select ARCH_USES_GETTIMEOFFSET
341 Support for the Cortina Systems Gemini family SoCs
344 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
348 select GENERIC_CLOCKEVENTS
350 select GENERIC_IRQ_CHIP
354 Support for CSR SiRFSoC ARM Cortex A9 Platform
361 select ARCH_USES_GETTIMEOFFSET
363 This is an evaluation board for the StrongARM processor available
364 from Digital. It has limited hardware on-board, including an
365 Ethernet interface, two PCMCIA sockets, two serial ports and a
374 select ARCH_REQUIRE_GPIOLIB
375 select ARCH_HAS_HOLES_MEMORYMODEL
376 select ARCH_USES_GETTIMEOFFSET
378 This enables support for the Cirrus EP93xx series of CPUs.
380 config ARCH_FOOTBRIDGE
384 select GENERIC_CLOCKEVENTS
386 Support for systems based on the DC21285 companion chip
387 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
390 bool "Freescale MXC/iMX-based"
391 select GENERIC_CLOCKEVENTS
392 select ARCH_REQUIRE_GPIOLIB
395 select HAVE_SCHED_CLOCK
397 Support for Freescale MXC/iMX-based family of processors
400 bool "Freescale MXS-based"
401 select GENERIC_CLOCKEVENTS
402 select ARCH_REQUIRE_GPIOLIB
406 Support for Freescale MXS-based family of processors
409 bool "Hilscher NetX based"
413 select GENERIC_CLOCKEVENTS
415 This enables support for systems based on the Hilscher NetX Soc
418 bool "Hynix HMS720x-based"
421 select ARCH_USES_GETTIMEOFFSET
423 This enables support for systems based on the Hynix HMS720x
431 select ARCH_SUPPORTS_MSI
434 Support for Intel's IOP13XX (XScale) family of processors.
442 select ARCH_REQUIRE_GPIOLIB
444 Support for Intel's 80219 and IOP32X (XScale) family of
453 select ARCH_REQUIRE_GPIOLIB
455 Support for Intel's IOP33X (XScale) family of processors.
462 select ARCH_USES_GETTIMEOFFSET
464 Support for Intel's IXP23xx (XScale) family of processors.
467 bool "IXP2400/2800-based"
471 select ARCH_USES_GETTIMEOFFSET
473 Support for Intel's IXP2400/2800 (XScale) family of processors.
481 select GENERIC_CLOCKEVENTS
482 select HAVE_SCHED_CLOCK
483 select MIGHT_HAVE_PCI
484 select DMABOUNCE if PCI
486 Support for Intel's IXP4XX (XScale) family of processors.
492 select ARCH_REQUIRE_GPIOLIB
493 select GENERIC_CLOCKEVENTS
496 Support for the Marvell Dove SoC 88AP510
499 bool "Marvell Kirkwood"
502 select ARCH_REQUIRE_GPIOLIB
503 select GENERIC_CLOCKEVENTS
506 Support for the following Marvell Kirkwood series SoCs:
507 88F6180, 88F6192 and 88F6281.
513 select ARCH_REQUIRE_GPIOLIB
516 select USB_ARCH_HAS_OHCI
519 select GENERIC_CLOCKEVENTS
521 Support for the NXP LPC32XX family of processors
524 bool "Marvell MV78xx0"
527 select ARCH_REQUIRE_GPIOLIB
528 select GENERIC_CLOCKEVENTS
531 Support for the following Marvell MV78xx0 series SoCs:
539 select ARCH_REQUIRE_GPIOLIB
540 select GENERIC_CLOCKEVENTS
543 Support for the following Marvell Orion 5x series SoCs:
544 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
545 Orion-2 (5281), Orion-1-90 (6183).
548 bool "Marvell PXA168/910/MMP2"
550 select ARCH_REQUIRE_GPIOLIB
552 select GENERIC_CLOCKEVENTS
553 select HAVE_SCHED_CLOCK
558 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
561 bool "Micrel/Kendin KS8695"
563 select ARCH_REQUIRE_GPIOLIB
564 select ARCH_USES_GETTIMEOFFSET
566 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
567 System-on-Chip devices.
570 bool "Nuvoton W90X900 CPU"
572 select ARCH_REQUIRE_GPIOLIB
575 select GENERIC_CLOCKEVENTS
577 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
578 At present, the w90x900 has been renamed nuc900, regarding
579 the ARM series product line, you can login the following
580 link address to know more.
582 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
583 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
586 bool "Nuvoton NUC93X CPU"
590 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
591 low-power and high performance MPEG-4/JPEG multimedia controller chip.
598 select GENERIC_CLOCKEVENTS
601 select HAVE_SCHED_CLOCK
602 select ARCH_HAS_BARRIERS if CACHE_L2X0
603 select ARCH_HAS_CPUFREQ
605 This enables support for NVIDIA Tegra based systems (Tegra APX,
606 Tegra 6xx and Tegra 2 series).
609 bool "Philips Nexperia PNX4008 Mobile"
612 select ARCH_USES_GETTIMEOFFSET
614 This enables support for Philips PNX4008 mobile platform.
617 bool "PXA2xx/PXA3xx-based"
620 select ARCH_HAS_CPUFREQ
623 select ARCH_REQUIRE_GPIOLIB
624 select GENERIC_CLOCKEVENTS
625 select HAVE_SCHED_CLOCK
630 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
635 select GENERIC_CLOCKEVENTS
636 select ARCH_REQUIRE_GPIOLIB
639 Support for Qualcomm MSM/QSD based systems. This runs on the
640 apps processor of the MSM/QSD and depends on a shared memory
641 interface to the modem processor which runs the baseband
642 stack and controls some vital subsystems
643 (clock and power control, etc).
646 bool "Renesas SH-Mobile / R-Mobile"
649 select GENERIC_CLOCKEVENTS
652 select MULTI_IRQ_HANDLER
653 select PM_GENERIC_DOMAINS if PM
655 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
662 select ARCH_MAY_HAVE_PC_FDC
663 select HAVE_PATA_PLATFORM
666 select ARCH_SPARSEMEM_ENABLE
667 select ARCH_USES_GETTIMEOFFSET
669 On the Acorn Risc-PC, Linux can support the internal IDE disk and
670 CD-ROM interface, serial and parallel port, and the floppy drive.
677 select ARCH_SPARSEMEM_ENABLE
679 select ARCH_HAS_CPUFREQ
681 select GENERIC_CLOCKEVENTS
683 select HAVE_SCHED_CLOCK
685 select ARCH_REQUIRE_GPIOLIB
687 Support for StrongARM 11x0 based boards.
690 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
692 select ARCH_HAS_CPUFREQ
695 select ARCH_USES_GETTIMEOFFSET
696 select HAVE_S3C2410_I2C if I2C
698 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
699 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
700 the Samsung SMDK2410 development board (and derivatives).
702 Note, the S3C2416 and the S3C2450 are so close that they even share
703 the same SoC ID code. This means that there is no separate machine
704 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
707 bool "Samsung S3C64XX"
714 select ARCH_USES_GETTIMEOFFSET
715 select ARCH_HAS_CPUFREQ
716 select ARCH_REQUIRE_GPIOLIB
717 select SAMSUNG_CLKSRC
718 select SAMSUNG_IRQ_VIC_TIMER
719 select SAMSUNG_IRQ_UART
720 select S3C_GPIO_TRACK
721 select S3C_GPIO_PULL_UPDOWN
722 select S3C_GPIO_CFG_S3C24XX
723 select S3C_GPIO_CFG_S3C64XX
725 select USB_ARCH_HAS_OHCI
726 select SAMSUNG_GPIOLIB_4BIT
727 select HAVE_S3C2410_I2C if I2C
728 select HAVE_S3C2410_WATCHDOG if WATCHDOG
730 Samsung S3C64XX series based systems
733 bool "Samsung S5P6440 S5P6450"
739 select HAVE_S3C2410_WATCHDOG if WATCHDOG
740 select GENERIC_CLOCKEVENTS
741 select HAVE_SCHED_CLOCK
742 select HAVE_S3C2410_I2C if I2C
743 select HAVE_S3C_RTC if RTC_CLASS
745 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
749 bool "Samsung S5PC100"
754 select ARM_L1_CACHE_SHIFT_6
755 select ARCH_USES_GETTIMEOFFSET
756 select HAVE_S3C2410_I2C if I2C
757 select HAVE_S3C_RTC if RTC_CLASS
758 select HAVE_S3C2410_WATCHDOG if WATCHDOG
760 Samsung S5PC100 series based systems
763 bool "Samsung S5PV210/S5PC110"
765 select ARCH_SPARSEMEM_ENABLE
770 select ARM_L1_CACHE_SHIFT_6
771 select ARCH_HAS_CPUFREQ
772 select GENERIC_CLOCKEVENTS
773 select HAVE_SCHED_CLOCK
774 select HAVE_S3C2410_I2C if I2C
775 select HAVE_S3C_RTC if RTC_CLASS
776 select HAVE_S3C2410_WATCHDOG if WATCHDOG
778 Samsung S5PV210/S5PC110 series based systems
781 bool "Samsung EXYNOS4"
783 select ARCH_SPARSEMEM_ENABLE
787 select ARCH_HAS_CPUFREQ
788 select GENERIC_CLOCKEVENTS
789 select HAVE_S3C_RTC if RTC_CLASS
790 select HAVE_S3C2410_I2C if I2C
791 select HAVE_S3C2410_WATCHDOG if WATCHDOG
793 Samsung EXYNOS4 series based systems
802 select ARCH_USES_GETTIMEOFFSET
804 Support for the StrongARM based Digital DNARD machine, also known
805 as "Shark" (<http://www.shark-linux.de/shark.html>).
808 bool "Telechips TCC ARM926-based systems"
813 select GENERIC_CLOCKEVENTS
815 Support for Telechips TCC ARM926-based systems.
818 bool "ST-Ericsson U300 Series"
822 select HAVE_SCHED_CLOCK
826 select GENERIC_CLOCKEVENTS
830 Support for ST-Ericsson U300 series mobile platforms.
833 bool "ST-Ericsson U8500 Series"
836 select GENERIC_CLOCKEVENTS
838 select ARCH_REQUIRE_GPIOLIB
839 select ARCH_HAS_CPUFREQ
841 Support for ST-Ericsson's Ux500 architecture
844 bool "STMicroelectronics Nomadik"
849 select GENERIC_CLOCKEVENTS
850 select ARCH_REQUIRE_GPIOLIB
852 Support for the Nomadik platform by ST-Ericsson
856 select GENERIC_CLOCKEVENTS
857 select ARCH_REQUIRE_GPIOLIB
861 select GENERIC_ALLOCATOR
862 select GENERIC_IRQ_CHIP
863 select ARCH_HAS_HOLES_MEMORYMODEL
865 Support for TI's DaVinci platform.
870 select ARCH_REQUIRE_GPIOLIB
871 select ARCH_HAS_CPUFREQ
873 select GENERIC_CLOCKEVENTS
874 select HAVE_SCHED_CLOCK
875 select ARCH_HAS_HOLES_MEMORYMODEL
877 Support for TI's OMAP platform (OMAP1/2/3/4).
882 select ARCH_REQUIRE_GPIOLIB
885 select GENERIC_CLOCKEVENTS
888 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
891 bool "VIA/WonderMedia 85xx"
894 select ARCH_HAS_CPUFREQ
895 select GENERIC_CLOCKEVENTS
896 select ARCH_REQUIRE_GPIOLIB
899 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
902 bool "Xilinx Zynq ARM Cortex A9 Platform"
905 select GENERIC_CLOCKEVENTS
912 Support for Xilinx Zynq ARM Cortex A9 Platform
916 # This is sorted alphabetically by mach-* pathname. However, plat-*
917 # Kconfigs may be included either alphabetically (according to the
918 # plat- suffix) or along side the corresponding mach-* source.
920 source "arch/arm/mach-at91/Kconfig"
922 source "arch/arm/mach-bcmring/Kconfig"
924 source "arch/arm/mach-clps711x/Kconfig"
926 source "arch/arm/mach-cns3xxx/Kconfig"
928 source "arch/arm/mach-davinci/Kconfig"
930 source "arch/arm/mach-dove/Kconfig"
932 source "arch/arm/mach-ep93xx/Kconfig"
934 source "arch/arm/mach-footbridge/Kconfig"
936 source "arch/arm/mach-gemini/Kconfig"
938 source "arch/arm/mach-h720x/Kconfig"
940 source "arch/arm/mach-integrator/Kconfig"
942 source "arch/arm/mach-iop32x/Kconfig"
944 source "arch/arm/mach-iop33x/Kconfig"
946 source "arch/arm/mach-iop13xx/Kconfig"
948 source "arch/arm/mach-ixp4xx/Kconfig"
950 source "arch/arm/mach-ixp2000/Kconfig"
952 source "arch/arm/mach-ixp23xx/Kconfig"
954 source "arch/arm/mach-kirkwood/Kconfig"
956 source "arch/arm/mach-ks8695/Kconfig"
958 source "arch/arm/mach-lpc32xx/Kconfig"
960 source "arch/arm/mach-msm/Kconfig"
962 source "arch/arm/mach-mv78xx0/Kconfig"
964 source "arch/arm/plat-mxc/Kconfig"
966 source "arch/arm/mach-mxs/Kconfig"
968 source "arch/arm/mach-netx/Kconfig"
970 source "arch/arm/mach-nomadik/Kconfig"
971 source "arch/arm/plat-nomadik/Kconfig"
973 source "arch/arm/mach-nuc93x/Kconfig"
975 source "arch/arm/plat-omap/Kconfig"
977 source "arch/arm/mach-omap1/Kconfig"
979 source "arch/arm/mach-omap2/Kconfig"
981 source "arch/arm/mach-orion5x/Kconfig"
983 source "arch/arm/mach-pxa/Kconfig"
984 source "arch/arm/plat-pxa/Kconfig"
986 source "arch/arm/mach-mmp/Kconfig"
988 source "arch/arm/mach-realview/Kconfig"
990 source "arch/arm/mach-sa1100/Kconfig"
992 source "arch/arm/plat-samsung/Kconfig"
993 source "arch/arm/plat-s3c24xx/Kconfig"
994 source "arch/arm/plat-s5p/Kconfig"
996 source "arch/arm/plat-spear/Kconfig"
998 source "arch/arm/plat-tcc/Kconfig"
1001 source "arch/arm/mach-s3c2410/Kconfig"
1002 source "arch/arm/mach-s3c2412/Kconfig"
1003 source "arch/arm/mach-s3c2416/Kconfig"
1004 source "arch/arm/mach-s3c2440/Kconfig"
1005 source "arch/arm/mach-s3c2443/Kconfig"
1009 source "arch/arm/mach-s3c64xx/Kconfig"
1012 source "arch/arm/mach-s5p64x0/Kconfig"
1014 source "arch/arm/mach-s5pc100/Kconfig"
1016 source "arch/arm/mach-s5pv210/Kconfig"
1018 source "arch/arm/mach-exynos4/Kconfig"
1020 source "arch/arm/mach-shmobile/Kconfig"
1022 source "arch/arm/mach-tegra/Kconfig"
1024 source "arch/arm/mach-u300/Kconfig"
1026 source "arch/arm/mach-ux500/Kconfig"
1028 source "arch/arm/mach-versatile/Kconfig"
1030 source "arch/arm/mach-vexpress/Kconfig"
1031 source "arch/arm/plat-versatile/Kconfig"
1033 source "arch/arm/mach-vt8500/Kconfig"
1035 source "arch/arm/mach-w90x900/Kconfig"
1037 # Definitions to make life easier
1043 select GENERIC_CLOCKEVENTS
1044 select HAVE_SCHED_CLOCK
1049 select GENERIC_IRQ_CHIP
1050 select HAVE_SCHED_CLOCK
1055 config PLAT_VERSATILE
1058 config ARM_TIMER_SP804
1062 source arch/arm/mm/Kconfig
1065 bool "Enable iWMMXt support"
1066 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1067 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1069 Enable support for iWMMXt context switching at run time if
1070 running on a CPU that supports it.
1072 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1075 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1079 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1080 (!ARCH_OMAP3 || OMAP3_EMU)
1084 config MULTI_IRQ_HANDLER
1087 Allow each machine to specify it's own IRQ handler at run time.
1090 source "arch/arm/Kconfig-nommu"
1093 config ARM_ERRATA_411920
1094 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1095 depends on CPU_V6 || CPU_V6K
1097 Invalidation of the Instruction Cache operation can
1098 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1099 It does not affect the MPCore. This option enables the ARM Ltd.
1100 recommended workaround.
1102 config ARM_ERRATA_430973
1103 bool "ARM errata: Stale prediction on replaced interworking branch"
1106 This option enables the workaround for the 430973 Cortex-A8
1107 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1108 interworking branch is replaced with another code sequence at the
1109 same virtual address, whether due to self-modifying code or virtual
1110 to physical address re-mapping, Cortex-A8 does not recover from the
1111 stale interworking branch prediction. This results in Cortex-A8
1112 executing the new code sequence in the incorrect ARM or Thumb state.
1113 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1114 and also flushes the branch target cache at every context switch.
1115 Note that setting specific bits in the ACTLR register may not be
1116 available in non-secure mode.
1118 config ARM_ERRATA_458693
1119 bool "ARM errata: Processor deadlock when a false hazard is created"
1122 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1123 erratum. For very specific sequences of memory operations, it is
1124 possible for a hazard condition intended for a cache line to instead
1125 be incorrectly associated with a different cache line. This false
1126 hazard might then cause a processor deadlock. The workaround enables
1127 the L1 caching of the NEON accesses and disables the PLD instruction
1128 in the ACTLR register. Note that setting specific bits in the ACTLR
1129 register may not be available in non-secure mode.
1131 config ARM_ERRATA_460075
1132 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1135 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1136 erratum. Any asynchronous access to the L2 cache may encounter a
1137 situation in which recent store transactions to the L2 cache are lost
1138 and overwritten with stale memory contents from external memory. The
1139 workaround disables the write-allocate mode for the L2 cache via the
1140 ACTLR register. Note that setting specific bits in the ACTLR register
1141 may not be available in non-secure mode.
1143 config ARM_ERRATA_742230
1144 bool "ARM errata: DMB operation may be faulty"
1145 depends on CPU_V7 && SMP
1147 This option enables the workaround for the 742230 Cortex-A9
1148 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1149 between two write operations may not ensure the correct visibility
1150 ordering of the two writes. This workaround sets a specific bit in
1151 the diagnostic register of the Cortex-A9 which causes the DMB
1152 instruction to behave as a DSB, ensuring the correct behaviour of
1155 config ARM_ERRATA_742231
1156 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1157 depends on CPU_V7 && SMP
1159 This option enables the workaround for the 742231 Cortex-A9
1160 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1161 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1162 accessing some data located in the same cache line, may get corrupted
1163 data due to bad handling of the address hazard when the line gets
1164 replaced from one of the CPUs at the same time as another CPU is
1165 accessing it. This workaround sets specific bits in the diagnostic
1166 register of the Cortex-A9 which reduces the linefill issuing
1167 capabilities of the processor.
1169 config PL310_ERRATA_588369
1170 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1171 depends on CACHE_L2X0
1173 The PL310 L2 cache controller implements three types of Clean &
1174 Invalidate maintenance operations: by Physical Address
1175 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1176 They are architecturally defined to behave as the execution of a
1177 clean operation followed immediately by an invalidate operation,
1178 both performing to the same memory location. This functionality
1179 is not correctly implemented in PL310 as clean lines are not
1180 invalidated as a result of these operations.
1182 config ARM_ERRATA_720789
1183 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1184 depends on CPU_V7 && SMP
1186 This option enables the workaround for the 720789 Cortex-A9 (prior to
1187 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1188 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1189 As a consequence of this erratum, some TLB entries which should be
1190 invalidated are not, resulting in an incoherency in the system page
1191 tables. The workaround changes the TLB flushing routines to invalidate
1192 entries regardless of the ASID.
1194 config PL310_ERRATA_727915
1195 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1196 depends on CACHE_L2X0
1198 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1199 operation (offset 0x7FC). This operation runs in background so that
1200 PL310 can handle normal accesses while it is in progress. Under very
1201 rare circumstances, due to this erratum, write data can be lost when
1202 PL310 treats a cacheable write transaction during a Clean &
1203 Invalidate by Way operation.
1205 config ARM_ERRATA_743622
1206 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1209 This option enables the workaround for the 743622 Cortex-A9
1210 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1211 optimisation in the Cortex-A9 Store Buffer may lead to data
1212 corruption. This workaround sets a specific bit in the diagnostic
1213 register of the Cortex-A9 which disables the Store Buffer
1214 optimisation, preventing the defect from occurring. This has no
1215 visible impact on the overall performance or power consumption of the
1218 config ARM_ERRATA_751472
1219 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1220 depends on CPU_V7 && SMP
1222 This option enables the workaround for the 751472 Cortex-A9 (prior
1223 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1224 completion of a following broadcasted operation if the second
1225 operation is received by a CPU before the ICIALLUIS has completed,
1226 potentially leading to corrupted entries in the cache or TLB.
1228 config ARM_ERRATA_753970
1229 bool "ARM errata: cache sync operation may be faulty"
1230 depends on CACHE_PL310
1232 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1234 Under some condition the effect of cache sync operation on
1235 the store buffer still remains when the operation completes.
1236 This means that the store buffer is always asked to drain and
1237 this prevents it from merging any further writes. The workaround
1238 is to replace the normal offset of cache sync operation (0x730)
1239 by another offset targeting an unmapped PL310 register 0x740.
1240 This has the same effect as the cache sync operation: store buffer
1241 drain and waiting for all buffers empty.
1243 config ARM_ERRATA_754322
1244 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1247 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1248 r3p*) erratum. A speculative memory access may cause a page table walk
1249 which starts prior to an ASID switch but completes afterwards. This
1250 can populate the micro-TLB with a stale entry which may be hit with
1251 the new ASID. This workaround places two dsb instructions in the mm
1252 switching code so that no page table walks can cross the ASID switch.
1254 config ARM_ERRATA_754327
1255 bool "ARM errata: no automatic Store Buffer drain"
1256 depends on CPU_V7 && SMP
1258 This option enables the workaround for the 754327 Cortex-A9 (prior to
1259 r2p0) erratum. The Store Buffer does not have any automatic draining
1260 mechanism and therefore a livelock may occur if an external agent
1261 continuously polls a memory location waiting to observe an update.
1262 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1263 written polling loops from denying visibility of updates to memory.
1267 source "arch/arm/common/Kconfig"
1277 Find out whether you have ISA slots on your motherboard. ISA is the
1278 name of a bus system, i.e. the way the CPU talks to the other stuff
1279 inside your box. Other bus systems are PCI, EISA, MicroChannel
1280 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1281 newer boards don't support it. If you have ISA, say Y, otherwise N.
1283 # Select ISA DMA controller support
1288 # Select ISA DMA interface
1293 bool "PCI support" if MIGHT_HAVE_PCI
1295 Find out whether you have a PCI motherboard. PCI is the name of a
1296 bus system, i.e. the way the CPU talks to the other stuff inside
1297 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1298 VESA. If you have PCI, say Y, otherwise N.
1304 config PCI_NANOENGINE
1305 bool "BSE nanoEngine PCI support"
1306 depends on SA1100_NANOENGINE
1308 Enable PCI on the BSE nanoEngine board.
1313 # Select the host bridge type
1314 config PCI_HOST_VIA82C505
1316 depends on PCI && ARCH_SHARK
1319 config PCI_HOST_ITE8152
1321 depends on PCI && MACH_ARMCORE
1325 source "drivers/pci/Kconfig"
1327 source "drivers/pcmcia/Kconfig"
1331 menu "Kernel Features"
1333 source "kernel/time/Kconfig"
1336 bool "Symmetric Multi-Processing"
1337 depends on CPU_V6K || CPU_V7
1338 depends on GENERIC_CLOCKEVENTS
1339 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1340 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1341 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1342 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1343 select USE_GENERIC_SMP_HELPERS
1344 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1346 This enables support for systems with more than one CPU. If you have
1347 a system with only one CPU, like most personal computers, say N. If
1348 you have a system with more than one CPU, say Y.
1350 If you say N here, the kernel will run on single and multiprocessor
1351 machines, but will use only one CPU of a multiprocessor machine. If
1352 you say Y here, the kernel will run on many, but not all, single
1353 processor machines. On a single processor machine, the kernel will
1354 run faster if you say N here.
1356 See also <file:Documentation/i386/IO-APIC.txt>,
1357 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1358 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1360 If you don't know what to do here, say N.
1363 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1364 depends on EXPERIMENTAL
1365 depends on SMP && !XIP_KERNEL
1368 SMP kernels contain instructions which fail on non-SMP processors.
1369 Enabling this option allows the kernel to modify itself to make
1370 these instructions safe. Disabling it allows about 1K of space
1373 If you don't know what to do here, say Y.
1378 This option enables support for the ARM system coherency unit
1385 This options enables support for the ARM timer and watchdog unit
1388 prompt "Memory split"
1391 Select the desired split between kernel and user memory.
1393 If you are not absolutely sure what you are doing, leave this
1397 bool "3G/1G user/kernel split"
1399 bool "2G/2G user/kernel split"
1401 bool "1G/3G user/kernel split"
1406 default 0x40000000 if VMSPLIT_1G
1407 default 0x80000000 if VMSPLIT_2G
1411 int "Maximum number of CPUs (2-32)"
1417 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1418 depends on SMP && HOTPLUG && EXPERIMENTAL
1420 Say Y here to experiment with turning CPUs off and on. CPUs
1421 can be controlled through /sys/devices/system/cpu.
1424 bool "Use local timer interrupts"
1427 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1429 Enable support for local timers on SMP platforms, rather then the
1430 legacy IPI broadcast method. Local timers allows the system
1431 accounting to be spread across the timer interval, preventing a
1432 "thundering herd" at every timer tick.
1434 source kernel/Kconfig.preempt
1438 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1439 ARCH_S5PV210 || ARCH_EXYNOS4
1440 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1441 default AT91_TIMER_HZ if ARCH_AT91
1442 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1445 config THUMB2_KERNEL
1446 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1447 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1449 select ARM_ASM_UNIFIED
1451 By enabling this option, the kernel will be compiled in
1452 Thumb-2 mode. A compiler/assembler that understand the unified
1453 ARM-Thumb syntax is needed.
1457 config THUMB2_AVOID_R_ARM_THM_JUMP11
1458 bool "Work around buggy Thumb-2 short branch relocations in gas"
1459 depends on THUMB2_KERNEL && MODULES
1462 Various binutils versions can resolve Thumb-2 branches to
1463 locally-defined, preemptible global symbols as short-range "b.n"
1464 branch instructions.
1466 This is a problem, because there's no guarantee the final
1467 destination of the symbol, or any candidate locations for a
1468 trampoline, are within range of the branch. For this reason, the
1469 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1470 relocation in modules at all, and it makes little sense to add
1473 The symptom is that the kernel fails with an "unsupported
1474 relocation" error when loading some modules.
1476 Until fixed tools are available, passing
1477 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1478 code which hits this problem, at the cost of a bit of extra runtime
1479 stack usage in some cases.
1481 The problem is described in more detail at:
1482 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1484 Only Thumb-2 kernels are affected.
1486 Unless you are sure your tools don't have this problem, say Y.
1488 config ARM_ASM_UNIFIED
1492 bool "Use the ARM EABI to compile the kernel"
1494 This option allows for the kernel to be compiled using the latest
1495 ARM ABI (aka EABI). This is only useful if you are using a user
1496 space environment that is also compiled with EABI.
1498 Since there are major incompatibilities between the legacy ABI and
1499 EABI, especially with regard to structure member alignment, this
1500 option also changes the kernel syscall calling convention to
1501 disambiguate both ABIs and allow for backward compatibility support
1502 (selected with CONFIG_OABI_COMPAT).
1504 To use this you need GCC version 4.0.0 or later.
1507 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1508 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1511 This option preserves the old syscall interface along with the
1512 new (ARM EABI) one. It also provides a compatibility layer to
1513 intercept syscalls that have structure arguments which layout
1514 in memory differs between the legacy ABI and the new ARM EABI
1515 (only for non "thumb" binaries). This option adds a tiny
1516 overhead to all syscalls and produces a slightly larger kernel.
1517 If you know you'll be using only pure EABI user space then you
1518 can say N here. If this option is not selected and you attempt
1519 to execute a legacy ABI binary then the result will be
1520 UNPREDICTABLE (in fact it can be predicted that it won't work
1521 at all). If in doubt say Y.
1523 config ARCH_HAS_HOLES_MEMORYMODEL
1526 config ARCH_SPARSEMEM_ENABLE
1529 config ARCH_SPARSEMEM_DEFAULT
1530 def_bool ARCH_SPARSEMEM_ENABLE
1532 config ARCH_SELECT_MEMORY_MODEL
1533 def_bool ARCH_SPARSEMEM_ENABLE
1535 config HAVE_ARCH_PFN_VALID
1536 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1539 bool "High Memory Support"
1542 The address space of ARM processors is only 4 Gigabytes large
1543 and it has to accommodate user address space, kernel address
1544 space as well as some memory mapped IO. That means that, if you
1545 have a large amount of physical memory and/or IO, not all of the
1546 memory can be "permanently mapped" by the kernel. The physical
1547 memory that is not permanently mapped is called "high memory".
1549 Depending on the selected kernel/user memory split, minimum
1550 vmalloc space and actual amount of RAM, you may not need this
1551 option which should result in a slightly faster kernel.
1556 bool "Allocate 2nd-level pagetables from highmem"
1559 config HW_PERF_EVENTS
1560 bool "Enable hardware performance counter support for perf events"
1561 depends on PERF_EVENTS && CPU_HAS_PMU
1564 Enable hardware performance counter support for perf events. If
1565 disabled, perf events will use software events only.
1569 config FORCE_MAX_ZONEORDER
1570 int "Maximum zone order" if ARCH_SHMOBILE
1571 range 11 64 if ARCH_SHMOBILE
1572 default "9" if SA1111
1575 The kernel memory allocator divides physically contiguous memory
1576 blocks into "zones", where each zone is a power of two number of
1577 pages. This option selects the largest power of two that the kernel
1578 keeps in the memory allocator. If you need to allocate very large
1579 blocks of physically contiguous memory, then you may need to
1580 increase this value.
1582 This config option is actually maximum order plus one. For example,
1583 a value of 11 means that the largest free memory block is 2^10 pages.
1586 bool "Timer and CPU usage LEDs"
1587 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1588 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1589 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1590 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1591 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1592 ARCH_AT91 || ARCH_DAVINCI || \
1593 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1595 If you say Y here, the LEDs on your machine will be used
1596 to provide useful information about your current system status.
1598 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1599 be able to select which LEDs are active using the options below. If
1600 you are compiling a kernel for the EBSA-110 or the LART however, the
1601 red LED will simply flash regularly to indicate that the system is
1602 still functional. It is safe to say Y here if you have a CATS
1603 system, but the driver will do nothing.
1606 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1607 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1608 || MACH_OMAP_PERSEUS2
1610 depends on !GENERIC_CLOCKEVENTS
1611 default y if ARCH_EBSA110
1613 If you say Y here, one of the system LEDs (the green one on the
1614 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1615 will flash regularly to indicate that the system is still
1616 operational. This is mainly useful to kernel hackers who are
1617 debugging unstable kernels.
1619 The LART uses the same LED for both Timer LED and CPU usage LED
1620 functions. You may choose to use both, but the Timer LED function
1621 will overrule the CPU usage LED.
1624 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1626 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1627 || MACH_OMAP_PERSEUS2
1630 If you say Y here, the red LED will be used to give a good real
1631 time indication of CPU usage, by lighting whenever the idle task
1632 is not currently executing.
1634 The LART uses the same LED for both Timer LED and CPU usage LED
1635 functions. You may choose to use both, but the Timer LED function
1636 will overrule the CPU usage LED.
1638 config ALIGNMENT_TRAP
1640 depends on CPU_CP15_MMU
1641 default y if !ARCH_EBSA110
1642 select HAVE_PROC_CPU if PROC_FS
1644 ARM processors cannot fetch/store information which is not
1645 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1646 address divisible by 4. On 32-bit ARM processors, these non-aligned
1647 fetch/store instructions will be emulated in software if you say
1648 here, which has a severe performance impact. This is necessary for
1649 correct operation of some network protocols. With an IP-only
1650 configuration it is safe to say N, otherwise say Y.
1652 config UACCESS_WITH_MEMCPY
1653 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1654 depends on MMU && EXPERIMENTAL
1655 default y if CPU_FEROCEON
1657 Implement faster copy_to_user and clear_user methods for CPU
1658 cores where a 8-word STM instruction give significantly higher
1659 memory write throughput than a sequence of individual 32bit stores.
1661 A possible side effect is a slight increase in scheduling latency
1662 between threads sharing the same address space if they invoke
1663 such copy operations with large buffers.
1665 However, if the CPU data cache is using a write-allocate mode,
1666 this option is unlikely to provide any performance gain.
1670 prompt "Enable seccomp to safely compute untrusted bytecode"
1672 This kernel feature is useful for number crunching applications
1673 that may need to compute untrusted bytecode during their
1674 execution. By using pipes or other transports made available to
1675 the process as file descriptors supporting the read/write
1676 syscalls, it's possible to isolate those applications in
1677 their own address space using seccomp. Once seccomp is
1678 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1679 and the task is only allowed to execute a few safe syscalls
1680 defined by each seccomp mode.
1682 config CC_STACKPROTECTOR
1683 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1684 depends on EXPERIMENTAL
1686 This option turns on the -fstack-protector GCC feature. This
1687 feature puts, at the beginning of functions, a canary value on
1688 the stack just before the return address, and validates
1689 the value just before actually returning. Stack based buffer
1690 overflows (that need to overwrite this return address) now also
1691 overwrite the canary, which gets detected and the attack is then
1692 neutralized via a kernel panic.
1693 This feature requires gcc version 4.2 or above.
1695 config DEPRECATED_PARAM_STRUCT
1696 bool "Provide old way to pass kernel parameters"
1698 This was deprecated in 2001 and announced to live on for 5 years.
1699 Some old boot loaders still use this way.
1706 bool "Flattened Device Tree support"
1708 select OF_EARLY_FLATTREE
1710 Include support for flattened device tree machine descriptions.
1712 # Compressed boot loader in ROM. Yes, we really want to ask about
1713 # TEXT and BSS so we preserve their values in the config files.
1714 config ZBOOT_ROM_TEXT
1715 hex "Compressed ROM boot loader base address"
1718 The physical address at which the ROM-able zImage is to be
1719 placed in the target. Platforms which normally make use of
1720 ROM-able zImage formats normally set this to a suitable
1721 value in their defconfig file.
1723 If ZBOOT_ROM is not enabled, this has no effect.
1725 config ZBOOT_ROM_BSS
1726 hex "Compressed ROM boot loader BSS address"
1729 The base address of an area of read/write memory in the target
1730 for the ROM-able zImage which must be available while the
1731 decompressor is running. It must be large enough to hold the
1732 entire decompressed kernel plus an additional 128 KiB.
1733 Platforms which normally make use of ROM-able zImage formats
1734 normally set this to a suitable value in their defconfig file.
1736 If ZBOOT_ROM is not enabled, this has no effect.
1739 bool "Compressed boot loader in ROM/flash"
1740 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1742 Say Y here if you intend to execute your compressed kernel image
1743 (zImage) directly from ROM or flash. If unsure, say N.
1746 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1747 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1748 default ZBOOT_ROM_NONE
1750 Include experimental SD/MMC loading code in the ROM-able zImage.
1751 With this enabled it is possible to write the the ROM-able zImage
1752 kernel image to an MMC or SD card and boot the kernel straight
1753 from the reset vector. At reset the processor Mask ROM will load
1754 the first part of the the ROM-able zImage which in turn loads the
1755 rest the kernel image to RAM.
1757 config ZBOOT_ROM_NONE
1758 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1760 Do not load image from SD or MMC
1762 config ZBOOT_ROM_MMCIF
1763 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1765 Load image from MMCIF hardware block.
1767 config ZBOOT_ROM_SH_MOBILE_SDHI
1768 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1770 Load image from SDHI hardware block
1775 string "Default kernel command string"
1778 On some architectures (EBSA110 and CATS), there is currently no way
1779 for the boot loader to pass arguments to the kernel. For these
1780 architectures, you should supply some command-line options at build
1781 time by entering them here. As a minimum, you should specify the
1782 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1785 prompt "Kernel command line type" if CMDLINE != ""
1786 default CMDLINE_FROM_BOOTLOADER
1788 config CMDLINE_FROM_BOOTLOADER
1789 bool "Use bootloader kernel arguments if available"
1791 Uses the command-line options passed by the boot loader. If
1792 the boot loader doesn't provide any, the default kernel command
1793 string provided in CMDLINE will be used.
1795 config CMDLINE_EXTEND
1796 bool "Extend bootloader kernel arguments"
1798 The command-line arguments provided by the boot loader will be
1799 appended to the default kernel command string.
1801 config CMDLINE_FORCE
1802 bool "Always use the default kernel command string"
1804 Always use the default kernel command string, even if the boot
1805 loader passes other arguments to the kernel.
1806 This is useful if you cannot or don't want to change the
1807 command-line options your boot loader passes to the kernel.
1811 bool "Kernel Execute-In-Place from ROM"
1812 depends on !ZBOOT_ROM
1814 Execute-In-Place allows the kernel to run from non-volatile storage
1815 directly addressable by the CPU, such as NOR flash. This saves RAM
1816 space since the text section of the kernel is not loaded from flash
1817 to RAM. Read-write sections, such as the data section and stack,
1818 are still copied to RAM. The XIP kernel is not compressed since
1819 it has to run directly from flash, so it will take more space to
1820 store it. The flash address used to link the kernel object files,
1821 and for storing it, is configuration dependent. Therefore, if you
1822 say Y here, you must know the proper physical address where to
1823 store the kernel image depending on your own flash memory usage.
1825 Also note that the make target becomes "make xipImage" rather than
1826 "make zImage" or "make Image". The final kernel binary to put in
1827 ROM memory will be arch/arm/boot/xipImage.
1831 config XIP_PHYS_ADDR
1832 hex "XIP Kernel Physical Location"
1833 depends on XIP_KERNEL
1834 default "0x00080000"
1836 This is the physical address in your flash memory the kernel will
1837 be linked for and stored to. This address is dependent on your
1841 bool "Kexec system call (EXPERIMENTAL)"
1842 depends on EXPERIMENTAL
1844 kexec is a system call that implements the ability to shutdown your
1845 current kernel, and to start another kernel. It is like a reboot
1846 but it is independent of the system firmware. And like a reboot
1847 you can start any kernel with it, not just Linux.
1849 It is an ongoing process to be certain the hardware in a machine
1850 is properly shutdown, so do not be surprised if this code does not
1851 initially work for you. It may help to enable device hotplugging
1855 bool "Export atags in procfs"
1859 Should the atags used to boot the kernel be exported in an "atags"
1860 file in procfs. Useful with kexec.
1863 bool "Build kdump crash kernel (EXPERIMENTAL)"
1864 depends on EXPERIMENTAL
1866 Generate crash dump after being started by kexec. This should
1867 be normally only set in special crash dump kernels which are
1868 loaded in the main kernel with kexec-tools into a specially
1869 reserved region and then later executed after a crash by
1870 kdump/kexec. The crash dump kernel must be compiled to a
1871 memory address not used by the main kernel
1873 For more details see Documentation/kdump/kdump.txt
1875 config AUTO_ZRELADDR
1876 bool "Auto calculation of the decompressed kernel image address"
1877 depends on !ZBOOT_ROM && !ARCH_U300
1879 ZRELADDR is the physical address where the decompressed kernel
1880 image will be placed. If AUTO_ZRELADDR is selected, the address
1881 will be determined at run-time by masking the current IP with
1882 0xf8000000. This assumes the zImage being placed in the first 128MB
1883 from start of memory.
1887 menu "CPU Power Management"
1891 source "drivers/cpufreq/Kconfig"
1894 tristate "CPUfreq driver for i.MX CPUs"
1895 depends on ARCH_MXC && CPU_FREQ
1897 This enables the CPUfreq driver for i.MX CPUs.
1899 config CPU_FREQ_SA1100
1902 config CPU_FREQ_SA1110
1905 config CPU_FREQ_INTEGRATOR
1906 tristate "CPUfreq driver for ARM Integrator CPUs"
1907 depends on ARCH_INTEGRATOR && CPU_FREQ
1910 This enables the CPUfreq driver for ARM Integrator CPUs.
1912 For details, take a look at <file:Documentation/cpu-freq>.
1918 depends on CPU_FREQ && ARCH_PXA && PXA25x
1920 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1925 Internal configuration node for common cpufreq on Samsung SoC
1927 config CPU_FREQ_S3C24XX
1928 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
1929 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1932 This enables the CPUfreq driver for the Samsung S3C24XX family
1935 For details, take a look at <file:Documentation/cpu-freq>.
1939 config CPU_FREQ_S3C24XX_PLL
1940 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
1941 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
1943 Compile in support for changing the PLL frequency from the
1944 S3C24XX series CPUfreq driver. The PLL takes time to settle
1945 after a frequency change, so by default it is not enabled.
1947 This also means that the PLL tables for the selected CPU(s) will
1948 be built which may increase the size of the kernel image.
1950 config CPU_FREQ_S3C24XX_DEBUG
1951 bool "Debug CPUfreq Samsung driver core"
1952 depends on CPU_FREQ_S3C24XX
1954 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
1956 config CPU_FREQ_S3C24XX_IODEBUG
1957 bool "Debug CPUfreq Samsung driver IO timing"
1958 depends on CPU_FREQ_S3C24XX
1960 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
1962 config CPU_FREQ_S3C24XX_DEBUGFS
1963 bool "Export debugfs for CPUFreq"
1964 depends on CPU_FREQ_S3C24XX && DEBUG_FS
1966 Export status information via debugfs.
1970 source "drivers/cpuidle/Kconfig"
1974 menu "Floating point emulation"
1976 comment "At least one emulation must be selected"
1979 bool "NWFPE math emulation"
1980 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1982 Say Y to include the NWFPE floating point emulator in the kernel.
1983 This is necessary to run most binaries. Linux does not currently
1984 support floating point hardware so you need to say Y here even if
1985 your machine has an FPA or floating point co-processor podule.
1987 You may say N here if you are going to load the Acorn FPEmulator
1988 early in the bootup.
1991 bool "Support extended precision"
1992 depends on FPE_NWFPE
1994 Say Y to include 80-bit support in the kernel floating-point
1995 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1996 Note that gcc does not generate 80-bit operations by default,
1997 so in most cases this option only enlarges the size of the
1998 floating point emulator without any good reason.
2000 You almost surely want to say N here.
2003 bool "FastFPE math emulation (EXPERIMENTAL)"
2004 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2006 Say Y here to include the FAST floating point emulator in the kernel.
2007 This is an experimental much faster emulator which now also has full
2008 precision for the mantissa. It does not support any exceptions.
2009 It is very simple, and approximately 3-6 times faster than NWFPE.
2011 It should be sufficient for most programs. It may be not suitable
2012 for scientific calculations, but you have to check this for yourself.
2013 If you do not feel you need a faster FP emulation you should better
2017 bool "VFP-format floating point maths"
2018 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2020 Say Y to include VFP support code in the kernel. This is needed
2021 if your hardware includes a VFP unit.
2023 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2024 release notes and additional status information.
2026 Say N if your target does not have VFP hardware.
2034 bool "Advanced SIMD (NEON) Extension support"
2035 depends on VFPv3 && CPU_V7
2037 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2042 menu "Userspace binary formats"
2044 source "fs/Kconfig.binfmt"
2047 tristate "RISC OS personality"
2050 Say Y here to include the kernel code necessary if you want to run
2051 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2052 experimental; if this sounds frightening, say N and sleep in peace.
2053 You can also say M here to compile this support as a module (which
2054 will be called arthur).
2058 menu "Power management options"
2060 source "kernel/power/Kconfig"
2062 config ARCH_SUSPEND_POSSIBLE
2063 depends on !ARCH_S5P64X0 && !ARCH_S5PC100
2064 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2065 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2070 source "net/Kconfig"
2072 source "drivers/Kconfig"
2076 source "arch/arm/Kconfig.debug"
2078 source "security/Kconfig"
2080 source "crypto/Kconfig"
2082 source "lib/Kconfig"