5 select HAVE_DMA_API_DEBUG
6 select HAVE_IDE if PCI || ISA || PCMCIA
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
12 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
14 select HAVE_KPROBES if !XIP_KERNEL
15 select HAVE_KRETPROBES if (HAVE_KPROBES)
16 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
17 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
18 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
19 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
20 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
21 select HAVE_GENERIC_DMA_COHERENT
22 select HAVE_KERNEL_GZIP
23 select HAVE_KERNEL_LZO
24 select HAVE_KERNEL_LZMA
27 select HAVE_PERF_EVENTS
28 select PERF_USE_VMALLOC
29 select HAVE_REGS_AND_STACK_ACCESS_API
30 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
31 select HAVE_C_RECORDMCOUNT
32 select HAVE_GENERIC_HARDIRQS
33 select GENERIC_IRQ_SHOW
34 select CPU_PM if (SUSPEND || CPU_IDLE)
35 select GENERIC_PCI_IOMAP
36 select HAVE_BPF_JIT if NET
38 The ARM series is a line of low-power-consumption RISC chip designs
39 licensed by ARM Ltd and targeted at embedded applications and
40 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
41 manufactured, but legacy ARM-based PC hardware remains popular in
42 Europe. There is an ARM Linux project with a web page at
43 <http://www.arm.linux.org.uk/>.
45 config ARM_HAS_SG_CHAIN
54 config SYS_SUPPORTS_APM_EMULATION
60 config ARCH_USES_GETTIMEOFFSET
64 config GENERIC_CLOCKEVENTS
67 config GENERIC_CLOCKEVENTS_BROADCAST
69 depends on GENERIC_CLOCKEVENTS
78 select GENERIC_ALLOCATOR
89 The Extended Industry Standard Architecture (EISA) bus was
90 developed as an open alternative to the IBM MicroChannel bus.
92 The EISA bus provided some of the features of the IBM MicroChannel
93 bus while maintaining backward compatibility with cards made for
94 the older ISA bus. The EISA bus saw limited use between 1988 and
95 1995 when it was made obsolete by the PCI bus.
97 Say Y here if you are building a kernel for an EISA-based machine.
107 MicroChannel Architecture is found in some IBM PS/2 machines and
108 laptops. It is a bus system similar to PCI or ISA. See
109 <file:Documentation/mca.txt> (and especially the web page given
110 there) before attempting to build an MCA bus kernel.
112 config STACKTRACE_SUPPORT
116 config HAVE_LATENCYTOP_SUPPORT
121 config LOCKDEP_SUPPORT
125 config TRACE_IRQFLAGS_SUPPORT
129 config HARDIRQS_SW_RESEND
133 config GENERIC_IRQ_PROBE
137 config GENERIC_LOCKBREAK
140 depends on SMP && PREEMPT
142 config RWSEM_GENERIC_SPINLOCK
146 config RWSEM_XCHGADD_ALGORITHM
149 config ARCH_HAS_ILOG2_U32
152 config ARCH_HAS_ILOG2_U64
155 config ARCH_HAS_CPUFREQ
158 Internal node to signify that the ARCH has CPUFREQ support
159 and that the relevant menu configurations are displayed for
162 config ARCH_HAS_CPU_IDLE_WAIT
165 config GENERIC_HWEIGHT
169 config GENERIC_CALIBRATE_DELAY
173 config ARCH_MAY_HAVE_PC_FDC
179 config NEED_DMA_MAP_STATE
182 config GENERIC_ISA_DMA
193 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
194 default DRAM_BASE if REMAP_VECTORS_TO_RAM
197 The base address of exception vectors.
199 config ARM_PATCH_PHYS_VIRT
200 bool "Patch physical to virtual translations at runtime" if EMBEDDED
202 depends on !XIP_KERNEL && MMU
203 depends on !ARCH_REALVIEW || !SPARSEMEM
205 Patch phys-to-virt and virt-to-phys translation functions at
206 boot and module load time according to the position of the
207 kernel in system memory.
209 This can only be used with non-XIP MMU kernels where the base
210 of physical memory is at a 16MB boundary.
212 Only disable this option if you know that you do not require
213 this feature (eg, building a kernel for a single machine) and
214 you need to shrink the kernel to the minimal size.
216 config NEED_MACH_MEMORY_H
219 Select this when mach/memory.h is required to provide special
220 definitions for this platform. The need for mach/memory.h should
221 be avoided when possible.
224 hex "Physical address of main memory" if MMU
225 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
226 default DRAM_BASE if !MMU
228 Please provide the physical address corresponding to the
229 location of main memory in your system.
235 source "init/Kconfig"
237 source "kernel/Kconfig.freezer"
242 bool "MMU-based Paged Memory Management Support"
245 Select if you want MMU-based virtualised addressing space
246 support by paged memory management. If unsure, say 'Y'.
249 # The "ARM system type" choice list is ordered alphabetically by option
250 # text. Please add new entries in the option alphabetic order.
253 prompt "ARM system type"
254 default ARCH_VERSATILE
256 config ARCH_INTEGRATOR
257 bool "ARM Ltd. Integrator family"
259 select ARCH_HAS_CPUFREQ
261 select HAVE_MACH_CLKDEV
264 select GENERIC_CLOCKEVENTS
265 select PLAT_VERSATILE
266 select PLAT_VERSATILE_FPGA_IRQ
267 select NEED_MACH_MEMORY_H
270 Support for ARM's Integrator platform.
273 bool "ARM Ltd. RealView family"
276 select HAVE_MACH_CLKDEV
278 select GENERIC_CLOCKEVENTS
279 select ARCH_WANT_OPTIONAL_GPIOLIB
280 select PLAT_VERSATILE
281 select PLAT_VERSATILE_CLCD
282 select ARM_TIMER_SP804
283 select GPIO_PL061 if GPIOLIB
284 select NEED_MACH_MEMORY_H
286 This enables support for ARM Ltd RealView boards.
288 config ARCH_VERSATILE
289 bool "ARM Ltd. Versatile family"
293 select HAVE_MACH_CLKDEV
295 select GENERIC_CLOCKEVENTS
296 select ARCH_WANT_OPTIONAL_GPIOLIB
297 select PLAT_VERSATILE
298 select PLAT_VERSATILE_CLCD
299 select PLAT_VERSATILE_FPGA_IRQ
300 select ARM_TIMER_SP804
302 This enables support for ARM Ltd Versatile board.
305 bool "ARM Ltd. Versatile Express family"
306 select ARCH_WANT_OPTIONAL_GPIOLIB
308 select ARM_TIMER_SP804
310 select HAVE_MACH_CLKDEV
311 select GENERIC_CLOCKEVENTS
313 select HAVE_PATA_PLATFORM
316 select PLAT_VERSATILE
317 select PLAT_VERSATILE_CLCD
319 This enables support for the ARM Ltd Versatile Express boards.
323 select ARCH_REQUIRE_GPIOLIB
327 This enables support for systems based on the Atmel AT91RM9200,
328 AT91SAM9 and AT91CAP9 processors.
331 bool "Broadcom BCMRING"
335 select ARM_TIMER_SP804
337 select GENERIC_CLOCKEVENTS
338 select ARCH_WANT_OPTIONAL_GPIOLIB
340 Support for Broadcom's BCMRing platform.
343 bool "Calxeda Highbank-based"
344 select ARCH_WANT_OPTIONAL_GPIOLIB
347 select ARM_TIMER_SP804
351 select GENERIC_CLOCKEVENTS
357 Support for the Calxeda Highbank SoC based boards.
360 bool "Cirrus Logic CLPS711x/EP721x-based"
362 select ARCH_USES_GETTIMEOFFSET
363 select NEED_MACH_MEMORY_H
365 Support for Cirrus Logic 711x/721x based boards.
368 bool "Cavium Networks CNS3XXX family"
370 select GENERIC_CLOCKEVENTS
372 select MIGHT_HAVE_CACHE_L2X0
373 select MIGHT_HAVE_PCI
374 select PCI_DOMAINS if PCI
376 Support for Cavium Networks CNS3XXX platform.
379 bool "Cortina Systems Gemini"
381 select ARCH_REQUIRE_GPIOLIB
382 select ARCH_USES_GETTIMEOFFSET
384 Support for the Cortina Systems Gemini family SoCs
387 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
390 select GENERIC_CLOCKEVENTS
392 select GENERIC_IRQ_CHIP
393 select MIGHT_HAVE_CACHE_L2X0
397 Support for CSR SiRFSoC ARM Cortex A9 Platform
404 select ARCH_USES_GETTIMEOFFSET
405 select NEED_MACH_MEMORY_H
407 This is an evaluation board for the StrongARM processor available
408 from Digital. It has limited hardware on-board, including an
409 Ethernet interface, two PCMCIA sockets, two serial ports and a
418 select ARCH_REQUIRE_GPIOLIB
419 select ARCH_HAS_HOLES_MEMORYMODEL
420 select ARCH_USES_GETTIMEOFFSET
421 select NEED_MACH_MEMORY_H
423 This enables support for the Cirrus EP93xx series of CPUs.
425 config ARCH_FOOTBRIDGE
429 select GENERIC_CLOCKEVENTS
431 select NEED_MACH_MEMORY_H
433 Support for systems based on the DC21285 companion chip
434 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
437 bool "Freescale MXC/iMX-based"
438 select GENERIC_CLOCKEVENTS
439 select ARCH_REQUIRE_GPIOLIB
442 select GENERIC_IRQ_CHIP
443 select MULTI_IRQ_HANDLER
445 Support for Freescale MXC/iMX-based family of processors
448 bool "Freescale MXS-based"
449 select GENERIC_CLOCKEVENTS
450 select ARCH_REQUIRE_GPIOLIB
453 select HAVE_CLK_PREPARE
455 Support for Freescale MXS-based family of processors
458 bool "Hilscher NetX based"
462 select GENERIC_CLOCKEVENTS
464 This enables support for systems based on the Hilscher NetX Soc
467 bool "Hynix HMS720x-based"
470 select ARCH_USES_GETTIMEOFFSET
472 This enables support for systems based on the Hynix HMS720x
480 select ARCH_SUPPORTS_MSI
482 select NEED_MACH_MEMORY_H
484 Support for Intel's IOP13XX (XScale) family of processors.
492 select ARCH_REQUIRE_GPIOLIB
494 Support for Intel's 80219 and IOP32X (XScale) family of
503 select ARCH_REQUIRE_GPIOLIB
505 Support for Intel's IOP33X (XScale) family of processors.
512 select ARCH_USES_GETTIMEOFFSET
513 select NEED_MACH_MEMORY_H
515 Support for Intel's IXP23xx (XScale) family of processors.
518 bool "IXP2400/2800-based"
522 select ARCH_USES_GETTIMEOFFSET
523 select NEED_MACH_MEMORY_H
525 Support for Intel's IXP2400/2800 (XScale) family of processors.
533 select GENERIC_CLOCKEVENTS
534 select MIGHT_HAVE_PCI
535 select DMABOUNCE if PCI
537 Support for Intel's IXP4XX (XScale) family of processors.
543 select ARCH_REQUIRE_GPIOLIB
544 select GENERIC_CLOCKEVENTS
547 Support for the Marvell Dove SoC 88AP510
550 bool "Marvell Kirkwood"
553 select ARCH_REQUIRE_GPIOLIB
554 select GENERIC_CLOCKEVENTS
557 Support for the following Marvell Kirkwood series SoCs:
558 88F6180, 88F6192 and 88F6281.
564 select ARCH_REQUIRE_GPIOLIB
567 select USB_ARCH_HAS_OHCI
569 select GENERIC_CLOCKEVENTS
571 Support for the NXP LPC32XX family of processors
574 bool "Marvell MV78xx0"
577 select ARCH_REQUIRE_GPIOLIB
578 select GENERIC_CLOCKEVENTS
581 Support for the following Marvell MV78xx0 series SoCs:
589 select ARCH_REQUIRE_GPIOLIB
590 select GENERIC_CLOCKEVENTS
593 Support for the following Marvell Orion 5x series SoCs:
594 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
595 Orion-2 (5281), Orion-1-90 (6183).
598 bool "Marvell PXA168/910/MMP2"
600 select ARCH_REQUIRE_GPIOLIB
602 select GENERIC_CLOCKEVENTS
607 select GENERIC_ALLOCATOR
609 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
612 bool "Micrel/Kendin KS8695"
614 select ARCH_REQUIRE_GPIOLIB
615 select ARCH_USES_GETTIMEOFFSET
616 select NEED_MACH_MEMORY_H
618 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
619 System-on-Chip devices.
622 bool "Nuvoton W90X900 CPU"
624 select ARCH_REQUIRE_GPIOLIB
627 select GENERIC_CLOCKEVENTS
629 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
630 At present, the w90x900 has been renamed nuc900, regarding
631 the ARM series product line, you can login the following
632 link address to know more.
634 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
635 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
641 select GENERIC_CLOCKEVENTS
645 select MIGHT_HAVE_CACHE_L2X0
646 select ARCH_HAS_CPUFREQ
648 This enables support for NVIDIA Tegra based systems (Tegra APX,
649 Tegra 6xx and Tegra 2 series).
651 config ARCH_PICOXCELL
652 bool "Picochip picoXcell"
653 select ARCH_REQUIRE_GPIOLIB
654 select ARM_PATCH_PHYS_VIRT
658 select GENERIC_CLOCKEVENTS
665 This enables support for systems based on the Picochip picoXcell
666 family of Femtocell devices. The picoxcell support requires device tree
670 bool "Philips Nexperia PNX4008 Mobile"
673 select ARCH_USES_GETTIMEOFFSET
675 This enables support for Philips PNX4008 mobile platform.
678 bool "PXA2xx/PXA3xx-based"
681 select ARCH_HAS_CPUFREQ
684 select ARCH_REQUIRE_GPIOLIB
685 select GENERIC_CLOCKEVENTS
691 select MULTI_IRQ_HANDLER
692 select ARM_CPU_SUSPEND if PM
695 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
700 select GENERIC_CLOCKEVENTS
701 select ARCH_REQUIRE_GPIOLIB
704 Support for Qualcomm MSM/QSD based systems. This runs on the
705 apps processor of the MSM/QSD and depends on a shared memory
706 interface to the modem processor which runs the baseband
707 stack and controls some vital subsystems
708 (clock and power control, etc).
711 bool "Renesas SH-Mobile / R-Mobile"
714 select HAVE_MACH_CLKDEV
716 select GENERIC_CLOCKEVENTS
717 select MIGHT_HAVE_CACHE_L2X0
720 select MULTI_IRQ_HANDLER
721 select PM_GENERIC_DOMAINS if PM
722 select NEED_MACH_MEMORY_H
724 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
731 select ARCH_MAY_HAVE_PC_FDC
732 select HAVE_PATA_PLATFORM
735 select ARCH_SPARSEMEM_ENABLE
736 select ARCH_USES_GETTIMEOFFSET
738 select NEED_MACH_MEMORY_H
740 On the Acorn Risc-PC, Linux can support the internal IDE disk and
741 CD-ROM interface, serial and parallel port, and the floppy drive.
748 select ARCH_SPARSEMEM_ENABLE
750 select ARCH_HAS_CPUFREQ
752 select GENERIC_CLOCKEVENTS
755 select ARCH_REQUIRE_GPIOLIB
757 select NEED_MACH_MEMORY_H
759 Support for StrongARM 11x0 based boards.
762 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
764 select ARCH_HAS_CPUFREQ
767 select ARCH_USES_GETTIMEOFFSET
768 select HAVE_S3C2410_I2C if I2C
770 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
771 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
772 the Samsung SMDK2410 development board (and derivatives).
774 Note, the S3C2416 and the S3C2450 are so close that they even share
775 the same SoC ID code. This means that there is no separate machine
776 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
779 bool "Samsung S3C64XX"
787 select ARCH_USES_GETTIMEOFFSET
788 select ARCH_HAS_CPUFREQ
789 select ARCH_REQUIRE_GPIOLIB
790 select SAMSUNG_CLKSRC
791 select SAMSUNG_IRQ_VIC_TIMER
792 select S3C_GPIO_TRACK
794 select USB_ARCH_HAS_OHCI
795 select SAMSUNG_GPIOLIB_4BIT
796 select HAVE_S3C2410_I2C if I2C
797 select HAVE_S3C2410_WATCHDOG if WATCHDOG
799 Samsung S3C64XX series based systems
802 bool "Samsung S5P6440 S5P6450"
808 select HAVE_S3C2410_WATCHDOG if WATCHDOG
809 select GENERIC_CLOCKEVENTS
810 select HAVE_S3C2410_I2C if I2C
811 select HAVE_S3C_RTC if RTC_CLASS
813 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
817 bool "Samsung S5PC100"
822 select ARM_L1_CACHE_SHIFT_6
823 select ARCH_USES_GETTIMEOFFSET
824 select HAVE_S3C2410_I2C if I2C
825 select HAVE_S3C_RTC if RTC_CLASS
826 select HAVE_S3C2410_WATCHDOG if WATCHDOG
828 Samsung S5PC100 series based systems
831 bool "Samsung S5PV210/S5PC110"
833 select ARCH_SPARSEMEM_ENABLE
834 select ARCH_HAS_HOLES_MEMORYMODEL
839 select ARM_L1_CACHE_SHIFT_6
840 select ARCH_HAS_CPUFREQ
841 select GENERIC_CLOCKEVENTS
842 select HAVE_S3C2410_I2C if I2C
843 select HAVE_S3C_RTC if RTC_CLASS
844 select HAVE_S3C2410_WATCHDOG if WATCHDOG
845 select NEED_MACH_MEMORY_H
847 Samsung S5PV210/S5PC110 series based systems
850 bool "SAMSUNG EXYNOS"
852 select ARCH_SPARSEMEM_ENABLE
853 select ARCH_HAS_HOLES_MEMORYMODEL
857 select ARCH_HAS_CPUFREQ
858 select GENERIC_CLOCKEVENTS
859 select HAVE_S3C_RTC if RTC_CLASS
860 select HAVE_S3C2410_I2C if I2C
861 select HAVE_S3C2410_WATCHDOG if WATCHDOG
862 select NEED_MACH_MEMORY_H
864 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
873 select ARCH_USES_GETTIMEOFFSET
874 select NEED_MACH_MEMORY_H
876 Support for the StrongARM based Digital DNARD machine, also known
877 as "Shark" (<http://www.shark-linux.de/shark.html>).
880 bool "ST-Ericsson U300 Series"
886 select ARM_PATCH_PHYS_VIRT
888 select GENERIC_CLOCKEVENTS
890 select HAVE_MACH_CLKDEV
892 select ARCH_REQUIRE_GPIOLIB
894 Support for ST-Ericsson U300 series mobile platforms.
897 bool "ST-Ericsson U8500 Series"
900 select GENERIC_CLOCKEVENTS
902 select ARCH_REQUIRE_GPIOLIB
903 select ARCH_HAS_CPUFREQ
905 select MIGHT_HAVE_CACHE_L2X0
907 Support for ST-Ericsson's Ux500 architecture
910 bool "STMicroelectronics Nomadik"
915 select GENERIC_CLOCKEVENTS
916 select MIGHT_HAVE_CACHE_L2X0
917 select ARCH_REQUIRE_GPIOLIB
919 Support for the Nomadik platform by ST-Ericsson
923 select GENERIC_CLOCKEVENTS
924 select ARCH_REQUIRE_GPIOLIB
928 select GENERIC_ALLOCATOR
929 select GENERIC_IRQ_CHIP
930 select ARCH_HAS_HOLES_MEMORYMODEL
932 Support for TI's DaVinci platform.
937 select ARCH_REQUIRE_GPIOLIB
938 select ARCH_HAS_CPUFREQ
940 select GENERIC_CLOCKEVENTS
941 select ARCH_HAS_HOLES_MEMORYMODEL
943 Support for TI's OMAP platform (OMAP1/2/3/4).
948 select ARCH_REQUIRE_GPIOLIB
951 select GENERIC_CLOCKEVENTS
954 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
957 bool "VIA/WonderMedia 85xx"
960 select ARCH_HAS_CPUFREQ
961 select GENERIC_CLOCKEVENTS
962 select ARCH_REQUIRE_GPIOLIB
965 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
968 bool "Xilinx Zynq ARM Cortex A9 Platform"
970 select GENERIC_CLOCKEVENTS
975 select MIGHT_HAVE_CACHE_L2X0
978 Support for Xilinx Zynq ARM Cortex A9 Platform
982 # This is sorted alphabetically by mach-* pathname. However, plat-*
983 # Kconfigs may be included either alphabetically (according to the
984 # plat- suffix) or along side the corresponding mach-* source.
986 source "arch/arm/mach-at91/Kconfig"
988 source "arch/arm/mach-bcmring/Kconfig"
990 source "arch/arm/mach-clps711x/Kconfig"
992 source "arch/arm/mach-cns3xxx/Kconfig"
994 source "arch/arm/mach-davinci/Kconfig"
996 source "arch/arm/mach-dove/Kconfig"
998 source "arch/arm/mach-ep93xx/Kconfig"
1000 source "arch/arm/mach-footbridge/Kconfig"
1002 source "arch/arm/mach-gemini/Kconfig"
1004 source "arch/arm/mach-h720x/Kconfig"
1006 source "arch/arm/mach-integrator/Kconfig"
1008 source "arch/arm/mach-iop32x/Kconfig"
1010 source "arch/arm/mach-iop33x/Kconfig"
1012 source "arch/arm/mach-iop13xx/Kconfig"
1014 source "arch/arm/mach-ixp4xx/Kconfig"
1016 source "arch/arm/mach-ixp2000/Kconfig"
1018 source "arch/arm/mach-ixp23xx/Kconfig"
1020 source "arch/arm/mach-kirkwood/Kconfig"
1022 source "arch/arm/mach-ks8695/Kconfig"
1024 source "arch/arm/mach-lpc32xx/Kconfig"
1026 source "arch/arm/mach-msm/Kconfig"
1028 source "arch/arm/mach-mv78xx0/Kconfig"
1030 source "arch/arm/plat-mxc/Kconfig"
1032 source "arch/arm/mach-mxs/Kconfig"
1034 source "arch/arm/mach-netx/Kconfig"
1036 source "arch/arm/mach-nomadik/Kconfig"
1037 source "arch/arm/plat-nomadik/Kconfig"
1039 source "arch/arm/plat-omap/Kconfig"
1041 source "arch/arm/mach-omap1/Kconfig"
1043 source "arch/arm/mach-omap2/Kconfig"
1045 source "arch/arm/mach-orion5x/Kconfig"
1047 source "arch/arm/mach-pxa/Kconfig"
1048 source "arch/arm/plat-pxa/Kconfig"
1050 source "arch/arm/mach-mmp/Kconfig"
1052 source "arch/arm/mach-realview/Kconfig"
1054 source "arch/arm/mach-sa1100/Kconfig"
1056 source "arch/arm/plat-samsung/Kconfig"
1057 source "arch/arm/plat-s3c24xx/Kconfig"
1058 source "arch/arm/plat-s5p/Kconfig"
1060 source "arch/arm/plat-spear/Kconfig"
1063 source "arch/arm/mach-s3c2410/Kconfig"
1064 source "arch/arm/mach-s3c2412/Kconfig"
1065 source "arch/arm/mach-s3c2416/Kconfig"
1066 source "arch/arm/mach-s3c2440/Kconfig"
1067 source "arch/arm/mach-s3c2443/Kconfig"
1071 source "arch/arm/mach-s3c64xx/Kconfig"
1074 source "arch/arm/mach-s5p64x0/Kconfig"
1076 source "arch/arm/mach-s5pc100/Kconfig"
1078 source "arch/arm/mach-s5pv210/Kconfig"
1080 source "arch/arm/mach-exynos/Kconfig"
1082 source "arch/arm/mach-shmobile/Kconfig"
1084 source "arch/arm/mach-tegra/Kconfig"
1086 source "arch/arm/mach-u300/Kconfig"
1088 source "arch/arm/mach-ux500/Kconfig"
1090 source "arch/arm/mach-versatile/Kconfig"
1092 source "arch/arm/mach-vexpress/Kconfig"
1093 source "arch/arm/plat-versatile/Kconfig"
1095 source "arch/arm/mach-vt8500/Kconfig"
1097 source "arch/arm/mach-w90x900/Kconfig"
1099 # Definitions to make life easier
1105 select GENERIC_CLOCKEVENTS
1110 select GENERIC_IRQ_CHIP
1115 config PLAT_VERSATILE
1118 config ARM_TIMER_SP804
1122 source arch/arm/mm/Kconfig
1126 default 16 if ARCH_EP93XX
1130 bool "Enable iWMMXt support"
1131 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1132 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1134 Enable support for iWMMXt context switching at run time if
1135 running on a CPU that supports it.
1139 depends on CPU_XSCALE
1143 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1144 (!ARCH_OMAP3 || OMAP3_EMU)
1148 config MULTI_IRQ_HANDLER
1151 Allow each machine to specify it's own IRQ handler at run time.
1154 source "arch/arm/Kconfig-nommu"
1157 config ARM_ERRATA_411920
1158 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1159 depends on CPU_V6 || CPU_V6K
1161 Invalidation of the Instruction Cache operation can
1162 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1163 It does not affect the MPCore. This option enables the ARM Ltd.
1164 recommended workaround.
1166 config ARM_ERRATA_430973
1167 bool "ARM errata: Stale prediction on replaced interworking branch"
1170 This option enables the workaround for the 430973 Cortex-A8
1171 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1172 interworking branch is replaced with another code sequence at the
1173 same virtual address, whether due to self-modifying code or virtual
1174 to physical address re-mapping, Cortex-A8 does not recover from the
1175 stale interworking branch prediction. This results in Cortex-A8
1176 executing the new code sequence in the incorrect ARM or Thumb state.
1177 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1178 and also flushes the branch target cache at every context switch.
1179 Note that setting specific bits in the ACTLR register may not be
1180 available in non-secure mode.
1182 config ARM_ERRATA_458693
1183 bool "ARM errata: Processor deadlock when a false hazard is created"
1186 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1187 erratum. For very specific sequences of memory operations, it is
1188 possible for a hazard condition intended for a cache line to instead
1189 be incorrectly associated with a different cache line. This false
1190 hazard might then cause a processor deadlock. The workaround enables
1191 the L1 caching of the NEON accesses and disables the PLD instruction
1192 in the ACTLR register. Note that setting specific bits in the ACTLR
1193 register may not be available in non-secure mode.
1195 config ARM_ERRATA_460075
1196 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1199 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1200 erratum. Any asynchronous access to the L2 cache may encounter a
1201 situation in which recent store transactions to the L2 cache are lost
1202 and overwritten with stale memory contents from external memory. The
1203 workaround disables the write-allocate mode for the L2 cache via the
1204 ACTLR register. Note that setting specific bits in the ACTLR register
1205 may not be available in non-secure mode.
1207 config ARM_ERRATA_742230
1208 bool "ARM errata: DMB operation may be faulty"
1209 depends on CPU_V7 && SMP
1211 This option enables the workaround for the 742230 Cortex-A9
1212 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1213 between two write operations may not ensure the correct visibility
1214 ordering of the two writes. This workaround sets a specific bit in
1215 the diagnostic register of the Cortex-A9 which causes the DMB
1216 instruction to behave as a DSB, ensuring the correct behaviour of
1219 config ARM_ERRATA_742231
1220 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1221 depends on CPU_V7 && SMP
1223 This option enables the workaround for the 742231 Cortex-A9
1224 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1225 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1226 accessing some data located in the same cache line, may get corrupted
1227 data due to bad handling of the address hazard when the line gets
1228 replaced from one of the CPUs at the same time as another CPU is
1229 accessing it. This workaround sets specific bits in the diagnostic
1230 register of the Cortex-A9 which reduces the linefill issuing
1231 capabilities of the processor.
1233 config PL310_ERRATA_588369
1234 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1235 depends on CACHE_L2X0
1237 The PL310 L2 cache controller implements three types of Clean &
1238 Invalidate maintenance operations: by Physical Address
1239 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1240 They are architecturally defined to behave as the execution of a
1241 clean operation followed immediately by an invalidate operation,
1242 both performing to the same memory location. This functionality
1243 is not correctly implemented in PL310 as clean lines are not
1244 invalidated as a result of these operations.
1246 config ARM_ERRATA_720789
1247 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1250 This option enables the workaround for the 720789 Cortex-A9 (prior to
1251 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1252 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1253 As a consequence of this erratum, some TLB entries which should be
1254 invalidated are not, resulting in an incoherency in the system page
1255 tables. The workaround changes the TLB flushing routines to invalidate
1256 entries regardless of the ASID.
1258 config PL310_ERRATA_727915
1259 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1260 depends on CACHE_L2X0
1262 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1263 operation (offset 0x7FC). This operation runs in background so that
1264 PL310 can handle normal accesses while it is in progress. Under very
1265 rare circumstances, due to this erratum, write data can be lost when
1266 PL310 treats a cacheable write transaction during a Clean &
1267 Invalidate by Way operation.
1269 config ARM_ERRATA_743622
1270 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1273 This option enables the workaround for the 743622 Cortex-A9
1274 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1275 optimisation in the Cortex-A9 Store Buffer may lead to data
1276 corruption. This workaround sets a specific bit in the diagnostic
1277 register of the Cortex-A9 which disables the Store Buffer
1278 optimisation, preventing the defect from occurring. This has no
1279 visible impact on the overall performance or power consumption of the
1282 config ARM_ERRATA_751472
1283 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1286 This option enables the workaround for the 751472 Cortex-A9 (prior
1287 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1288 completion of a following broadcasted operation if the second
1289 operation is received by a CPU before the ICIALLUIS has completed,
1290 potentially leading to corrupted entries in the cache or TLB.
1292 config PL310_ERRATA_753970
1293 bool "PL310 errata: cache sync operation may be faulty"
1294 depends on CACHE_PL310
1296 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1298 Under some condition the effect of cache sync operation on
1299 the store buffer still remains when the operation completes.
1300 This means that the store buffer is always asked to drain and
1301 this prevents it from merging any further writes. The workaround
1302 is to replace the normal offset of cache sync operation (0x730)
1303 by another offset targeting an unmapped PL310 register 0x740.
1304 This has the same effect as the cache sync operation: store buffer
1305 drain and waiting for all buffers empty.
1307 config ARM_ERRATA_754322
1308 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1311 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1312 r3p*) erratum. A speculative memory access may cause a page table walk
1313 which starts prior to an ASID switch but completes afterwards. This
1314 can populate the micro-TLB with a stale entry which may be hit with
1315 the new ASID. This workaround places two dsb instructions in the mm
1316 switching code so that no page table walks can cross the ASID switch.
1318 config ARM_ERRATA_754327
1319 bool "ARM errata: no automatic Store Buffer drain"
1320 depends on CPU_V7 && SMP
1322 This option enables the workaround for the 754327 Cortex-A9 (prior to
1323 r2p0) erratum. The Store Buffer does not have any automatic draining
1324 mechanism and therefore a livelock may occur if an external agent
1325 continuously polls a memory location waiting to observe an update.
1326 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1327 written polling loops from denying visibility of updates to memory.
1329 config ARM_ERRATA_364296
1330 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1331 depends on CPU_V6 && !SMP
1333 This options enables the workaround for the 364296 ARM1136
1334 r0p2 erratum (possible cache data corruption with
1335 hit-under-miss enabled). It sets the undocumented bit 31 in
1336 the auxiliary control register and the FI bit in the control
1337 register, thus disabling hit-under-miss without putting the
1338 processor into full low interrupt latency mode. ARM11MPCore
1341 config ARM_ERRATA_764369
1342 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1343 depends on CPU_V7 && SMP
1345 This option enables the workaround for erratum 764369
1346 affecting Cortex-A9 MPCore with two or more processors (all
1347 current revisions). Under certain timing circumstances, a data
1348 cache line maintenance operation by MVA targeting an Inner
1349 Shareable memory region may fail to proceed up to either the
1350 Point of Coherency or to the Point of Unification of the
1351 system. This workaround adds a DSB instruction before the
1352 relevant cache maintenance functions and sets a specific bit
1353 in the diagnostic control register of the SCU.
1355 config PL310_ERRATA_769419
1356 bool "PL310 errata: no automatic Store Buffer drain"
1357 depends on CACHE_L2X0
1359 On revisions of the PL310 prior to r3p2, the Store Buffer does
1360 not automatically drain. This can cause normal, non-cacheable
1361 writes to be retained when the memory system is idle, leading
1362 to suboptimal I/O performance for drivers using coherent DMA.
1363 This option adds a write barrier to the cpu_idle loop so that,
1364 on systems with an outer cache, the store buffer is drained
1369 source "arch/arm/common/Kconfig"
1379 Find out whether you have ISA slots on your motherboard. ISA is the
1380 name of a bus system, i.e. the way the CPU talks to the other stuff
1381 inside your box. Other bus systems are PCI, EISA, MicroChannel
1382 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1383 newer boards don't support it. If you have ISA, say Y, otherwise N.
1385 # Select ISA DMA controller support
1390 # Select ISA DMA interface
1395 bool "PCI support" if MIGHT_HAVE_PCI
1397 Find out whether you have a PCI motherboard. PCI is the name of a
1398 bus system, i.e. the way the CPU talks to the other stuff inside
1399 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1400 VESA. If you have PCI, say Y, otherwise N.
1406 config PCI_NANOENGINE
1407 bool "BSE nanoEngine PCI support"
1408 depends on SA1100_NANOENGINE
1410 Enable PCI on the BSE nanoEngine board.
1415 # Select the host bridge type
1416 config PCI_HOST_VIA82C505
1418 depends on PCI && ARCH_SHARK
1421 config PCI_HOST_ITE8152
1423 depends on PCI && MACH_ARMCORE
1427 source "drivers/pci/Kconfig"
1429 source "drivers/pcmcia/Kconfig"
1433 menu "Kernel Features"
1435 source "kernel/time/Kconfig"
1440 This option should be selected by machines which have an SMP-
1443 The only effect of this option is to make the SMP-related
1444 options available to the user for configuration.
1447 bool "Symmetric Multi-Processing"
1448 depends on CPU_V6K || CPU_V7
1449 depends on GENERIC_CLOCKEVENTS
1452 select USE_GENERIC_SMP_HELPERS
1453 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1455 This enables support for systems with more than one CPU. If you have
1456 a system with only one CPU, like most personal computers, say N. If
1457 you have a system with more than one CPU, say Y.
1459 If you say N here, the kernel will run on single and multiprocessor
1460 machines, but will use only one CPU of a multiprocessor machine. If
1461 you say Y here, the kernel will run on many, but not all, single
1462 processor machines. On a single processor machine, the kernel will
1463 run faster if you say N here.
1465 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1466 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1467 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1469 If you don't know what to do here, say N.
1472 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1473 depends on EXPERIMENTAL
1474 depends on SMP && !XIP_KERNEL
1477 SMP kernels contain instructions which fail on non-SMP processors.
1478 Enabling this option allows the kernel to modify itself to make
1479 these instructions safe. Disabling it allows about 1K of space
1482 If you don't know what to do here, say Y.
1484 config ARM_CPU_TOPOLOGY
1485 bool "Support cpu topology definition"
1486 depends on SMP && CPU_V7
1489 Support ARM cpu topology definition. The MPIDR register defines
1490 affinity between processors which is then used to describe the cpu
1491 topology of an ARM System.
1494 bool "Multi-core scheduler support"
1495 depends on ARM_CPU_TOPOLOGY
1497 Multi-core scheduler support improves the CPU scheduler's decision
1498 making when dealing with multi-core CPU chips at a cost of slightly
1499 increased overhead in some places. If unsure say N here.
1502 bool "SMT scheduler support"
1503 depends on ARM_CPU_TOPOLOGY
1505 Improves the CPU scheduler's decision making when dealing with
1506 MultiThreading at a cost of slightly increased overhead in some
1507 places. If unsure say N here.
1512 This option enables support for the ARM system coherency unit
1519 This options enables support for the ARM timer and watchdog unit
1522 prompt "Memory split"
1525 Select the desired split between kernel and user memory.
1527 If you are not absolutely sure what you are doing, leave this
1531 bool "3G/1G user/kernel split"
1533 bool "2G/2G user/kernel split"
1535 bool "1G/3G user/kernel split"
1540 default 0x40000000 if VMSPLIT_1G
1541 default 0x80000000 if VMSPLIT_2G
1545 int "Maximum number of CPUs (2-32)"
1551 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1552 depends on SMP && HOTPLUG && EXPERIMENTAL
1554 Say Y here to experiment with turning CPUs off and on. CPUs
1555 can be controlled through /sys/devices/system/cpu.
1558 bool "Use local timer interrupts"
1561 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1563 Enable support for local timers on SMP platforms, rather then the
1564 legacy IPI broadcast method. Local timers allows the system
1565 accounting to be spread across the timer interval, preventing a
1566 "thundering herd" at every timer tick.
1570 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1571 default 350 if ARCH_U8500
1574 Maximum number of GPIOs in the system.
1576 If unsure, leave the default value.
1578 source kernel/Kconfig.preempt
1582 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1583 ARCH_S5PV210 || ARCH_EXYNOS4
1584 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1585 default AT91_TIMER_HZ if ARCH_AT91
1586 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1589 config THUMB2_KERNEL
1590 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1591 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1593 select ARM_ASM_UNIFIED
1596 By enabling this option, the kernel will be compiled in
1597 Thumb-2 mode. A compiler/assembler that understand the unified
1598 ARM-Thumb syntax is needed.
1602 config THUMB2_AVOID_R_ARM_THM_JUMP11
1603 bool "Work around buggy Thumb-2 short branch relocations in gas"
1604 depends on THUMB2_KERNEL && MODULES
1607 Various binutils versions can resolve Thumb-2 branches to
1608 locally-defined, preemptible global symbols as short-range "b.n"
1609 branch instructions.
1611 This is a problem, because there's no guarantee the final
1612 destination of the symbol, or any candidate locations for a
1613 trampoline, are within range of the branch. For this reason, the
1614 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1615 relocation in modules at all, and it makes little sense to add
1618 The symptom is that the kernel fails with an "unsupported
1619 relocation" error when loading some modules.
1621 Until fixed tools are available, passing
1622 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1623 code which hits this problem, at the cost of a bit of extra runtime
1624 stack usage in some cases.
1626 The problem is described in more detail at:
1627 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1629 Only Thumb-2 kernels are affected.
1631 Unless you are sure your tools don't have this problem, say Y.
1633 config ARM_ASM_UNIFIED
1637 bool "Use the ARM EABI to compile the kernel"
1639 This option allows for the kernel to be compiled using the latest
1640 ARM ABI (aka EABI). This is only useful if you are using a user
1641 space environment that is also compiled with EABI.
1643 Since there are major incompatibilities between the legacy ABI and
1644 EABI, especially with regard to structure member alignment, this
1645 option also changes the kernel syscall calling convention to
1646 disambiguate both ABIs and allow for backward compatibility support
1647 (selected with CONFIG_OABI_COMPAT).
1649 To use this you need GCC version 4.0.0 or later.
1652 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1653 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1656 This option preserves the old syscall interface along with the
1657 new (ARM EABI) one. It also provides a compatibility layer to
1658 intercept syscalls that have structure arguments which layout
1659 in memory differs between the legacy ABI and the new ARM EABI
1660 (only for non "thumb" binaries). This option adds a tiny
1661 overhead to all syscalls and produces a slightly larger kernel.
1662 If you know you'll be using only pure EABI user space then you
1663 can say N here. If this option is not selected and you attempt
1664 to execute a legacy ABI binary then the result will be
1665 UNPREDICTABLE (in fact it can be predicted that it won't work
1666 at all). If in doubt say Y.
1668 config ARCH_HAS_HOLES_MEMORYMODEL
1671 config ARCH_SPARSEMEM_ENABLE
1674 config ARCH_SPARSEMEM_DEFAULT
1675 def_bool ARCH_SPARSEMEM_ENABLE
1677 config ARCH_SELECT_MEMORY_MODEL
1678 def_bool ARCH_SPARSEMEM_ENABLE
1680 config HAVE_ARCH_PFN_VALID
1681 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1684 bool "High Memory Support"
1687 The address space of ARM processors is only 4 Gigabytes large
1688 and it has to accommodate user address space, kernel address
1689 space as well as some memory mapped IO. That means that, if you
1690 have a large amount of physical memory and/or IO, not all of the
1691 memory can be "permanently mapped" by the kernel. The physical
1692 memory that is not permanently mapped is called "high memory".
1694 Depending on the selected kernel/user memory split, minimum
1695 vmalloc space and actual amount of RAM, you may not need this
1696 option which should result in a slightly faster kernel.
1701 bool "Allocate 2nd-level pagetables from highmem"
1704 config HW_PERF_EVENTS
1705 bool "Enable hardware performance counter support for perf events"
1706 depends on PERF_EVENTS && CPU_HAS_PMU
1709 Enable hardware performance counter support for perf events. If
1710 disabled, perf events will use software events only.
1714 config FORCE_MAX_ZONEORDER
1715 int "Maximum zone order" if ARCH_SHMOBILE
1716 range 11 64 if ARCH_SHMOBILE
1717 default "9" if SA1111
1720 The kernel memory allocator divides physically contiguous memory
1721 blocks into "zones", where each zone is a power of two number of
1722 pages. This option selects the largest power of two that the kernel
1723 keeps in the memory allocator. If you need to allocate very large
1724 blocks of physically contiguous memory, then you may need to
1725 increase this value.
1727 This config option is actually maximum order plus one. For example,
1728 a value of 11 means that the largest free memory block is 2^10 pages.
1731 bool "Timer and CPU usage LEDs"
1732 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1733 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1734 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1735 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1736 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1737 ARCH_AT91 || ARCH_DAVINCI || \
1738 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1740 If you say Y here, the LEDs on your machine will be used
1741 to provide useful information about your current system status.
1743 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1744 be able to select which LEDs are active using the options below. If
1745 you are compiling a kernel for the EBSA-110 or the LART however, the
1746 red LED will simply flash regularly to indicate that the system is
1747 still functional. It is safe to say Y here if you have a CATS
1748 system, but the driver will do nothing.
1751 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1752 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1753 || MACH_OMAP_PERSEUS2
1755 depends on !GENERIC_CLOCKEVENTS
1756 default y if ARCH_EBSA110
1758 If you say Y here, one of the system LEDs (the green one on the
1759 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1760 will flash regularly to indicate that the system is still
1761 operational. This is mainly useful to kernel hackers who are
1762 debugging unstable kernels.
1764 The LART uses the same LED for both Timer LED and CPU usage LED
1765 functions. You may choose to use both, but the Timer LED function
1766 will overrule the CPU usage LED.
1769 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1771 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1772 || MACH_OMAP_PERSEUS2
1775 If you say Y here, the red LED will be used to give a good real
1776 time indication of CPU usage, by lighting whenever the idle task
1777 is not currently executing.
1779 The LART uses the same LED for both Timer LED and CPU usage LED
1780 functions. You may choose to use both, but the Timer LED function
1781 will overrule the CPU usage LED.
1783 config ALIGNMENT_TRAP
1785 depends on CPU_CP15_MMU
1786 default y if !ARCH_EBSA110
1787 select HAVE_PROC_CPU if PROC_FS
1789 ARM processors cannot fetch/store information which is not
1790 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1791 address divisible by 4. On 32-bit ARM processors, these non-aligned
1792 fetch/store instructions will be emulated in software if you say
1793 here, which has a severe performance impact. This is necessary for
1794 correct operation of some network protocols. With an IP-only
1795 configuration it is safe to say N, otherwise say Y.
1797 config UACCESS_WITH_MEMCPY
1798 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1799 depends on MMU && EXPERIMENTAL
1800 default y if CPU_FEROCEON
1802 Implement faster copy_to_user and clear_user methods for CPU
1803 cores where a 8-word STM instruction give significantly higher
1804 memory write throughput than a sequence of individual 32bit stores.
1806 A possible side effect is a slight increase in scheduling latency
1807 between threads sharing the same address space if they invoke
1808 such copy operations with large buffers.
1810 However, if the CPU data cache is using a write-allocate mode,
1811 this option is unlikely to provide any performance gain.
1815 prompt "Enable seccomp to safely compute untrusted bytecode"
1817 This kernel feature is useful for number crunching applications
1818 that may need to compute untrusted bytecode during their
1819 execution. By using pipes or other transports made available to
1820 the process as file descriptors supporting the read/write
1821 syscalls, it's possible to isolate those applications in
1822 their own address space using seccomp. Once seccomp is
1823 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1824 and the task is only allowed to execute a few safe syscalls
1825 defined by each seccomp mode.
1827 config CC_STACKPROTECTOR
1828 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1829 depends on EXPERIMENTAL
1831 This option turns on the -fstack-protector GCC feature. This
1832 feature puts, at the beginning of functions, a canary value on
1833 the stack just before the return address, and validates
1834 the value just before actually returning. Stack based buffer
1835 overflows (that need to overwrite this return address) now also
1836 overwrite the canary, which gets detected and the attack is then
1837 neutralized via a kernel panic.
1838 This feature requires gcc version 4.2 or above.
1840 config DEPRECATED_PARAM_STRUCT
1841 bool "Provide old way to pass kernel parameters"
1843 This was deprecated in 2001 and announced to live on for 5 years.
1844 Some old boot loaders still use this way.
1851 bool "Flattened Device Tree support"
1853 select OF_EARLY_FLATTREE
1856 Include support for flattened device tree machine descriptions.
1858 # Compressed boot loader in ROM. Yes, we really want to ask about
1859 # TEXT and BSS so we preserve their values in the config files.
1860 config ZBOOT_ROM_TEXT
1861 hex "Compressed ROM boot loader base address"
1864 The physical address at which the ROM-able zImage is to be
1865 placed in the target. Platforms which normally make use of
1866 ROM-able zImage formats normally set this to a suitable
1867 value in their defconfig file.
1869 If ZBOOT_ROM is not enabled, this has no effect.
1871 config ZBOOT_ROM_BSS
1872 hex "Compressed ROM boot loader BSS address"
1875 The base address of an area of read/write memory in the target
1876 for the ROM-able zImage which must be available while the
1877 decompressor is running. It must be large enough to hold the
1878 entire decompressed kernel plus an additional 128 KiB.
1879 Platforms which normally make use of ROM-able zImage formats
1880 normally set this to a suitable value in their defconfig file.
1882 If ZBOOT_ROM is not enabled, this has no effect.
1885 bool "Compressed boot loader in ROM/flash"
1886 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1888 Say Y here if you intend to execute your compressed kernel image
1889 (zImage) directly from ROM or flash. If unsure, say N.
1892 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1893 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1894 default ZBOOT_ROM_NONE
1896 Include experimental SD/MMC loading code in the ROM-able zImage.
1897 With this enabled it is possible to write the the ROM-able zImage
1898 kernel image to an MMC or SD card and boot the kernel straight
1899 from the reset vector. At reset the processor Mask ROM will load
1900 the first part of the the ROM-able zImage which in turn loads the
1901 rest the kernel image to RAM.
1903 config ZBOOT_ROM_NONE
1904 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1906 Do not load image from SD or MMC
1908 config ZBOOT_ROM_MMCIF
1909 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1911 Load image from MMCIF hardware block.
1913 config ZBOOT_ROM_SH_MOBILE_SDHI
1914 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1916 Load image from SDHI hardware block
1920 config ARM_APPENDED_DTB
1921 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1922 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1924 With this option, the boot code will look for a device tree binary
1925 (DTB) appended to zImage
1926 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1928 This is meant as a backward compatibility convenience for those
1929 systems with a bootloader that can't be upgraded to accommodate
1930 the documented boot protocol using a device tree.
1932 Beware that there is very little in terms of protection against
1933 this option being confused by leftover garbage in memory that might
1934 look like a DTB header after a reboot if no actual DTB is appended
1935 to zImage. Do not leave this option active in a production kernel
1936 if you don't intend to always append a DTB. Proper passing of the
1937 location into r2 of a bootloader provided DTB is always preferable
1940 config ARM_ATAG_DTB_COMPAT
1941 bool "Supplement the appended DTB with traditional ATAG information"
1942 depends on ARM_APPENDED_DTB
1944 Some old bootloaders can't be updated to a DTB capable one, yet
1945 they provide ATAGs with memory configuration, the ramdisk address,
1946 the kernel cmdline string, etc. Such information is dynamically
1947 provided by the bootloader and can't always be stored in a static
1948 DTB. To allow a device tree enabled kernel to be used with such
1949 bootloaders, this option allows zImage to extract the information
1950 from the ATAG list and store it at run time into the appended DTB.
1953 string "Default kernel command string"
1956 On some architectures (EBSA110 and CATS), there is currently no way
1957 for the boot loader to pass arguments to the kernel. For these
1958 architectures, you should supply some command-line options at build
1959 time by entering them here. As a minimum, you should specify the
1960 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1963 prompt "Kernel command line type" if CMDLINE != ""
1964 default CMDLINE_FROM_BOOTLOADER
1966 config CMDLINE_FROM_BOOTLOADER
1967 bool "Use bootloader kernel arguments if available"
1969 Uses the command-line options passed by the boot loader. If
1970 the boot loader doesn't provide any, the default kernel command
1971 string provided in CMDLINE will be used.
1973 config CMDLINE_EXTEND
1974 bool "Extend bootloader kernel arguments"
1976 The command-line arguments provided by the boot loader will be
1977 appended to the default kernel command string.
1979 config CMDLINE_FORCE
1980 bool "Always use the default kernel command string"
1982 Always use the default kernel command string, even if the boot
1983 loader passes other arguments to the kernel.
1984 This is useful if you cannot or don't want to change the
1985 command-line options your boot loader passes to the kernel.
1989 bool "Kernel Execute-In-Place from ROM"
1990 depends on !ZBOOT_ROM && !ARM_LPAE
1992 Execute-In-Place allows the kernel to run from non-volatile storage
1993 directly addressable by the CPU, such as NOR flash. This saves RAM
1994 space since the text section of the kernel is not loaded from flash
1995 to RAM. Read-write sections, such as the data section and stack,
1996 are still copied to RAM. The XIP kernel is not compressed since
1997 it has to run directly from flash, so it will take more space to
1998 store it. The flash address used to link the kernel object files,
1999 and for storing it, is configuration dependent. Therefore, if you
2000 say Y here, you must know the proper physical address where to
2001 store the kernel image depending on your own flash memory usage.
2003 Also note that the make target becomes "make xipImage" rather than
2004 "make zImage" or "make Image". The final kernel binary to put in
2005 ROM memory will be arch/arm/boot/xipImage.
2009 config XIP_PHYS_ADDR
2010 hex "XIP Kernel Physical Location"
2011 depends on XIP_KERNEL
2012 default "0x00080000"
2014 This is the physical address in your flash memory the kernel will
2015 be linked for and stored to. This address is dependent on your
2019 bool "Kexec system call (EXPERIMENTAL)"
2020 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2022 kexec is a system call that implements the ability to shutdown your
2023 current kernel, and to start another kernel. It is like a reboot
2024 but it is independent of the system firmware. And like a reboot
2025 you can start any kernel with it, not just Linux.
2027 It is an ongoing process to be certain the hardware in a machine
2028 is properly shutdown, so do not be surprised if this code does not
2029 initially work for you. It may help to enable device hotplugging
2033 bool "Export atags in procfs"
2037 Should the atags used to boot the kernel be exported in an "atags"
2038 file in procfs. Useful with kexec.
2041 bool "Build kdump crash kernel (EXPERIMENTAL)"
2042 depends on EXPERIMENTAL
2044 Generate crash dump after being started by kexec. This should
2045 be normally only set in special crash dump kernels which are
2046 loaded in the main kernel with kexec-tools into a specially
2047 reserved region and then later executed after a crash by
2048 kdump/kexec. The crash dump kernel must be compiled to a
2049 memory address not used by the main kernel
2051 For more details see Documentation/kdump/kdump.txt
2053 config AUTO_ZRELADDR
2054 bool "Auto calculation of the decompressed kernel image address"
2055 depends on !ZBOOT_ROM && !ARCH_U300
2057 ZRELADDR is the physical address where the decompressed kernel
2058 image will be placed. If AUTO_ZRELADDR is selected, the address
2059 will be determined at run-time by masking the current IP with
2060 0xf8000000. This assumes the zImage being placed in the first 128MB
2061 from start of memory.
2065 menu "CPU Power Management"
2069 source "drivers/cpufreq/Kconfig"
2072 tristate "CPUfreq driver for i.MX CPUs"
2073 depends on ARCH_MXC && CPU_FREQ
2075 This enables the CPUfreq driver for i.MX CPUs.
2077 config CPU_FREQ_SA1100
2080 config CPU_FREQ_SA1110
2083 config CPU_FREQ_INTEGRATOR
2084 tristate "CPUfreq driver for ARM Integrator CPUs"
2085 depends on ARCH_INTEGRATOR && CPU_FREQ
2088 This enables the CPUfreq driver for ARM Integrator CPUs.
2090 For details, take a look at <file:Documentation/cpu-freq>.
2096 depends on CPU_FREQ && ARCH_PXA && PXA25x
2098 select CPU_FREQ_TABLE
2099 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2104 Internal configuration node for common cpufreq on Samsung SoC
2106 config CPU_FREQ_S3C24XX
2107 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2108 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
2111 This enables the CPUfreq driver for the Samsung S3C24XX family
2114 For details, take a look at <file:Documentation/cpu-freq>.
2118 config CPU_FREQ_S3C24XX_PLL
2119 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2120 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2122 Compile in support for changing the PLL frequency from the
2123 S3C24XX series CPUfreq driver. The PLL takes time to settle
2124 after a frequency change, so by default it is not enabled.
2126 This also means that the PLL tables for the selected CPU(s) will
2127 be built which may increase the size of the kernel image.
2129 config CPU_FREQ_S3C24XX_DEBUG
2130 bool "Debug CPUfreq Samsung driver core"
2131 depends on CPU_FREQ_S3C24XX
2133 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2135 config CPU_FREQ_S3C24XX_IODEBUG
2136 bool "Debug CPUfreq Samsung driver IO timing"
2137 depends on CPU_FREQ_S3C24XX
2139 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2141 config CPU_FREQ_S3C24XX_DEBUGFS
2142 bool "Export debugfs for CPUFreq"
2143 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2145 Export status information via debugfs.
2149 source "drivers/cpuidle/Kconfig"
2153 menu "Floating point emulation"
2155 comment "At least one emulation must be selected"
2158 bool "NWFPE math emulation"
2159 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2161 Say Y to include the NWFPE floating point emulator in the kernel.
2162 This is necessary to run most binaries. Linux does not currently
2163 support floating point hardware so you need to say Y here even if
2164 your machine has an FPA or floating point co-processor podule.
2166 You may say N here if you are going to load the Acorn FPEmulator
2167 early in the bootup.
2170 bool "Support extended precision"
2171 depends on FPE_NWFPE
2173 Say Y to include 80-bit support in the kernel floating-point
2174 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2175 Note that gcc does not generate 80-bit operations by default,
2176 so in most cases this option only enlarges the size of the
2177 floating point emulator without any good reason.
2179 You almost surely want to say N here.
2182 bool "FastFPE math emulation (EXPERIMENTAL)"
2183 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2185 Say Y here to include the FAST floating point emulator in the kernel.
2186 This is an experimental much faster emulator which now also has full
2187 precision for the mantissa. It does not support any exceptions.
2188 It is very simple, and approximately 3-6 times faster than NWFPE.
2190 It should be sufficient for most programs. It may be not suitable
2191 for scientific calculations, but you have to check this for yourself.
2192 If you do not feel you need a faster FP emulation you should better
2196 bool "VFP-format floating point maths"
2197 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2199 Say Y to include VFP support code in the kernel. This is needed
2200 if your hardware includes a VFP unit.
2202 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2203 release notes and additional status information.
2205 Say N if your target does not have VFP hardware.
2213 bool "Advanced SIMD (NEON) Extension support"
2214 depends on VFPv3 && CPU_V7
2216 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2221 menu "Userspace binary formats"
2223 source "fs/Kconfig.binfmt"
2226 tristate "RISC OS personality"
2229 Say Y here to include the kernel code necessary if you want to run
2230 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2231 experimental; if this sounds frightening, say N and sleep in peace.
2232 You can also say M here to compile this support as a module (which
2233 will be called arthur).
2237 menu "Power management options"
2239 source "kernel/power/Kconfig"
2241 config ARCH_SUSPEND_POSSIBLE
2242 depends on !ARCH_S5PC100
2243 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2244 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2247 config ARM_CPU_SUSPEND
2252 source "net/Kconfig"
2254 source "drivers/Kconfig"
2258 source "arch/arm/Kconfig.debug"
2260 source "security/Kconfig"
2262 source "crypto/Kconfig"
2264 source "lib/Kconfig"