4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_WANT_IPC_PARSE_VERSION
8 select BUILDTIME_EXTABLE_SORT if MMU
9 select CPU_PM if (SUSPEND || CPU_IDLE)
10 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
11 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
12 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
13 select GENERIC_IRQ_PROBE
14 select GENERIC_IRQ_SHOW
15 select GENERIC_PCI_IOMAP
16 select GENERIC_SMP_IDLE_THREAD
17 select GENERIC_STRNCPY_FROM_USER
18 select GENERIC_STRNLEN_USER
19 select HARDIRQS_SW_RESEND
21 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
23 select HAVE_ARCH_SECCOMP_FILTER
24 select HAVE_ARCH_TRACEHOOK
26 select HAVE_C_RECORDMCOUNT
27 select HAVE_DEBUG_KMEMLEAK
28 select HAVE_DMA_API_DEBUG
30 select HAVE_DMA_CONTIGUOUS if MMU
31 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
32 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
33 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
34 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
35 select HAVE_GENERIC_DMA_COHERENT
36 select HAVE_GENERIC_HARDIRQS
37 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
38 select HAVE_IDE if PCI || ISA || PCMCIA
39 select HAVE_KERNEL_GZIP
40 select HAVE_KERNEL_LZMA
41 select HAVE_KERNEL_LZO
43 select HAVE_KPROBES if !XIP_KERNEL
44 select HAVE_KRETPROBES if (HAVE_KPROBES)
46 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
47 select HAVE_PERF_EVENTS
48 select HAVE_REGS_AND_STACK_ACCESS_API
49 select HAVE_SYSCALL_TRACEPOINTS
52 select PERF_USE_VMALLOC
54 select SYS_SUPPORTS_APM_EMULATION
55 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
56 select MODULES_USE_ELF_REL
57 select CLONE_BACKWARDS
59 The ARM series is a line of low-power-consumption RISC chip designs
60 licensed by ARM Ltd and targeted at embedded applications and
61 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
62 manufactured, but legacy ARM-based PC hardware remains popular in
63 Europe. There is an ARM Linux project with a web page at
64 <http://www.arm.linux.org.uk/>.
66 config ARM_HAS_SG_CHAIN
69 config NEED_SG_DMA_LENGTH
72 config ARM_DMA_USE_IOMMU
74 select ARM_HAS_SG_CHAIN
75 select NEED_SG_DMA_LENGTH
83 config SYS_SUPPORTS_APM_EMULATION
91 select GENERIC_ALLOCATOR
102 The Extended Industry Standard Architecture (EISA) bus was
103 developed as an open alternative to the IBM MicroChannel bus.
105 The EISA bus provided some of the features of the IBM MicroChannel
106 bus while maintaining backward compatibility with cards made for
107 the older ISA bus. The EISA bus saw limited use between 1988 and
108 1995 when it was made obsolete by the PCI bus.
110 Say Y here if you are building a kernel for an EISA-based machine.
117 config STACKTRACE_SUPPORT
121 config HAVE_LATENCYTOP_SUPPORT
126 config LOCKDEP_SUPPORT
130 config TRACE_IRQFLAGS_SUPPORT
134 config RWSEM_GENERIC_SPINLOCK
138 config RWSEM_XCHGADD_ALGORITHM
141 config ARCH_HAS_ILOG2_U32
144 config ARCH_HAS_ILOG2_U64
147 config ARCH_HAS_CPUFREQ
150 Internal node to signify that the ARCH has CPUFREQ support
151 and that the relevant menu configurations are displayed for
154 config GENERIC_HWEIGHT
158 config GENERIC_CALIBRATE_DELAY
162 config ARCH_MAY_HAVE_PC_FDC
168 config NEED_DMA_MAP_STATE
171 config ARCH_HAS_DMA_SET_COHERENT_MASK
174 config GENERIC_ISA_DMA
180 config NEED_RET_TO_USER
188 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
189 default DRAM_BASE if REMAP_VECTORS_TO_RAM
192 The base address of exception vectors.
194 config ARM_PATCH_PHYS_VIRT
195 bool "Patch physical to virtual translations at runtime" if EMBEDDED
197 depends on !XIP_KERNEL && MMU
198 depends on !ARCH_REALVIEW || !SPARSEMEM
200 Patch phys-to-virt and virt-to-phys translation functions at
201 boot and module load time according to the position of the
202 kernel in system memory.
204 This can only be used with non-XIP MMU kernels where the base
205 of physical memory is at a 16MB boundary.
207 Only disable this option if you know that you do not require
208 this feature (eg, building a kernel for a single machine) and
209 you need to shrink the kernel to the minimal size.
211 config NEED_MACH_GPIO_H
214 Select this when mach/gpio.h is required to provide special
215 definitions for this platform. The need for mach/gpio.h should
216 be avoided when possible.
218 config NEED_MACH_IO_H
221 Select this when mach/io.h is required to provide special
222 definitions for this platform. The need for mach/io.h should
223 be avoided when possible.
225 config NEED_MACH_MEMORY_H
228 Select this when mach/memory.h is required to provide special
229 definitions for this platform. The need for mach/memory.h should
230 be avoided when possible.
233 hex "Physical address of main memory" if MMU
234 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
235 default DRAM_BASE if !MMU
237 Please provide the physical address corresponding to the
238 location of main memory in your system.
244 source "init/Kconfig"
246 source "kernel/Kconfig.freezer"
251 bool "MMU-based Paged Memory Management Support"
254 Select if you want MMU-based virtualised addressing space
255 support by paged memory management. If unsure, say 'Y'.
258 # The "ARM system type" choice list is ordered alphabetically by option
259 # text. Please add new entries in the option alphabetic order.
262 prompt "ARM system type"
263 default ARCH_VERSATILE if !MMU
264 default ARCH_MULTIPLATFORM if MMU
266 config ARCH_MULTIPLATFORM
267 bool "Allow multiple platforms to be selected"
269 select ARM_PATCH_PHYS_VIRT
272 select MULTI_IRQ_HANDLER
276 config ARCH_INTEGRATOR
277 bool "ARM Ltd. Integrator family"
278 select ARCH_HAS_CPUFREQ
281 select COMMON_CLK_VERSATILE
282 select GENERIC_CLOCKEVENTS
285 select MULTI_IRQ_HANDLER
286 select NEED_MACH_MEMORY_H
287 select PLAT_VERSATILE
289 select VERSATILE_FPGA_IRQ
291 Support for ARM's Integrator platform.
294 bool "ARM Ltd. RealView family"
295 select ARCH_WANT_OPTIONAL_GPIOLIB
297 select ARM_TIMER_SP804
299 select COMMON_CLK_VERSATILE
300 select GENERIC_CLOCKEVENTS
301 select GPIO_PL061 if GPIOLIB
303 select NEED_MACH_MEMORY_H
304 select PLAT_VERSATILE
305 select PLAT_VERSATILE_CLCD
307 This enables support for ARM Ltd RealView boards.
309 config ARCH_VERSATILE
310 bool "ARM Ltd. Versatile family"
311 select ARCH_WANT_OPTIONAL_GPIOLIB
313 select ARM_TIMER_SP804
316 select GENERIC_CLOCKEVENTS
317 select HAVE_MACH_CLKDEV
319 select PLAT_VERSATILE
320 select PLAT_VERSATILE_CLCD
321 select PLAT_VERSATILE_CLOCK
322 select VERSATILE_FPGA_IRQ
324 This enables support for ARM Ltd Versatile board.
328 select ARCH_REQUIRE_GPIOLIB
332 select NEED_MACH_GPIO_H
333 select NEED_MACH_IO_H if PCCARD
335 select PINCTRL_AT91 if USE_OF
337 This enables support for systems based on Atmel
338 AT91RM9200 and AT91SAM9* processors.
341 bool "Broadcom BCM2835 family"
342 select ARCH_REQUIRE_GPIOLIB
344 select ARM_ERRATA_411920
345 select ARM_TIMER_SP804
349 select GENERIC_CLOCKEVENTS
351 select MULTI_IRQ_HANDLER
353 select PINCTRL_BCM2835
357 This enables support for the Broadcom BCM2835 SoC. This SoC is
358 use in the Raspberry Pi, and Roku 2 devices.
361 bool "Cavium Networks CNS3XXX family"
364 select GENERIC_CLOCKEVENTS
365 select MIGHT_HAVE_CACHE_L2X0
366 select MIGHT_HAVE_PCI
367 select PCI_DOMAINS if PCI
369 Support for Cavium Networks CNS3XXX platform.
372 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
373 select ARCH_REQUIRE_GPIOLIB
378 select GENERIC_CLOCKEVENTS
379 select MULTI_IRQ_HANDLER
380 select NEED_MACH_MEMORY_H
383 Support for Cirrus Logic 711x/721x/731x based boards.
386 bool "Cortina Systems Gemini"
387 select ARCH_REQUIRE_GPIOLIB
388 select ARCH_USES_GETTIMEOFFSET
391 Support for the Cortina Systems Gemini family SoCs
395 select ARCH_REQUIRE_GPIOLIB
397 select GENERIC_CLOCKEVENTS
398 select GENERIC_IRQ_CHIP
399 select MIGHT_HAVE_CACHE_L2X0
405 Support for CSR SiRFprimaII/Marco/Polo platforms
409 select ARCH_USES_GETTIMEOFFSET
412 select NEED_MACH_IO_H
413 select NEED_MACH_MEMORY_H
416 This is an evaluation board for the StrongARM processor available
417 from Digital. It has limited hardware on-board, including an
418 Ethernet interface, two PCMCIA sockets, two serial ports and a
423 select ARCH_HAS_HOLES_MEMORYMODEL
424 select ARCH_REQUIRE_GPIOLIB
425 select ARCH_USES_GETTIMEOFFSET
430 select NEED_MACH_MEMORY_H
432 This enables support for the Cirrus EP93xx series of CPUs.
434 config ARCH_FOOTBRIDGE
438 select GENERIC_CLOCKEVENTS
440 select NEED_MACH_IO_H if !MMU
441 select NEED_MACH_MEMORY_H
443 Support for systems based on the DC21285 companion chip
444 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
447 bool "Freescale MXS-based"
448 select ARCH_REQUIRE_GPIOLIB
452 select GENERIC_CLOCKEVENTS
453 select HAVE_CLK_PREPARE
454 select MULTI_IRQ_HANDLER
459 Support for Freescale MXS-based family of processors
462 bool "Hilscher NetX based"
466 select GENERIC_CLOCKEVENTS
468 This enables support for systems based on the Hilscher NetX Soc
471 bool "Hynix HMS720x-based"
472 select ARCH_USES_GETTIMEOFFSET
476 This enables support for systems based on the Hynix HMS720x
481 select ARCH_SUPPORTS_MSI
483 select NEED_MACH_MEMORY_H
484 select NEED_RET_TO_USER
489 Support for Intel's IOP13XX (XScale) family of processors.
494 select ARCH_REQUIRE_GPIOLIB
496 select NEED_MACH_GPIO_H
497 select NEED_RET_TO_USER
501 Support for Intel's 80219 and IOP32X (XScale) family of
507 select ARCH_REQUIRE_GPIOLIB
509 select NEED_MACH_GPIO_H
510 select NEED_RET_TO_USER
514 Support for Intel's IOP33X (XScale) family of processors.
519 select ARCH_HAS_DMA_SET_COHERENT_MASK
520 select ARCH_REQUIRE_GPIOLIB
523 select DMABOUNCE if PCI
524 select GENERIC_CLOCKEVENTS
525 select MIGHT_HAVE_PCI
526 select NEED_MACH_IO_H
528 Support for Intel's IXP4XX (XScale) family of processors.
532 select ARCH_REQUIRE_GPIOLIB
533 select COMMON_CLK_DOVE
535 select GENERIC_CLOCKEVENTS
536 select MIGHT_HAVE_PCI
539 select PLAT_ORION_LEGACY
540 select USB_ARCH_HAS_EHCI
542 Support for the Marvell Dove SoC 88AP510
545 bool "Marvell Kirkwood"
546 select ARCH_REQUIRE_GPIOLIB
548 select GENERIC_CLOCKEVENTS
552 select PINCTRL_KIRKWOOD
553 select PLAT_ORION_LEGACY
555 Support for the following Marvell Kirkwood series SoCs:
556 88F6180, 88F6192 and 88F6281.
559 bool "Marvell MV78xx0"
560 select ARCH_REQUIRE_GPIOLIB
562 select GENERIC_CLOCKEVENTS
564 select PLAT_ORION_LEGACY
566 Support for the following Marvell MV78xx0 series SoCs:
572 select ARCH_REQUIRE_GPIOLIB
574 select GENERIC_CLOCKEVENTS
576 select PLAT_ORION_LEGACY
578 Support for the following Marvell Orion 5x series SoCs:
579 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
580 Orion-2 (5281), Orion-1-90 (6183).
583 bool "Marvell PXA168/910/MMP2"
585 select ARCH_REQUIRE_GPIOLIB
587 select GENERIC_ALLOCATOR
588 select GENERIC_CLOCKEVENTS
591 select NEED_MACH_GPIO_H
596 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
599 bool "Micrel/Kendin KS8695"
600 select ARCH_REQUIRE_GPIOLIB
603 select GENERIC_CLOCKEVENTS
604 select NEED_MACH_MEMORY_H
606 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
607 System-on-Chip devices.
610 bool "Nuvoton W90X900 CPU"
611 select ARCH_REQUIRE_GPIOLIB
615 select GENERIC_CLOCKEVENTS
617 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
618 At present, the w90x900 has been renamed nuc900, regarding
619 the ARM series product line, you can login the following
620 link address to know more.
622 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
623 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
627 select ARCH_REQUIRE_GPIOLIB
632 select GENERIC_CLOCKEVENTS
635 select USB_ARCH_HAS_OHCI
638 Support for the NXP LPC32XX family of processors
642 select ARCH_HAS_CPUFREQ
646 select GENERIC_CLOCKEVENTS
650 select MIGHT_HAVE_CACHE_L2X0
654 This enables support for NVIDIA Tegra based systems (Tegra APX,
655 Tegra 6xx and Tegra 2 series).
658 bool "PXA2xx/PXA3xx-based"
660 select ARCH_HAS_CPUFREQ
662 select ARCH_REQUIRE_GPIOLIB
663 select ARM_CPU_SUSPEND if PM
667 select GENERIC_CLOCKEVENTS
670 select MULTI_IRQ_HANDLER
671 select NEED_MACH_GPIO_H
675 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
679 select ARCH_REQUIRE_GPIOLIB
681 select GENERIC_CLOCKEVENTS
684 Support for Qualcomm MSM/QSD based systems. This runs on the
685 apps processor of the MSM/QSD and depends on a shared memory
686 interface to the modem processor which runs the baseband
687 stack and controls some vital subsystems
688 (clock and power control, etc).
691 bool "Renesas SH-Mobile / R-Mobile"
693 select GENERIC_CLOCKEVENTS
695 select HAVE_MACH_CLKDEV
697 select MIGHT_HAVE_CACHE_L2X0
698 select MULTI_IRQ_HANDLER
699 select NEED_MACH_MEMORY_H
701 select PM_GENERIC_DOMAINS if PM
704 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
709 select ARCH_MAY_HAVE_PC_FDC
710 select ARCH_SPARSEMEM_ENABLE
711 select ARCH_USES_GETTIMEOFFSET
714 select HAVE_PATA_PLATFORM
716 select NEED_MACH_IO_H
717 select NEED_MACH_MEMORY_H
720 On the Acorn Risc-PC, Linux can support the internal IDE disk and
721 CD-ROM interface, serial and parallel port, and the floppy drive.
725 select ARCH_HAS_CPUFREQ
727 select ARCH_REQUIRE_GPIOLIB
728 select ARCH_SPARSEMEM_ENABLE
733 select GENERIC_CLOCKEVENTS
736 select NEED_MACH_GPIO_H
737 select NEED_MACH_MEMORY_H
740 Support for StrongARM 11x0 based boards.
743 bool "Samsung S3C24XX SoCs"
744 select ARCH_HAS_CPUFREQ
745 select ARCH_USES_GETTIMEOFFSET
749 select HAVE_S3C2410_I2C if I2C
750 select HAVE_S3C2410_WATCHDOG if WATCHDOG
751 select HAVE_S3C_RTC if RTC_CLASS
752 select NEED_MACH_GPIO_H
753 select NEED_MACH_IO_H
755 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
756 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
757 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
758 Samsung SMDK2410 development board (and derivatives).
761 bool "Samsung S3C64XX"
762 select ARCH_HAS_CPUFREQ
763 select ARCH_REQUIRE_GPIOLIB
764 select ARCH_USES_GETTIMEOFFSET
769 select HAVE_S3C2410_I2C if I2C
770 select HAVE_S3C2410_WATCHDOG if WATCHDOG
772 select NEED_MACH_GPIO_H
776 select S3C_GPIO_TRACK
777 select SAMSUNG_CLKSRC
778 select SAMSUNG_GPIOLIB_4BIT
779 select SAMSUNG_IRQ_VIC_TIMER
780 select USB_ARCH_HAS_OHCI
782 Samsung S3C64XX series based systems
785 bool "Samsung S5P6440 S5P6450"
789 select GENERIC_CLOCKEVENTS
792 select HAVE_S3C2410_I2C if I2C
793 select HAVE_S3C2410_WATCHDOG if WATCHDOG
794 select HAVE_S3C_RTC if RTC_CLASS
795 select NEED_MACH_GPIO_H
797 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
801 bool "Samsung S5PC100"
802 select ARCH_USES_GETTIMEOFFSET
807 select HAVE_S3C2410_I2C if I2C
808 select HAVE_S3C2410_WATCHDOG if WATCHDOG
809 select HAVE_S3C_RTC if RTC_CLASS
810 select NEED_MACH_GPIO_H
812 Samsung S5PC100 series based systems
815 bool "Samsung S5PV210/S5PC110"
816 select ARCH_HAS_CPUFREQ
817 select ARCH_HAS_HOLES_MEMORYMODEL
818 select ARCH_SPARSEMEM_ENABLE
822 select GENERIC_CLOCKEVENTS
825 select HAVE_S3C2410_I2C if I2C
826 select HAVE_S3C2410_WATCHDOG if WATCHDOG
827 select HAVE_S3C_RTC if RTC_CLASS
828 select NEED_MACH_GPIO_H
829 select NEED_MACH_MEMORY_H
831 Samsung S5PV210/S5PC110 series based systems
834 bool "Samsung EXYNOS"
835 select ARCH_HAS_CPUFREQ
836 select ARCH_HAS_HOLES_MEMORYMODEL
837 select ARCH_SPARSEMEM_ENABLE
840 select GENERIC_CLOCKEVENTS
843 select HAVE_S3C2410_I2C if I2C
844 select HAVE_S3C2410_WATCHDOG if WATCHDOG
845 select HAVE_S3C_RTC if RTC_CLASS
846 select NEED_MACH_GPIO_H
847 select NEED_MACH_MEMORY_H
849 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
853 select ARCH_USES_GETTIMEOFFSET
857 select NEED_MACH_MEMORY_H
861 Support for the StrongARM based Digital DNARD machine, also known
862 as "Shark" (<http://www.shark-linux.de/shark.html>).
865 bool "ST-Ericsson U300 Series"
867 select ARCH_REQUIRE_GPIOLIB
869 select ARM_PATCH_PHYS_VIRT
875 select GENERIC_CLOCKEVENTS
880 Support for ST-Ericsson U300 series mobile platforms.
883 bool "ST-Ericsson U8500 Series"
885 select ARCH_HAS_CPUFREQ
886 select ARCH_REQUIRE_GPIOLIB
890 select GENERIC_CLOCKEVENTS
892 select MIGHT_HAVE_CACHE_L2X0
895 Support for ST-Ericsson's Ux500 architecture
898 bool "STMicroelectronics Nomadik"
899 select ARCH_REQUIRE_GPIOLIB
904 select GENERIC_CLOCKEVENTS
905 select MIGHT_HAVE_CACHE_L2X0
907 select PINCTRL_STN8815
910 Support for the Nomadik platform by ST-Ericsson
914 select ARCH_HAS_CPUFREQ
915 select ARCH_REQUIRE_GPIOLIB
920 select GENERIC_CLOCKEVENTS
923 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
927 select ARCH_HAS_HOLES_MEMORYMODEL
928 select ARCH_REQUIRE_GPIOLIB
930 select GENERIC_ALLOCATOR
931 select GENERIC_CLOCKEVENTS
932 select GENERIC_IRQ_CHIP
934 select NEED_MACH_GPIO_H
938 Support for TI's DaVinci platform.
943 select ARCH_HAS_CPUFREQ
944 select ARCH_HAS_HOLES_MEMORYMODEL
945 select ARCH_REQUIRE_GPIOLIB
947 select GENERIC_CLOCKEVENTS
950 Support for TI's OMAP platform (OMAP1/2/3/4).
952 config ARCH_VT8500_SINGLE
953 bool "VIA/WonderMedia 85xx"
954 select ARCH_HAS_CPUFREQ
955 select ARCH_REQUIRE_GPIOLIB
959 select GENERIC_CLOCKEVENTS
962 select MULTI_IRQ_HANDLER
966 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
970 menu "Multiple platform selection"
971 depends on ARCH_MULTIPLATFORM
973 comment "CPU Core family selection"
976 bool "ARMv4 based platforms (FA526, StrongARM)"
977 depends on !ARCH_MULTI_V6_V7
978 select ARCH_MULTI_V4_V5
980 config ARCH_MULTI_V4T
981 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
982 depends on !ARCH_MULTI_V6_V7
983 select ARCH_MULTI_V4_V5
986 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
987 depends on !ARCH_MULTI_V6_V7
988 select ARCH_MULTI_V4_V5
990 config ARCH_MULTI_V4_V5
994 bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
995 select ARCH_MULTI_V6_V7
999 bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
1001 select ARCH_MULTI_V6_V7
1002 select ARCH_VEXPRESS
1005 config ARCH_MULTI_V6_V7
1008 config ARCH_MULTI_CPU_AUTO
1009 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
1010 select ARCH_MULTI_V5
1015 # This is sorted alphabetically by mach-* pathname. However, plat-*
1016 # Kconfigs may be included either alphabetically (according to the
1017 # plat- suffix) or along side the corresponding mach-* source.
1019 source "arch/arm/mach-mvebu/Kconfig"
1021 source "arch/arm/mach-at91/Kconfig"
1023 source "arch/arm/mach-bcm/Kconfig"
1025 source "arch/arm/mach-clps711x/Kconfig"
1027 source "arch/arm/mach-cns3xxx/Kconfig"
1029 source "arch/arm/mach-davinci/Kconfig"
1031 source "arch/arm/mach-dove/Kconfig"
1033 source "arch/arm/mach-ep93xx/Kconfig"
1035 source "arch/arm/mach-footbridge/Kconfig"
1037 source "arch/arm/mach-gemini/Kconfig"
1039 source "arch/arm/mach-h720x/Kconfig"
1041 source "arch/arm/mach-highbank/Kconfig"
1043 source "arch/arm/mach-integrator/Kconfig"
1045 source "arch/arm/mach-iop32x/Kconfig"
1047 source "arch/arm/mach-iop33x/Kconfig"
1049 source "arch/arm/mach-iop13xx/Kconfig"
1051 source "arch/arm/mach-ixp4xx/Kconfig"
1053 source "arch/arm/mach-kirkwood/Kconfig"
1055 source "arch/arm/mach-ks8695/Kconfig"
1057 source "arch/arm/mach-msm/Kconfig"
1059 source "arch/arm/mach-mv78xx0/Kconfig"
1061 source "arch/arm/mach-imx/Kconfig"
1063 source "arch/arm/mach-mxs/Kconfig"
1065 source "arch/arm/mach-netx/Kconfig"
1067 source "arch/arm/mach-nomadik/Kconfig"
1069 source "arch/arm/plat-omap/Kconfig"
1071 source "arch/arm/mach-omap1/Kconfig"
1073 source "arch/arm/mach-omap2/Kconfig"
1075 source "arch/arm/mach-orion5x/Kconfig"
1077 source "arch/arm/mach-picoxcell/Kconfig"
1079 source "arch/arm/mach-pxa/Kconfig"
1080 source "arch/arm/plat-pxa/Kconfig"
1082 source "arch/arm/mach-mmp/Kconfig"
1084 source "arch/arm/mach-realview/Kconfig"
1086 source "arch/arm/mach-sa1100/Kconfig"
1088 source "arch/arm/plat-samsung/Kconfig"
1089 source "arch/arm/plat-s3c24xx/Kconfig"
1091 source "arch/arm/mach-socfpga/Kconfig"
1093 source "arch/arm/plat-spear/Kconfig"
1095 source "arch/arm/mach-s3c24xx/Kconfig"
1097 source "arch/arm/mach-s3c2412/Kconfig"
1098 source "arch/arm/mach-s3c2440/Kconfig"
1102 source "arch/arm/mach-s3c64xx/Kconfig"
1105 source "arch/arm/mach-s5p64x0/Kconfig"
1107 source "arch/arm/mach-s5pc100/Kconfig"
1109 source "arch/arm/mach-s5pv210/Kconfig"
1111 source "arch/arm/mach-exynos/Kconfig"
1113 source "arch/arm/mach-shmobile/Kconfig"
1115 source "arch/arm/mach-sunxi/Kconfig"
1117 source "arch/arm/mach-prima2/Kconfig"
1119 source "arch/arm/mach-tegra/Kconfig"
1121 source "arch/arm/mach-u300/Kconfig"
1123 source "arch/arm/mach-ux500/Kconfig"
1125 source "arch/arm/mach-versatile/Kconfig"
1127 source "arch/arm/mach-vexpress/Kconfig"
1128 source "arch/arm/plat-versatile/Kconfig"
1130 source "arch/arm/mach-vt8500/Kconfig"
1132 source "arch/arm/mach-w90x900/Kconfig"
1134 source "arch/arm/mach-zynq/Kconfig"
1136 # Definitions to make life easier
1142 select GENERIC_CLOCKEVENTS
1148 select GENERIC_IRQ_CHIP
1151 config PLAT_ORION_LEGACY
1158 config PLAT_VERSATILE
1161 config ARM_TIMER_SP804
1164 select HAVE_SCHED_CLOCK
1166 source arch/arm/mm/Kconfig
1170 default 16 if ARCH_EP93XX
1174 bool "Enable iWMMXt support"
1175 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1176 default y if PXA27x || PXA3xx || ARCH_MMP
1178 Enable support for iWMMXt context switching at run time if
1179 running on a CPU that supports it.
1183 depends on CPU_XSCALE
1186 config MULTI_IRQ_HANDLER
1189 Allow each machine to specify it's own IRQ handler at run time.
1192 source "arch/arm/Kconfig-nommu"
1195 config ARM_ERRATA_326103
1196 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1199 Executing a SWP instruction to read-only memory does not set bit 11
1200 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1201 treat the access as a read, preventing a COW from occurring and
1202 causing the faulting task to livelock.
1204 config ARM_ERRATA_411920
1205 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1206 depends on CPU_V6 || CPU_V6K
1208 Invalidation of the Instruction Cache operation can
1209 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1210 It does not affect the MPCore. This option enables the ARM Ltd.
1211 recommended workaround.
1213 config ARM_ERRATA_430973
1214 bool "ARM errata: Stale prediction on replaced interworking branch"
1217 This option enables the workaround for the 430973 Cortex-A8
1218 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1219 interworking branch is replaced with another code sequence at the
1220 same virtual address, whether due to self-modifying code or virtual
1221 to physical address re-mapping, Cortex-A8 does not recover from the
1222 stale interworking branch prediction. This results in Cortex-A8
1223 executing the new code sequence in the incorrect ARM or Thumb state.
1224 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1225 and also flushes the branch target cache at every context switch.
1226 Note that setting specific bits in the ACTLR register may not be
1227 available in non-secure mode.
1229 config ARM_ERRATA_458693
1230 bool "ARM errata: Processor deadlock when a false hazard is created"
1232 depends on !ARCH_MULTIPLATFORM
1234 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1235 erratum. For very specific sequences of memory operations, it is
1236 possible for a hazard condition intended for a cache line to instead
1237 be incorrectly associated with a different cache line. This false
1238 hazard might then cause a processor deadlock. The workaround enables
1239 the L1 caching of the NEON accesses and disables the PLD instruction
1240 in the ACTLR register. Note that setting specific bits in the ACTLR
1241 register may not be available in non-secure mode.
1243 config ARM_ERRATA_460075
1244 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1246 depends on !ARCH_MULTIPLATFORM
1248 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1249 erratum. Any asynchronous access to the L2 cache may encounter a
1250 situation in which recent store transactions to the L2 cache are lost
1251 and overwritten with stale memory contents from external memory. The
1252 workaround disables the write-allocate mode for the L2 cache via the
1253 ACTLR register. Note that setting specific bits in the ACTLR register
1254 may not be available in non-secure mode.
1256 config ARM_ERRATA_742230
1257 bool "ARM errata: DMB operation may be faulty"
1258 depends on CPU_V7 && SMP
1259 depends on !ARCH_MULTIPLATFORM
1261 This option enables the workaround for the 742230 Cortex-A9
1262 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1263 between two write operations may not ensure the correct visibility
1264 ordering of the two writes. This workaround sets a specific bit in
1265 the diagnostic register of the Cortex-A9 which causes the DMB
1266 instruction to behave as a DSB, ensuring the correct behaviour of
1269 config ARM_ERRATA_742231
1270 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1271 depends on CPU_V7 && SMP
1272 depends on !ARCH_MULTIPLATFORM
1274 This option enables the workaround for the 742231 Cortex-A9
1275 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1276 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1277 accessing some data located in the same cache line, may get corrupted
1278 data due to bad handling of the address hazard when the line gets
1279 replaced from one of the CPUs at the same time as another CPU is
1280 accessing it. This workaround sets specific bits in the diagnostic
1281 register of the Cortex-A9 which reduces the linefill issuing
1282 capabilities of the processor.
1284 config PL310_ERRATA_588369
1285 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1286 depends on CACHE_L2X0
1288 The PL310 L2 cache controller implements three types of Clean &
1289 Invalidate maintenance operations: by Physical Address
1290 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1291 They are architecturally defined to behave as the execution of a
1292 clean operation followed immediately by an invalidate operation,
1293 both performing to the same memory location. This functionality
1294 is not correctly implemented in PL310 as clean lines are not
1295 invalidated as a result of these operations.
1297 config ARM_ERRATA_720789
1298 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1301 This option enables the workaround for the 720789 Cortex-A9 (prior to
1302 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1303 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1304 As a consequence of this erratum, some TLB entries which should be
1305 invalidated are not, resulting in an incoherency in the system page
1306 tables. The workaround changes the TLB flushing routines to invalidate
1307 entries regardless of the ASID.
1309 config PL310_ERRATA_727915
1310 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1311 depends on CACHE_L2X0
1313 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1314 operation (offset 0x7FC). This operation runs in background so that
1315 PL310 can handle normal accesses while it is in progress. Under very
1316 rare circumstances, due to this erratum, write data can be lost when
1317 PL310 treats a cacheable write transaction during a Clean &
1318 Invalidate by Way operation.
1320 config ARM_ERRATA_743622
1321 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1323 depends on !ARCH_MULTIPLATFORM
1325 This option enables the workaround for the 743622 Cortex-A9
1326 (r2p*) erratum. Under very rare conditions, a faulty
1327 optimisation in the Cortex-A9 Store Buffer may lead to data
1328 corruption. This workaround sets a specific bit in the diagnostic
1329 register of the Cortex-A9 which disables the Store Buffer
1330 optimisation, preventing the defect from occurring. This has no
1331 visible impact on the overall performance or power consumption of the
1334 config ARM_ERRATA_751472
1335 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1337 depends on !ARCH_MULTIPLATFORM
1339 This option enables the workaround for the 751472 Cortex-A9 (prior
1340 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1341 completion of a following broadcasted operation if the second
1342 operation is received by a CPU before the ICIALLUIS has completed,
1343 potentially leading to corrupted entries in the cache or TLB.
1345 config PL310_ERRATA_753970
1346 bool "PL310 errata: cache sync operation may be faulty"
1347 depends on CACHE_PL310
1349 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1351 Under some condition the effect of cache sync operation on
1352 the store buffer still remains when the operation completes.
1353 This means that the store buffer is always asked to drain and
1354 this prevents it from merging any further writes. The workaround
1355 is to replace the normal offset of cache sync operation (0x730)
1356 by another offset targeting an unmapped PL310 register 0x740.
1357 This has the same effect as the cache sync operation: store buffer
1358 drain and waiting for all buffers empty.
1360 config ARM_ERRATA_754322
1361 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1364 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1365 r3p*) erratum. A speculative memory access may cause a page table walk
1366 which starts prior to an ASID switch but completes afterwards. This
1367 can populate the micro-TLB with a stale entry which may be hit with
1368 the new ASID. This workaround places two dsb instructions in the mm
1369 switching code so that no page table walks can cross the ASID switch.
1371 config ARM_ERRATA_754327
1372 bool "ARM errata: no automatic Store Buffer drain"
1373 depends on CPU_V7 && SMP
1375 This option enables the workaround for the 754327 Cortex-A9 (prior to
1376 r2p0) erratum. The Store Buffer does not have any automatic draining
1377 mechanism and therefore a livelock may occur if an external agent
1378 continuously polls a memory location waiting to observe an update.
1379 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1380 written polling loops from denying visibility of updates to memory.
1382 config ARM_ERRATA_364296
1383 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1384 depends on CPU_V6 && !SMP
1386 This options enables the workaround for the 364296 ARM1136
1387 r0p2 erratum (possible cache data corruption with
1388 hit-under-miss enabled). It sets the undocumented bit 31 in
1389 the auxiliary control register and the FI bit in the control
1390 register, thus disabling hit-under-miss without putting the
1391 processor into full low interrupt latency mode. ARM11MPCore
1394 config ARM_ERRATA_764369
1395 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1396 depends on CPU_V7 && SMP
1398 This option enables the workaround for erratum 764369
1399 affecting Cortex-A9 MPCore with two or more processors (all
1400 current revisions). Under certain timing circumstances, a data
1401 cache line maintenance operation by MVA targeting an Inner
1402 Shareable memory region may fail to proceed up to either the
1403 Point of Coherency or to the Point of Unification of the
1404 system. This workaround adds a DSB instruction before the
1405 relevant cache maintenance functions and sets a specific bit
1406 in the diagnostic control register of the SCU.
1408 config PL310_ERRATA_769419
1409 bool "PL310 errata: no automatic Store Buffer drain"
1410 depends on CACHE_L2X0
1412 On revisions of the PL310 prior to r3p2, the Store Buffer does
1413 not automatically drain. This can cause normal, non-cacheable
1414 writes to be retained when the memory system is idle, leading
1415 to suboptimal I/O performance for drivers using coherent DMA.
1416 This option adds a write barrier to the cpu_idle loop so that,
1417 on systems with an outer cache, the store buffer is drained
1420 config ARM_ERRATA_775420
1421 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1424 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1425 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1426 operation aborts with MMU exception, it might cause the processor
1427 to deadlock. This workaround puts DSB before executing ISB if
1428 an abort may occur on cache maintenance.
1432 source "arch/arm/common/Kconfig"
1442 Find out whether you have ISA slots on your motherboard. ISA is the
1443 name of a bus system, i.e. the way the CPU talks to the other stuff
1444 inside your box. Other bus systems are PCI, EISA, MicroChannel
1445 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1446 newer boards don't support it. If you have ISA, say Y, otherwise N.
1448 # Select ISA DMA controller support
1453 config ARCH_NO_VIRT_TO_BUS
1455 depends on !ARCH_RPC && !ARCH_NETWINDER && !ARCH_SHARK
1457 # Select ISA DMA interface
1462 bool "PCI support" if MIGHT_HAVE_PCI
1464 Find out whether you have a PCI motherboard. PCI is the name of a
1465 bus system, i.e. the way the CPU talks to the other stuff inside
1466 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1467 VESA. If you have PCI, say Y, otherwise N.
1473 config PCI_NANOENGINE
1474 bool "BSE nanoEngine PCI support"
1475 depends on SA1100_NANOENGINE
1477 Enable PCI on the BSE nanoEngine board.
1482 # Select the host bridge type
1483 config PCI_HOST_VIA82C505
1485 depends on PCI && ARCH_SHARK
1488 config PCI_HOST_ITE8152
1490 depends on PCI && MACH_ARMCORE
1494 source "drivers/pci/Kconfig"
1496 source "drivers/pcmcia/Kconfig"
1500 menu "Kernel Features"
1505 This option should be selected by machines which have an SMP-
1508 The only effect of this option is to make the SMP-related
1509 options available to the user for configuration.
1512 bool "Symmetric Multi-Processing"
1513 depends on CPU_V6K || CPU_V7
1514 depends on GENERIC_CLOCKEVENTS
1517 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1518 select USE_GENERIC_SMP_HELPERS
1520 This enables support for systems with more than one CPU. If you have
1521 a system with only one CPU, like most personal computers, say N. If
1522 you have a system with more than one CPU, say Y.
1524 If you say N here, the kernel will run on single and multiprocessor
1525 machines, but will use only one CPU of a multiprocessor machine. If
1526 you say Y here, the kernel will run on many, but not all, single
1527 processor machines. On a single processor machine, the kernel will
1528 run faster if you say N here.
1530 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1531 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1532 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1534 If you don't know what to do here, say N.
1537 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1538 depends on SMP && !XIP_KERNEL
1541 SMP kernels contain instructions which fail on non-SMP processors.
1542 Enabling this option allows the kernel to modify itself to make
1543 these instructions safe. Disabling it allows about 1K of space
1546 If you don't know what to do here, say Y.
1548 config ARM_CPU_TOPOLOGY
1549 bool "Support cpu topology definition"
1550 depends on SMP && CPU_V7
1553 Support ARM cpu topology definition. The MPIDR register defines
1554 affinity between processors which is then used to describe the cpu
1555 topology of an ARM System.
1558 bool "Multi-core scheduler support"
1559 depends on ARM_CPU_TOPOLOGY
1561 Multi-core scheduler support improves the CPU scheduler's decision
1562 making when dealing with multi-core CPU chips at a cost of slightly
1563 increased overhead in some places. If unsure say N here.
1566 bool "SMT scheduler support"
1567 depends on ARM_CPU_TOPOLOGY
1569 Improves the CPU scheduler's decision making when dealing with
1570 MultiThreading at a cost of slightly increased overhead in some
1571 places. If unsure say N here.
1576 This option enables support for the ARM system coherency unit
1578 config ARM_ARCH_TIMER
1579 bool "Architected timer support"
1582 This option enables support for the ARM architected timer
1588 This options enables support for the ARM timer and watchdog unit
1591 prompt "Memory split"
1594 Select the desired split between kernel and user memory.
1596 If you are not absolutely sure what you are doing, leave this
1600 bool "3G/1G user/kernel split"
1602 bool "2G/2G user/kernel split"
1604 bool "1G/3G user/kernel split"
1609 default 0x40000000 if VMSPLIT_1G
1610 default 0x80000000 if VMSPLIT_2G
1614 int "Maximum number of CPUs (2-32)"
1620 bool "Support for hot-pluggable CPUs"
1621 depends on SMP && HOTPLUG
1623 Say Y here to experiment with turning CPUs off and on. CPUs
1624 can be controlled through /sys/devices/system/cpu.
1627 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1630 Say Y here if you want Linux to communicate with system firmware
1631 implementing the PSCI specification for CPU-centric power
1632 management operations described in ARM document number ARM DEN
1633 0022A ("Power State Coordination Interface System Software on
1637 bool "Use local timer interrupts"
1640 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1642 Enable support for local timers on SMP platforms, rather then the
1643 legacy IPI broadcast method. Local timers allows the system
1644 accounting to be spread across the timer interval, preventing a
1645 "thundering herd" at every timer tick.
1649 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1650 default 355 if ARCH_U8500
1651 default 264 if MACH_H4700
1652 default 512 if SOC_OMAP5
1653 default 288 if ARCH_VT8500 || ARCH_SUNXI
1656 Maximum number of GPIOs in the system.
1658 If unsure, leave the default value.
1660 source kernel/Kconfig.preempt
1664 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1665 ARCH_S5PV210 || ARCH_EXYNOS4
1666 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1667 default AT91_TIMER_HZ if ARCH_AT91
1668 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1672 def_bool HIGH_RES_TIMERS
1674 config THUMB2_KERNEL
1675 bool "Compile the kernel in Thumb-2 mode"
1676 depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1678 select ARM_ASM_UNIFIED
1681 By enabling this option, the kernel will be compiled in
1682 Thumb-2 mode. A compiler/assembler that understand the unified
1683 ARM-Thumb syntax is needed.
1687 config THUMB2_AVOID_R_ARM_THM_JUMP11
1688 bool "Work around buggy Thumb-2 short branch relocations in gas"
1689 depends on THUMB2_KERNEL && MODULES
1692 Various binutils versions can resolve Thumb-2 branches to
1693 locally-defined, preemptible global symbols as short-range "b.n"
1694 branch instructions.
1696 This is a problem, because there's no guarantee the final
1697 destination of the symbol, or any candidate locations for a
1698 trampoline, are within range of the branch. For this reason, the
1699 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1700 relocation in modules at all, and it makes little sense to add
1703 The symptom is that the kernel fails with an "unsupported
1704 relocation" error when loading some modules.
1706 Until fixed tools are available, passing
1707 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1708 code which hits this problem, at the cost of a bit of extra runtime
1709 stack usage in some cases.
1711 The problem is described in more detail at:
1712 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1714 Only Thumb-2 kernels are affected.
1716 Unless you are sure your tools don't have this problem, say Y.
1718 config ARM_ASM_UNIFIED
1722 bool "Use the ARM EABI to compile the kernel"
1724 This option allows for the kernel to be compiled using the latest
1725 ARM ABI (aka EABI). This is only useful if you are using a user
1726 space environment that is also compiled with EABI.
1728 Since there are major incompatibilities between the legacy ABI and
1729 EABI, especially with regard to structure member alignment, this
1730 option also changes the kernel syscall calling convention to
1731 disambiguate both ABIs and allow for backward compatibility support
1732 (selected with CONFIG_OABI_COMPAT).
1734 To use this you need GCC version 4.0.0 or later.
1737 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1738 depends on AEABI && !THUMB2_KERNEL
1741 This option preserves the old syscall interface along with the
1742 new (ARM EABI) one. It also provides a compatibility layer to
1743 intercept syscalls that have structure arguments which layout
1744 in memory differs between the legacy ABI and the new ARM EABI
1745 (only for non "thumb" binaries). This option adds a tiny
1746 overhead to all syscalls and produces a slightly larger kernel.
1747 If you know you'll be using only pure EABI user space then you
1748 can say N here. If this option is not selected and you attempt
1749 to execute a legacy ABI binary then the result will be
1750 UNPREDICTABLE (in fact it can be predicted that it won't work
1751 at all). If in doubt say Y.
1753 config ARCH_HAS_HOLES_MEMORYMODEL
1756 config ARCH_SPARSEMEM_ENABLE
1759 config ARCH_SPARSEMEM_DEFAULT
1760 def_bool ARCH_SPARSEMEM_ENABLE
1762 config ARCH_SELECT_MEMORY_MODEL
1763 def_bool ARCH_SPARSEMEM_ENABLE
1765 config HAVE_ARCH_PFN_VALID
1766 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1769 bool "High Memory Support"
1772 The address space of ARM processors is only 4 Gigabytes large
1773 and it has to accommodate user address space, kernel address
1774 space as well as some memory mapped IO. That means that, if you
1775 have a large amount of physical memory and/or IO, not all of the
1776 memory can be "permanently mapped" by the kernel. The physical
1777 memory that is not permanently mapped is called "high memory".
1779 Depending on the selected kernel/user memory split, minimum
1780 vmalloc space and actual amount of RAM, you may not need this
1781 option which should result in a slightly faster kernel.
1786 bool "Allocate 2nd-level pagetables from highmem"
1789 config HW_PERF_EVENTS
1790 bool "Enable hardware performance counter support for perf events"
1791 depends on PERF_EVENTS
1794 Enable hardware performance counter support for perf events. If
1795 disabled, perf events will use software events only.
1799 config FORCE_MAX_ZONEORDER
1800 int "Maximum zone order" if ARCH_SHMOBILE
1801 range 11 64 if ARCH_SHMOBILE
1802 default "12" if SOC_AM33XX
1803 default "9" if SA1111
1806 The kernel memory allocator divides physically contiguous memory
1807 blocks into "zones", where each zone is a power of two number of
1808 pages. This option selects the largest power of two that the kernel
1809 keeps in the memory allocator. If you need to allocate very large
1810 blocks of physically contiguous memory, then you may need to
1811 increase this value.
1813 This config option is actually maximum order plus one. For example,
1814 a value of 11 means that the largest free memory block is 2^10 pages.
1816 config ALIGNMENT_TRAP
1818 depends on CPU_CP15_MMU
1819 default y if !ARCH_EBSA110
1820 select HAVE_PROC_CPU if PROC_FS
1822 ARM processors cannot fetch/store information which is not
1823 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1824 address divisible by 4. On 32-bit ARM processors, these non-aligned
1825 fetch/store instructions will be emulated in software if you say
1826 here, which has a severe performance impact. This is necessary for
1827 correct operation of some network protocols. With an IP-only
1828 configuration it is safe to say N, otherwise say Y.
1830 config UACCESS_WITH_MEMCPY
1831 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1833 default y if CPU_FEROCEON
1835 Implement faster copy_to_user and clear_user methods for CPU
1836 cores where a 8-word STM instruction give significantly higher
1837 memory write throughput than a sequence of individual 32bit stores.
1839 A possible side effect is a slight increase in scheduling latency
1840 between threads sharing the same address space if they invoke
1841 such copy operations with large buffers.
1843 However, if the CPU data cache is using a write-allocate mode,
1844 this option is unlikely to provide any performance gain.
1848 prompt "Enable seccomp to safely compute untrusted bytecode"
1850 This kernel feature is useful for number crunching applications
1851 that may need to compute untrusted bytecode during their
1852 execution. By using pipes or other transports made available to
1853 the process as file descriptors supporting the read/write
1854 syscalls, it's possible to isolate those applications in
1855 their own address space using seccomp. Once seccomp is
1856 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1857 and the task is only allowed to execute a few safe syscalls
1858 defined by each seccomp mode.
1860 config CC_STACKPROTECTOR
1861 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1863 This option turns on the -fstack-protector GCC feature. This
1864 feature puts, at the beginning of functions, a canary value on
1865 the stack just before the return address, and validates
1866 the value just before actually returning. Stack based buffer
1867 overflows (that need to overwrite this return address) now also
1868 overwrite the canary, which gets detected and the attack is then
1869 neutralized via a kernel panic.
1870 This feature requires gcc version 4.2 or above.
1877 bool "Xen guest support on ARM (EXPERIMENTAL)"
1878 depends on ARM && OF
1879 depends on CPU_V7 && !CPU_V6
1881 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1888 bool "Flattened Device Tree support"
1891 select OF_EARLY_FLATTREE
1893 Include support for flattened device tree machine descriptions.
1896 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1899 This is the traditional way of passing data to the kernel at boot
1900 time. If you are solely relying on the flattened device tree (or
1901 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1902 to remove ATAGS support from your kernel binary. If unsure,
1905 config DEPRECATED_PARAM_STRUCT
1906 bool "Provide old way to pass kernel parameters"
1909 This was deprecated in 2001 and announced to live on for 5 years.
1910 Some old boot loaders still use this way.
1912 # Compressed boot loader in ROM. Yes, we really want to ask about
1913 # TEXT and BSS so we preserve their values in the config files.
1914 config ZBOOT_ROM_TEXT
1915 hex "Compressed ROM boot loader base address"
1918 The physical address at which the ROM-able zImage is to be
1919 placed in the target. Platforms which normally make use of
1920 ROM-able zImage formats normally set this to a suitable
1921 value in their defconfig file.
1923 If ZBOOT_ROM is not enabled, this has no effect.
1925 config ZBOOT_ROM_BSS
1926 hex "Compressed ROM boot loader BSS address"
1929 The base address of an area of read/write memory in the target
1930 for the ROM-able zImage which must be available while the
1931 decompressor is running. It must be large enough to hold the
1932 entire decompressed kernel plus an additional 128 KiB.
1933 Platforms which normally make use of ROM-able zImage formats
1934 normally set this to a suitable value in their defconfig file.
1936 If ZBOOT_ROM is not enabled, this has no effect.
1939 bool "Compressed boot loader in ROM/flash"
1940 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1942 Say Y here if you intend to execute your compressed kernel image
1943 (zImage) directly from ROM or flash. If unsure, say N.
1946 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1947 depends on ZBOOT_ROM && ARCH_SH7372
1948 default ZBOOT_ROM_NONE
1950 Include experimental SD/MMC loading code in the ROM-able zImage.
1951 With this enabled it is possible to write the ROM-able zImage
1952 kernel image to an MMC or SD card and boot the kernel straight
1953 from the reset vector. At reset the processor Mask ROM will load
1954 the first part of the ROM-able zImage which in turn loads the
1955 rest the kernel image to RAM.
1957 config ZBOOT_ROM_NONE
1958 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1960 Do not load image from SD or MMC
1962 config ZBOOT_ROM_MMCIF
1963 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1965 Load image from MMCIF hardware block.
1967 config ZBOOT_ROM_SH_MOBILE_SDHI
1968 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1970 Load image from SDHI hardware block
1974 config ARM_APPENDED_DTB
1975 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1976 depends on OF && !ZBOOT_ROM
1978 With this option, the boot code will look for a device tree binary
1979 (DTB) appended to zImage
1980 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1982 This is meant as a backward compatibility convenience for those
1983 systems with a bootloader that can't be upgraded to accommodate
1984 the documented boot protocol using a device tree.
1986 Beware that there is very little in terms of protection against
1987 this option being confused by leftover garbage in memory that might
1988 look like a DTB header after a reboot if no actual DTB is appended
1989 to zImage. Do not leave this option active in a production kernel
1990 if you don't intend to always append a DTB. Proper passing of the
1991 location into r2 of a bootloader provided DTB is always preferable
1994 config ARM_ATAG_DTB_COMPAT
1995 bool "Supplement the appended DTB with traditional ATAG information"
1996 depends on ARM_APPENDED_DTB
1998 Some old bootloaders can't be updated to a DTB capable one, yet
1999 they provide ATAGs with memory configuration, the ramdisk address,
2000 the kernel cmdline string, etc. Such information is dynamically
2001 provided by the bootloader and can't always be stored in a static
2002 DTB. To allow a device tree enabled kernel to be used with such
2003 bootloaders, this option allows zImage to extract the information
2004 from the ATAG list and store it at run time into the appended DTB.
2007 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2008 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2010 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2011 bool "Use bootloader kernel arguments if available"
2013 Uses the command-line options passed by the boot loader instead of
2014 the device tree bootargs property. If the boot loader doesn't provide
2015 any, the device tree bootargs property will be used.
2017 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2018 bool "Extend with bootloader kernel arguments"
2020 The command-line arguments provided by the boot loader will be
2021 appended to the the device tree bootargs property.
2026 string "Default kernel command string"
2029 On some architectures (EBSA110 and CATS), there is currently no way
2030 for the boot loader to pass arguments to the kernel. For these
2031 architectures, you should supply some command-line options at build
2032 time by entering them here. As a minimum, you should specify the
2033 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2036 prompt "Kernel command line type" if CMDLINE != ""
2037 default CMDLINE_FROM_BOOTLOADER
2040 config CMDLINE_FROM_BOOTLOADER
2041 bool "Use bootloader kernel arguments if available"
2043 Uses the command-line options passed by the boot loader. If
2044 the boot loader doesn't provide any, the default kernel command
2045 string provided in CMDLINE will be used.
2047 config CMDLINE_EXTEND
2048 bool "Extend bootloader kernel arguments"
2050 The command-line arguments provided by the boot loader will be
2051 appended to the default kernel command string.
2053 config CMDLINE_FORCE
2054 bool "Always use the default kernel command string"
2056 Always use the default kernel command string, even if the boot
2057 loader passes other arguments to the kernel.
2058 This is useful if you cannot or don't want to change the
2059 command-line options your boot loader passes to the kernel.
2063 bool "Kernel Execute-In-Place from ROM"
2064 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2066 Execute-In-Place allows the kernel to run from non-volatile storage
2067 directly addressable by the CPU, such as NOR flash. This saves RAM
2068 space since the text section of the kernel is not loaded from flash
2069 to RAM. Read-write sections, such as the data section and stack,
2070 are still copied to RAM. The XIP kernel is not compressed since
2071 it has to run directly from flash, so it will take more space to
2072 store it. The flash address used to link the kernel object files,
2073 and for storing it, is configuration dependent. Therefore, if you
2074 say Y here, you must know the proper physical address where to
2075 store the kernel image depending on your own flash memory usage.
2077 Also note that the make target becomes "make xipImage" rather than
2078 "make zImage" or "make Image". The final kernel binary to put in
2079 ROM memory will be arch/arm/boot/xipImage.
2083 config XIP_PHYS_ADDR
2084 hex "XIP Kernel Physical Location"
2085 depends on XIP_KERNEL
2086 default "0x00080000"
2088 This is the physical address in your flash memory the kernel will
2089 be linked for and stored to. This address is dependent on your
2093 bool "Kexec system call (EXPERIMENTAL)"
2094 depends on (!SMP || HOTPLUG_CPU)
2096 kexec is a system call that implements the ability to shutdown your
2097 current kernel, and to start another kernel. It is like a reboot
2098 but it is independent of the system firmware. And like a reboot
2099 you can start any kernel with it, not just Linux.
2101 It is an ongoing process to be certain the hardware in a machine
2102 is properly shutdown, so do not be surprised if this code does not
2103 initially work for you. It may help to enable device hotplugging
2107 bool "Export atags in procfs"
2108 depends on ATAGS && KEXEC
2111 Should the atags used to boot the kernel be exported in an "atags"
2112 file in procfs. Useful with kexec.
2115 bool "Build kdump crash kernel (EXPERIMENTAL)"
2117 Generate crash dump after being started by kexec. This should
2118 be normally only set in special crash dump kernels which are
2119 loaded in the main kernel with kexec-tools into a specially
2120 reserved region and then later executed after a crash by
2121 kdump/kexec. The crash dump kernel must be compiled to a
2122 memory address not used by the main kernel
2124 For more details see Documentation/kdump/kdump.txt
2126 config AUTO_ZRELADDR
2127 bool "Auto calculation of the decompressed kernel image address"
2128 depends on !ZBOOT_ROM && !ARCH_U300
2130 ZRELADDR is the physical address where the decompressed kernel
2131 image will be placed. If AUTO_ZRELADDR is selected, the address
2132 will be determined at run-time by masking the current IP with
2133 0xf8000000. This assumes the zImage being placed in the first 128MB
2134 from start of memory.
2138 menu "CPU Power Management"
2142 source "drivers/cpufreq/Kconfig"
2145 tristate "CPUfreq driver for i.MX CPUs"
2146 depends on ARCH_MXC && CPU_FREQ
2147 select CPU_FREQ_TABLE
2149 This enables the CPUfreq driver for i.MX CPUs.
2151 config CPU_FREQ_SA1100
2154 config CPU_FREQ_SA1110
2157 config CPU_FREQ_INTEGRATOR
2158 tristate "CPUfreq driver for ARM Integrator CPUs"
2159 depends on ARCH_INTEGRATOR && CPU_FREQ
2162 This enables the CPUfreq driver for ARM Integrator CPUs.
2164 For details, take a look at <file:Documentation/cpu-freq>.
2170 depends on CPU_FREQ && ARCH_PXA && PXA25x
2172 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2173 select CPU_FREQ_TABLE
2178 Internal configuration node for common cpufreq on Samsung SoC
2180 config CPU_FREQ_S3C24XX
2181 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2182 depends on ARCH_S3C24XX && CPU_FREQ
2185 This enables the CPUfreq driver for the Samsung S3C24XX family
2188 For details, take a look at <file:Documentation/cpu-freq>.
2192 config CPU_FREQ_S3C24XX_PLL
2193 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2194 depends on CPU_FREQ_S3C24XX
2196 Compile in support for changing the PLL frequency from the
2197 S3C24XX series CPUfreq driver. The PLL takes time to settle
2198 after a frequency change, so by default it is not enabled.
2200 This also means that the PLL tables for the selected CPU(s) will
2201 be built which may increase the size of the kernel image.
2203 config CPU_FREQ_S3C24XX_DEBUG
2204 bool "Debug CPUfreq Samsung driver core"
2205 depends on CPU_FREQ_S3C24XX
2207 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2209 config CPU_FREQ_S3C24XX_IODEBUG
2210 bool "Debug CPUfreq Samsung driver IO timing"
2211 depends on CPU_FREQ_S3C24XX
2213 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2215 config CPU_FREQ_S3C24XX_DEBUGFS
2216 bool "Export debugfs for CPUFreq"
2217 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2219 Export status information via debugfs.
2223 source "drivers/cpuidle/Kconfig"
2227 menu "Floating point emulation"
2229 comment "At least one emulation must be selected"
2232 bool "NWFPE math emulation"
2233 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2235 Say Y to include the NWFPE floating point emulator in the kernel.
2236 This is necessary to run most binaries. Linux does not currently
2237 support floating point hardware so you need to say Y here even if
2238 your machine has an FPA or floating point co-processor podule.
2240 You may say N here if you are going to load the Acorn FPEmulator
2241 early in the bootup.
2244 bool "Support extended precision"
2245 depends on FPE_NWFPE
2247 Say Y to include 80-bit support in the kernel floating-point
2248 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2249 Note that gcc does not generate 80-bit operations by default,
2250 so in most cases this option only enlarges the size of the
2251 floating point emulator without any good reason.
2253 You almost surely want to say N here.
2256 bool "FastFPE math emulation (EXPERIMENTAL)"
2257 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2259 Say Y here to include the FAST floating point emulator in the kernel.
2260 This is an experimental much faster emulator which now also has full
2261 precision for the mantissa. It does not support any exceptions.
2262 It is very simple, and approximately 3-6 times faster than NWFPE.
2264 It should be sufficient for most programs. It may be not suitable
2265 for scientific calculations, but you have to check this for yourself.
2266 If you do not feel you need a faster FP emulation you should better
2270 bool "VFP-format floating point maths"
2271 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2273 Say Y to include VFP support code in the kernel. This is needed
2274 if your hardware includes a VFP unit.
2276 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2277 release notes and additional status information.
2279 Say N if your target does not have VFP hardware.
2287 bool "Advanced SIMD (NEON) Extension support"
2288 depends on VFPv3 && CPU_V7
2290 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2295 menu "Userspace binary formats"
2297 source "fs/Kconfig.binfmt"
2300 tristate "RISC OS personality"
2303 Say Y here to include the kernel code necessary if you want to run
2304 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2305 experimental; if this sounds frightening, say N and sleep in peace.
2306 You can also say M here to compile this support as a module (which
2307 will be called arthur).
2311 menu "Power management options"
2313 source "kernel/power/Kconfig"
2315 config ARCH_SUSPEND_POSSIBLE
2316 depends on !ARCH_S5PC100
2317 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2318 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2321 config ARM_CPU_SUSPEND
2326 source "net/Kconfig"
2328 source "drivers/Kconfig"
2332 source "arch/arm/Kconfig.debug"
2334 source "security/Kconfig"
2336 source "crypto/Kconfig"
2338 source "lib/Kconfig"
2340 source "arch/arm/kvm/Kconfig"