9 #define __xg(x) ((volatile INTPTR *)(x))
11 #define CFENCE asm volatile("":::"memory");
14 ".section .smp_locks,\"a\"\n" \
16 " .long 661f\n" /* address */\
21 static inline void atomic_dec(volatile int *v) {
22 __asm__ __volatile__ (LOCK_PREFIX "decl %0"
26 static inline void atomic_inc(volatile int *v) {
27 __asm__ __volatile__ (LOCK_PREFIX "incl %0"
31 static inline int atomic_sub_and_test(int i, volatile int *v) {
34 __asm__ __volatile__ (LOCK_PREFIX "subl %2,%0; sete %1"
35 : "+m" (*v), "=qm" (c)
36 : "ir" (i) : "memory");
41 static inline INTPTR LOCKXCHG(volatile INTPTR * ptr, INTPTR val){
43 //note: xchgl always implies lock
44 __asm__ __volatile__("xchgq %0,%1"
52 static inline int LOCKXCHG(volatile int* ptr, int val){
54 //note: xchgl always implies lock
55 __asm__ __volatile__("xchgl %0,%1"
65 static inline int write_trylock(volatile int *lock) {
67 __asm__ __volatile__("xchgl %0,%1"
69 : "m"(*lock), "0"(retval)
76 static inline INTPTR CAS(volatile void *ptr, unsigned INTPTR old, unsigned INTPTR new){
78 __asm__ __volatile__("lock; cmpxchgq %1,%2"
80 : "r"(new), "m"(*__xg(ptr)), "0"(old)
85 static inline long CAS(volatile void *ptr, unsigned long old, unsigned long new){
87 __asm__ __volatile__("lock; cmpxchgl %k1,%2"
89 : "r"(new), "m"(*__xg(ptr)), "0"(old)
95 static inline int BARRIER(){