1 #ifndef ____MLP_LOCK_H__
2 #define ____MLP_LOCK_H__
11 #define __xg(x) ((volatile INTPTR *)(x))
13 #define CFENCE asm volatile("":::"memory");
16 ".section .smp_locks,\"a\"\n" \
18 " .long 661f\n" /* address */\
23 static inline void atomic_dec(volatile int *v) {
24 __asm__ __volatile__ (LOCK_PREFIX "decl %0"
28 static inline void atomic_inc(volatile int *v) {
29 __asm__ __volatile__ (LOCK_PREFIX "incl %0"
33 static inline int atomic_sub_and_test(int i, volatile int *v) {
36 __asm__ __volatile__ (LOCK_PREFIX "subl %2,%0; sete %1"
37 : "+m" (*v), "=qm" (c)
38 : "ir" (i) : "memory");
43 static inline INTPTR LOCKXCHG(volatile INTPTR * ptr, INTPTR val){
45 //note: xchgl always implies lock
46 __asm__ __volatile__("xchgq %0,%1"
54 static inline int LOCKXCHG(volatile int* ptr, int val){
56 //note: xchgl always implies lock
57 __asm__ __volatile__("xchgl %0,%1"
67 static inline int write_trylock(volatile int *lock) {
69 __asm__ __volatile__("xchgl %0,%1"
71 : "m"(*lock), "0"(retval)
78 static inline INTPTR CAS(volatile void *ptr, unsigned INTPTR old, unsigned INTPTR new){
80 __asm__ __volatile__("lock; cmpxchgq %1,%2"
82 : "r"(new), "m"(*__xg(ptr)), "0"(old)
87 static inline long CAS(volatile void *ptr, unsigned long old, unsigned long new){
89 __asm__ __volatile__("lock; cmpxchgl %k1,%2"
91 : "r"(new), "m"(*__xg(ptr)), "0"(old)
97 static inline int BARRIER(){
103 #endif // ____MLP_LOCK_H__