1 ARM Virtual Generic Interrupt Controller (VGIC)
2 ===============================================
4 Device types supported:
5 KVM_DEV_TYPE_ARM_VGIC_V2 ARM Generic Interrupt Controller v2.0
7 Only one VGIC instance may be instantiated through either this API or the
8 legacy KVM_CREATE_IRQCHIP api. The created VGIC will act as the VM interrupt
9 controller, requiring emulated user-space devices to inject interrupts to the
10 VGIC instead of directly to CPUs.
13 KVM_DEV_ARM_VGIC_GRP_ADDR
15 KVM_VGIC_V2_ADDR_TYPE_DIST (rw, 64-bit)
16 Base address in the guest physical address space of the GIC distributor
19 KVM_VGIC_V2_ADDR_TYPE_CPU (rw, 64-bit)
20 Base address in the guest physical address space of the GIC virtual cpu
21 interface register mappings.
23 KVM_DEV_ARM_VGIC_GRP_DIST_REGS
25 The attr field of kvm_device_attr encodes two values:
26 bits: | 63 .... 40 | 39 .. 32 | 31 .... 0 |
27 values: | reserved | cpu id | offset |
29 All distributor regs are (rw, 32-bit)
31 The offset is relative to the "Distributor base address" as defined in the
32 GICv2 specs. Getting or setting such a register has the same effect as
33 reading or writing the register on the actual hardware from the cpu
34 specified with cpu id field. Note that most distributor fields are not
35 banked, but return the same value regardless of the cpu id used to access
38 - Priorities are not implemented, and registers are RAZ/WI
40 -ENODEV: Getting or setting this register is not yet supported
41 -EBUSY: One or more VCPUs are running
43 KVM_DEV_ARM_VGIC_GRP_CPU_REGS
45 The attr field of kvm_device_attr encodes two values:
46 bits: | 63 .... 40 | 39 .. 32 | 31 .... 0 |
47 values: | reserved | cpu id | offset |
49 All CPU interface regs are (rw, 32-bit)
51 The offset specifies the offset from the "CPU interface base address" as
52 defined in the GICv2 specs. Getting or setting such a register has the
53 same effect as reading or writing the register on the actual hardware.
55 The Active Priorities Registers APRn are implementation defined, so we set a
56 fixed format for our implementation that fits with the model of a "GICv2
57 implementation without the security extensions" which we present to the
58 guest. This interface always exposes four register APR[0-3] describing the
59 maximum possible 128 preemption levels. The semantics of the register
60 indicate if any interrupts in a given preemption level are in the active
61 state by setting the corresponding bit.
63 Thus, preemption level X has one or more active interrupts if and only if:
65 APRn[X mod 32] == 0b1, where n = X / 32
67 Bits for undefined preemption levels are RAZ/WI.
70 - Priorities are not implemented, and registers are RAZ/WI
72 -ENODEV: Getting or setting this register is not yet supported
73 -EBUSY: One or more VCPUs are running