Documentation/devicetree/bindings/video/rockchip-lvds.txt

   1 Rockchip RK3288 LVDS interface
   2 ================================
   3
   4 Required properties:
   5 - compatible: "rockchip,rk3288-lvds";
   6
   7 - reg: physical base address of the controller and length
   8         of memory mapped region.
   9 - clocks: must include clock specifiers corresponding to entries in the
  10         clock-names property.
  11 - clock-names: must contain "pclk_lvds"
  12
  13 - avdd1v0-supply: regulator phandle for 1.0V analog power
  14 - avdd1v8-supply: regulator phandle for 1.8V analog power
  15 - avdd3v3-supply: regulator phandle for 3.3V analog power
  16
  17 - rockchip,grf: phandle to the general register files syscon
  18
  19 - rockchip,data-mapping: should be "vesa" or "jeida",
  20         This describes how the color bits are laid out in the
  21         serialized LVDS signal.
  22 - rockchip,data-width : should be <18> or <24>;
  23 - rockchip,output: should be "rgb", "lvds" or "duallvds",
  24         This describes the output face.
  25
  26 Required nodes:
  27
  28 The lvds has two video ports as described by
  29         Documentation/devicetree/bindings/media/video-interfaces.txt.
  30 Their connections are modeled using the OF graph bindings specified in
  31         Documentation/devicetree/bindings/graph.txt.
  32
  33 - video port 0 for the VOP inputs
  34 - video port 1 for either a panel or subsequent encoder
  35
  36 Example:
  37         lvds: lvds@ff96c000 {
  38                 compatible = "rockchip,rk3288-lvds";
  39                 rockchip,grf = <&grf>;
  40                 reg = <0xff96c000 0x4000>;
  41                 clocks = <&cru PCLK_LVDS_PHY>;
  42                 clock-names = "pclk_lvds";
  43                 avdd1v0-supply = <&vdd10_lcd>;
  44                 avdd1v8-supply = <&vcc18_lcd>;
  45                 avdd3v3-supply = <&vcca_33>;
  46                 rockchip,data-mapping = "jeida";
  47                 rockchip,data-width = <24>;
  48                 rockchip,output = "rgb";
  49                 ports {
  50                         #address-cells = <1>;
  51                         #size-cells = <0>;
  52
  53                         lvds_in: port@0 {
  54                                 reg = <0>;
  55
  56                                 lvds_in_vopb: endpoint@0 {
  57                                         reg = <0>;
  58                                         remote-endpoint = <&vopb_out_lvds>;
  59                                 };
  60                                 lvds_in_vopl: endpoint@1 {
  61                                         reg = <1>;
  62                                         remote-endpoint = <&vopl_out_lvds>;
  63                                 };
  64                         };
  65
  66                         lvds_out: port@1 {
  67                                 reg = <1>;
  68
  69                                 lvds_out_panel: endpoint {
  70                                         remote-endpoint = <&panel_in>;
  71                                 };
  72                         };
  73                 };
  74         };