1 Rockchip SoC USB controller
3 The USB devices interface with USB controllers on Rockchip SOCs.
4 The device node has following properties.
8 - compatible : Should be "rockchip,rk3188_usb20_otg" or
9 "rockchip,rk3288_usb20_otg" and so on, depending upon the SoC.
10 - reg : Physical base address of the controller and
11 length of memory mapped region.
12 - interrupts : interrupt number to the cpu.
13 - clocks : Clock IDs array as required by the controller.
14 - clock-names : Names of clock correseponding IDs clock
15 property as requested by the controller driver.
16 - rockchip,usb-mode : This signifies the otg controller mode.
17 "0" represents that otg supports both host and slave mode,
18 "1" represents that force otg to host only mode,
19 "2" represents that force otg to device only mode.
25 compatible = "rockchip,rk3288_usb20_otg";
26 reg = <0xff580000 0x40000>;
27 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
28 clocks = <&clk_gates13 4>, <&clk_gates7 4>;
29 clock-names = "clk_usbphy0", "hclk_usb0";
30 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
31 rockchip,usb-mode = <0>;
36 - compatible : Should be "rockchip,rk3188_usb20_host" or
37 "rockchip,rk3288_usb20_host" and so on, depending upon the SoC.
38 - reg : Physical base address of the controller and
39 length of memory mapped region.
40 - interrupts : Interrupt number to the cpu.
41 - clocks : Clock IDs array as required by the controller.
42 - clock-names : Names of clock correseponding IDs clock
43 property as requested by the controller driver.
49 compatible = "rockchip,rk3288_usb20_host";
50 reg = <0xff540000 0x40000>;
51 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
52 clocks = <&clk_gates13 6>, <&clk_gates7 7>,
54 clock-names = "clk_usbphy1", "hclk_usb1",
60 - compatible : Should be "rockchip,rk3188_rk_ehci_host" or
61 "rockchip,rk3288_rk_ehci_host" and so on, for USB 2.0 EHCI
62 controller in host mode, depending upon the SoC.
63 - reg : Physical base address of the controller and
64 length of memory mapped region.
65 - interrupts : Interrupt number to the cpu.
66 - clocks : Clock IDs array as required by the controller.
67 - clock-names : Names of clock correseponding IDs clock
68 property as requested by the controller driver.
74 compatible = "rockchip,rk3288_rk_ehci_host";
75 reg = <0xff500000 0x20000>;
76 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
77 clocks = <&clk_gates13 5>, <&clk_gates7 6>;
78 clock-names = "clk_usbphy2", "hclk_usb2";
83 - compatible : Should be "rockchip,rk3188_rk_ohci_host" or
84 "rockchip,rk3288_rk_ohci_host" and so on, for USB 2.0 OHCI
85 companion controller in host mode, depending upon the SoC.
86 - reg : Physical base address of the controller and
87 length of memory mapped region.
88 - interrupts : Interrupt number to the cpu.
89 - clocks : Clock IDs array as required by the controller.
90 - clock-names : Names of clock correseponding IDs clock
91 property as requested by the controller driver.
97 compatible = "rockchip,rk3288_rk_ohci_host";
98 reg = <0xff520000 0x20000>;
99 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
100 clocks = <&clk_gates13 5>, <&clk_gates7 6>;
101 clock-names = "clk_usbphy3", "hclk_usb3";
107 - compatible : Should be "rockchip,rk3188_rk_hsic_host" or
108 "rockchip,rk3288_rk_hsic_host" and so on, depending upon
110 - reg : Physical base address of the controller and
111 length of memory mapped region.
112 - interrupts : Interrupt number to the cpu.
113 - clocks : Clock IDs array as required by the controller.
114 - clock-names : Names of clock correseponding IDs clock
115 property as requested by the controller driver.
120 hsic: hsic@ff5c0000 {
121 compatible = "rockchip,rk3288_rk_hsic_host";
122 reg = <0xff5c0000 0x40000>;
123 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
124 clocks = <&hsicphy_480m>, <&clk_gates7 8>,
125 <&hsicphy_12m>, <&usbphy_480m>,
126 <&otgphy1_480m>, <&otgphy2_480m>;
127 clock-names = "hsicphy_480m", "hclk_hsic",
128 "hsicphy_12m", "usbphy_480m",
129 "hsic_usbphy1", "hsic_usbphy2";
132 ROCKCHIP USB-PHY CONTROL
134 - compatible : Should be "rockchip,rk3188-dwc-control-usb"
135 or "rockchip,rk3288-dwc-control-usb" and so on, depending
137 - reg : Physical base address of USB-PHY GRF registers.
138 It contains the address of "GRF_SOC_STATUSX" and
139 "GRF_UOCX_BASE" depending upon the number of usb controllers
141 - reg-names : The names of the register addresses corresponding
142 to the registers filled in "reg".
143 - interrupts : Interrupt number to the cpu.
144 - interrupt-names : The names of the interrupts corresponding
145 to the registers filled in "interrupts".
146 - clocks : Clock IDs array as required by the controller.
147 - clock-names : Names of clock correseponding IDs clock
148 property as requested by the controller driver.
151 The child node 'usb_bc' to the node 'dwc_control_usb' is for
152 USB Battery Charging detect. It is used to differentiate the
153 Charging Port(i.e. CDP, DCP or SDP).
155 - compatible : Should be "synopsys,phy", "inno,phy" or
156 "rockchip,ctrl" depending upon the vendor of usb phy
160 The following properties represent the control and status
161 registers of usb otg battery charging. All these properties
162 are of type <u32>. Each property contains three tuples.
163 The layout of each tuple is:
165 offset, start bit, and bitmask.
184 dwc_control_usb: dwc-control-usb@ff770284 {
185 compatible = "rockchip,rk3288-dwc-control-usb";
186 reg = <0xff770284 0x04>, <0xff770288 0x04>,
187 <0xff7702cc 0x04>, <0xff7702d4 0x04>,
188 <0xff770320 0x14>, <0xff770334 0x14>,
189 <0xff770348 0x10>, <0xff770358 0x08>,
191 reg-names = "GRF_SOC_STATUS1" ,"GRF_SOC_STATUS2",
192 "GRF_SOC_STATUS19", "GRF_SOC_STATUS21",
193 "GRF_UOC0_BASE", "GRF_UOC1_BASE",
194 "GRF_UOC2_BASE", "GRF_UOC3_BASE",
196 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
201 interrupt-names = "otg_id",
206 clocks = <&clk_gates7 9>, <&usbphy_480m>,
207 <&otgphy1_480m>, <&otgphy2_480m>;
208 clock-names = "hclk_usb_peri", "usbphy_480m",
209 "usbphy1_480m", "usbphy2_480m";
212 compatible = "synopsys,phy";
213 /* offset bit mask */
214 rk_usb,bvalid = <0x288 14 1>;
215 rk_usb,dcdenb = <0x328 14 1>;
216 rk_usb,vdatsrcenb = <0x328 7 1>;
217 rk_usb,vdatdetenb = <0x328 6 1>;
218 rk_usb,chrgsel = <0x328 5 1>;
219 rk_usb,chgdet = <0x2cc 23 1>;
220 rk_usb,fsvminus = <0x2cc 25 1>;
221 rk_usb,fsvplus = <0x2cc 24 1>;
225 ROCKCHIP USB-COMMON CONTROL
227 - compatible : Should be "rockchip,rk3188-usb-control" or
228 "rockchip,rk3288-usb-control" and so on, depending upon
232 - host_drv_gpio : If present, specifies the GPIO that needs
233 to be pulled up for the host bus to be powered.
234 - otg_drv_gpio : If present, specifies the GPIO that needs
235 to be pulled up for the otg bus to be powered.
236 - rockchip,remote_wakeup : If present, host can be resumed
237 from suspend state by remote wakeup signal.
238 - rockchip,usb_irq_wakeup : If present, supports usb irqs to
239 wake up the system. The usb irqs are described in ROCKCHIP
240 USB-PHY CONTROL node, which include: "otg_id","otg_bvalid",
241 "linestate" and so on.
247 compatible = "rockchip,rk3288-usb-control";
249 host_drv_gpio = <&gpio0 GPIO_B6 GPIO_ACTIVE_LOW>;
250 otg_drv_gpio = <&gpio0 GPIO_B4 GPIO_ACTIVE_LOW>;
252 rockchip,remote_wakeup;
253 rockchip,usb_irq_wakeup;