1 * Synopsys DesignWare ABP UART
4 - compatible : "snps,dw-apb-uart"
5 - reg : offset and length of the register set for the device.
6 - interrupts : should contain uart interrupt.
9 The clock rate of the input clock needs to be supplied by one of
10 - clock-frequency : the input clock frequency for the UART.
11 - clocks : phandle to the input clock
13 The supplying peripheral clock can also be handled, needing a second property
14 - clock-names: tuple listing input clock names.
15 Required elements: "baudclk", "apb_pclk"
18 - resets : phandle to the parent reset controller.
19 - reg-shift : quantity to shift the register offsets by. If this property is
20 not present then the register offsets are not shifted.
21 - reg-io-width : the size (in bytes) of the IO accesses that should be
22 performed on the device. If this property is not present then single byte
28 compatible = "snps,dw-apb-uart";
29 reg = <0x80230000 0x100>;
30 clock-frequency = <3686400>;
36 Example with one clock:
39 compatible = "snps,dw-apb-uart";
40 reg = <0x80230000 0x100>;
47 Example with two clocks:
50 compatible = "snps,dw-apb-uart";
51 reg = <0x80230000 0x100>;
52 clocks = <&baudclk>, <&apb_pclk>;
53 clock-names = "baudclk", "apb_pclk";