5 - compatible : must be "rockchip,rk3399-typec-phy"
6 - reg: Address and length of the usb phy control register set
7 - rockchip,grf : phandle to the syscon managing the "general
9 - clocks : phandle + clock specifier for the phy clocks
10 - clock-names : string, clock name, must be "tcpdcore", "tcpdphy-ref";
11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
12 <&cru SCLK_UPHY1_TCPDCORE>;
13 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
14 - resets : a list of phandle + reset specifier pairs
15 - reset-names : string reset name, must be:
16 "uphy", "uphy-pipe", "uphy-tcphy"
17 - extcon : extcon specifier for the Power Delivery
18 - #phy-cells: must be 1. create 2 PHY node:
19 <&tcphy0 0> and <&tcphy1 0> for DP PHY.
20 <&tcphy0 1> and <&tcphy1 1> for USB3 PHY.
21 See ./phy-bindings.txt for details.
23 Note, there are 2 type-c phys for RK3399, and they are almost identical, except
24 these registers(description below), every register node contains 3 sections:
25 offset, enable bit, write mask bit.
26 - rockchip,typec-conn-dir : the register of type-c connector direction,
27 for type-c phy0, it must be <0xe580 0 16>;
28 for type-c phy1, it must be <0xe58c 0 16>;
29 - rockchip,usb3tousb2-en : the register of type-c force usb3 to usb2 enable
31 for type-c phy0, it must be <0xe580 3 19>;
32 for type-c phy1, it must be <0xe58c 3 19>;
33 - rockchip,external-psm : the register of type-c phy external psm clock
35 for type-c phy0, it must be <0xe588 14 30>;
36 for type-c phy1, it must be <0xe594 14 30>;
37 - rockchip,pipe-status : the register of type-c phy pipe status.
38 for type-c phy0, it must be <0xe5c0 0 0>;
39 for type-c phy1, it must be <0xe5c0 16 16>;
40 - rockchip,uphy-dp-sel : the register of type-c phy selection for DP
41 for type-c phy0, it must be <0x6268 19 19>;
42 for type-c phy1, it must be <0x6268 3 19>;
45 tcphy0: phy@ff7c0000 {
46 compatible = "rockchip,rk3399-typec-phy";
47 reg = <0x0 0xff7c0000 0x0 0x40000>;
48 rockchip,grf = <&grf>;
51 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
52 <&cru SCLK_UPHY0_TCPDPHY_REF>;
53 clock-names = "tcpdcore", "tcpdphy-ref";
54 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
55 assigned-clock-rates = <50000000>;
56 resets = <&cru SRST_UPHY0>,
57 <&cru SRST_UPHY0_PIPE_L00>,
58 <&cru SRST_P_UPHY0_TCPHY>;
59 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
60 rockchip,typec-conn-dir = <0xe580 0 16>;
61 rockchip,usb3tousb2-en = <0xe580 3 19>;
62 rockchip,external-psm = <0xe588 14 30>;
63 rockchip,pipe-status = <0xe5c0 0 0>;
64 rockchip,uphy-dp-sel = <0x6268 19 19>;
67 tcphy1: phy@ff800000 {
68 compatible = "rockchip,rk3399-typec-phy";
69 reg = <0x0 0xff800000 0x0 0x40000>;
70 rockchip,grf = <&grf>;
73 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
74 <&cru SCLK_UPHY1_TCPDPHY_REF>;
75 clock-names = "tcpdcore", "tcpdphy-ref";
76 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
77 assigned-clock-rates = <50000000>;
78 resets = <&cru SRST_UPHY1>,
79 <&cru SRST_UPHY1_PIPE_L00>,
80 <&cru SRST_P_UPHY1_TCPHY>;
81 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
82 rockchip,typec-conn-dir = <0xe58c 0 16>;
83 rockchip,usb3tousb2-en = <0xe58c 3 19>;
84 rockchip,external-psm = <0xe594 14 30>;
85 rockchip,pipe-status = <0xe5c0 16 16>;
86 rockchip,uphy-dp-sel = <0x6268 3 19>;