Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt

   1 * Renesas R-Car DMA Controller Device Tree bindings
   2
   3 Renesas R-Car Generation 2 SoCs have have multiple multi-channel DMA
   4 controller instances named DMAC capable of serving multiple clients. Channels
   5 can be dedicated to specific clients or shared between a large number of
   6 clients.
   7
   8 DMA clients are connected to the DMAC ports referenced by an 8-bit identifier
   9 called MID/RID.
  10
  11 Each DMA client is connected to one dedicated port of the DMAC, identified by
  12 an 8-bit port number called the MID/RID. A DMA controller can thus serve up to
  13 256 clients in total. When the number of hardware channels is lower than the
  14 number of clients to be served, channels must be shared between multiple DMA
  15 clients. The association of DMA clients to DMAC channels is fully dynamic and
  16 not described in these device tree bindings.
  17
  18 Required Properties:
  19
  20 - compatible: must contain "renesas,rcar-dmac"
  21
  22 - reg: base address and length of the registers block for the DMAC
  23
  24 - interrupts: interrupt specifiers for the DMAC, one for each entry in
  25   interrupt-names.
  26 - interrupt-names: one entry per channel, named "ch%u", where %u is the
  27   channel number ranging from zero to the number of channels minus one.
  28
  29 - clock-names: "fck" for the functional clock
  30 - clocks: a list of phandle + clock-specifier pairs, one for each entry
  31   in clock-names.
  32 - clock-names: must contain "fck" for the functional clock.
  33
  34 - #dma-cells: must be <1>, the cell specifies the MID/RID of the DMAC port
  35   connected to the DMA client
  36 - dma-channels: number of DMA channels
  37
  38 Example: R8A7790 (R-Car H2) SYS-DMACs
  39
  40         dmac0: dma-controller@e6700000 {
  41                 compatible = "renesas,rcar-dmac";
  42                 reg = <0 0xe6700000 0 0x20000>;
  43                 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
  44                               0 200 IRQ_TYPE_LEVEL_HIGH
  45                               0 201 IRQ_TYPE_LEVEL_HIGH
  46                               0 202 IRQ_TYPE_LEVEL_HIGH
  47                               0 203 IRQ_TYPE_LEVEL_HIGH
  48                               0 204 IRQ_TYPE_LEVEL_HIGH
  49                               0 205 IRQ_TYPE_LEVEL_HIGH
  50                               0 206 IRQ_TYPE_LEVEL_HIGH
  51                               0 207 IRQ_TYPE_LEVEL_HIGH
  52                               0 208 IRQ_TYPE_LEVEL_HIGH
  53                               0 209 IRQ_TYPE_LEVEL_HIGH
  54                               0 210 IRQ_TYPE_LEVEL_HIGH
  55                               0 211 IRQ_TYPE_LEVEL_HIGH
  56                               0 212 IRQ_TYPE_LEVEL_HIGH
  57                               0 213 IRQ_TYPE_LEVEL_HIGH
  58                               0 214 IRQ_TYPE_LEVEL_HIGH>;
  59                 interrupt-names = "error",
  60                                 "ch0", "ch1", "ch2", "ch3",
  61                                 "ch4", "ch5", "ch6", "ch7",
  62                                 "ch8", "ch9", "ch10", "ch11",
  63                                 "ch12", "ch13", "ch14";
  64                 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
  65                 clock-names = "fck";
  66                 #dma-cells = <1>;
  67                 dma-channels = <15>;
  68         };
  69
  70         dmac1: dma-controller@e6720000 {
  71                 compatible = "renesas,rcar-dmac";
  72                 reg = <0 0xe6720000 0 0x20000>;
  73                 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
  74                               0 216 IRQ_TYPE_LEVEL_HIGH
  75                               0 217 IRQ_TYPE_LEVEL_HIGH
  76                               0 218 IRQ_TYPE_LEVEL_HIGH
  77                               0 219 IRQ_TYPE_LEVEL_HIGH
  78                               0 308 IRQ_TYPE_LEVEL_HIGH
  79                               0 309 IRQ_TYPE_LEVEL_HIGH
  80                               0 310 IRQ_TYPE_LEVEL_HIGH
  81                               0 311 IRQ_TYPE_LEVEL_HIGH
  82                               0 312 IRQ_TYPE_LEVEL_HIGH
  83                               0 313 IRQ_TYPE_LEVEL_HIGH
  84                               0 314 IRQ_TYPE_LEVEL_HIGH
  85                               0 315 IRQ_TYPE_LEVEL_HIGH
  86                               0 316 IRQ_TYPE_LEVEL_HIGH
  87                               0 317 IRQ_TYPE_LEVEL_HIGH
  88                               0 318 IRQ_TYPE_LEVEL_HIGH>;
  89                 interrupt-names = "error",
  90                                 "ch0", "ch1", "ch2", "ch3",
  91                                 "ch4", "ch5", "ch6", "ch7",
  92                                 "ch8", "ch9", "ch10", "ch11",
  93                                 "ch12", "ch13", "ch14";
  94                 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
  95                 clock-names = "fck";
  96                 #dma-cells = <1>;
  97                 dma-channels = <15>;
  98         };