1 device-tree bindings for rockchip soc display controller (vop)
3 VOP (Visual Output Processor) is the Display Controller for the Rockchip
4 series of SoCs which transfers the image data from a video memory
5 buffer to an external LCD interface.
8 - compatible: value should be one of the following
10 "rockchip,rk3288-vop";
11 "rockchip,rk3368-vop";
12 "rockchip,rk3366-vop";
13 "rockchip,rk3399-vop-big";
14 "rockchip,rk3399-vop-lit";
15 "rockchip,rk322x-vop";
16 "rockchip,rk3328-vop";
18 - interrupts: should contain a list of all VOP IP block interrupts in the
19 order: VSYNC, LCD_SYSTEM. The interrupt specifier
20 format depends on the interrupt controller used.
22 - clocks: must include clock specifiers corresponding to entries in the
25 - clock-names: Must contain
26 aclk_vop: for ddr buffer transfer.
27 hclk_vop: for ahb bus to R/W the phy regs.
28 dclk_vop: pixel clock.
30 - resets: Must contain an entry for each entry in reset-names.
31 See ../reset/reset.txt for details.
32 - reset-names: Must include the following entries:
37 - iommus: required a iommu node
39 - port: A port node with endpoint definitions as defined in
40 Documentation/devicetree/bindings/media/video-interfaces.txt.
43 SoC specific DT entry:
45 compatible = "rockchip,rk3288-vop";
46 reg = <0xff930000 0x19c>;
47 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
48 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
49 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
50 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
51 reset-names = "axi", "ahb", "dclk";
56 vopb_out_edp: endpoint@0 {
58 remote-endpoint=<&edp_in_vopb>;
60 vopb_out_hdmi: endpoint@1 {
62 remote-endpoint=<&hdmi_in_vopb>;