Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt

   1 Rockchip specific extensions to the Synopsys Designware MIPI DSI
   2 ================================
   3
   4 Required properties:
   5 - #address-cells: Should be <1>.
   6 - #size-cells: Should be <0>.
   7 - compatible: must be one of:
   8         "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi".
   9         "rockchip,rk3366-mipi-dsi", "snps,dw-mipi-dsi".
  10         "rockchip,rk3368-mipi-dsi", "snps,dw-mipi-dsi".
  11         "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi".
  12 - reg: Represent the physical address range of the controller.
  13 - interrupts: Represent the controller's interrupt to the CPU(s).
  14 - clocks, clock-names: Phandles to the controller's APB clock(pclk) as
  15   described in [1].
  16 - rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
  17 - ports: contain a port node with endpoint definitions as defined in [2].
  18   For vopb,set the reg = <0> and set the reg = <1> for vopl.
  19
  20 Optional properties
  21 - clocks, clock-names: phandle to the mipi dsi phy config clock, name should be
  22   "phy_cfg".phandle to the mipi dsi phy reference clock, name should be 'ref'.
  23 - phys: phandle to third party MIPI PHY node
  24 - phy-names: the string "mipi_dphy" when is found in a node, along with "phys"
  25   attribute, provides phandle to MIPI PHY node
  26 - resets : phandle to the reset of MIPI DSI APB Clock.
  27 - reset-names : should be "apb".
  28
  29 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
  30 [2] Documentation/devicetree/bindings/media/video-interfaces.txt
  31 [3] Documentation/devicetree/bindings/reset/reset.txt
  32
  33 Example:
  34
  35 For Rockchip RK3288:
  36
  37         mipi_dsi: mipi@ff960000 {
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
  41                 reg = <0xff960000 0x4000>;
  42                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
  43                 clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPI_DSI0>,
  44                          <&cru SCLK_DPHY_TX0_CFG>;
  45                 clock-names = "ref", "pclk", "phy_cfg";
  46                 rockchip,grf = <&grf>;
  47                 status = "okay";
  48
  49                 ports {
  50                         #address-cells = <1>;
  51                         #size-cells = <0>;
  52                         reg = <1>;
  53
  54                         mipi_in: port {
  55                                 #address-cells = <1>;
  56                                 #size-cells = <0>;
  57                                 mipi_in_vopb: endpoint@0 {
  58                                         reg = <0>;
  59                                         remote-endpoint = <&vopb_out_mipi>;
  60                                 };
  61                                 mipi_in_vopl: endpoint@1 {
  62                                         reg = <1>;
  63                                         remote-endpoint = <&vopl_out_mipi>;
  64                                 };
  65                         };
  66                 };
  67
  68                 panel {
  69                         compatible ="boe,tv080wum-nl0";
  70                         reg = <0>;
  71
  72                         enable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
  73                         pinctrl-names = "default";
  74                         pinctrl-0 = <&lcd_en>;
  75                         backlight = <&backlight>;
  76                         status = "okay";
  77                 };
  78         };
  79
  80 For Rockchip RK3368:
  81
  82 mipi_dsi_host: mipi-dsi-host@ff960000 {
  83         compatible = "rockchip,rk3368-mipi-dsi";
  84         phys = <&mipi_dphy>;
  85         phy-names = "mipi_dphy";
  86         resets = <&cru SRST_MIPIDSI0>;
  87         reset-names = "apb";
  88         ...
  89
  90         ports@1 {
  91                 #address-cells = <1>;
  92                 #size-cells = <0>;
  93                 reg = <1>;
  94
  95                 mipi_in: port {
  96                         #address-cells = <1>;
  97                         #size-cells = <0>;
  98
  99                         mipi_in_vop: endpoint@0 {
 100                                 reg = <0>;
 101                                 remote-endpoint = <&vop_out_mipi>;
 102                         };
 103                 };
 104         };
 105
 106         dsi_panel: panel@0 {
 107                 compatible = "simple-panel-dsi";
 108                 reg = <0>;
 109                 dsi,lanes = <4>;
 110                 ...
 111         };
 112 };