1 =====================================================================
2 SEC 4 Device Tree Binding
3 Copyright (C) 2008-2011 Freescale Semiconductor Inc.
9 -Run Time Integrity Check (RTIC) Node
10 -Run Time Integrity Check (RTIC) Memory Node
11 -Secure Non-Volatile Storage (SNVS) Node
12 -Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
15 NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator
16 Accelerator and Assurance Module (CAAM).
18 =====================================================================
23 SEC 4 h/w can process requests from 2 types of sources.
24 1. DPAA Queue Interface (HW interface between Queue Manager & SEC 4).
25 2. Job Rings (HW interface between cores & SEC 4 registers).
27 High Speed Data Path Configuration:
29 HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
30 such as the P4080. The number of simultaneous dequeues the QI can make is
31 equal to the number of Descriptor Controller (DECO) engines in a particular
32 SEC version. E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus
33 dequeue from 5 subportals simultaneously.
35 Job Ring Data Path Configuration:
37 Each JR is located on a separate 4k page, they may (or may not) be made visible
38 in the memory partition devoted to a particular core. The P4080 has 4 JRs, so
39 up to 4 JRs can be configured; and all 4 JRs process requests in parallel.
41 =====================================================================
46 Node defines the base address of the SEC 4 block.
47 This block specifies the address range of all global
48 configuration registers for the SEC 4 block. It
49 also receives interrupts from the Run Time Integrity Check
50 (RTIC) function within the SEC 4 block.
57 Definition: Must include "fsl,sec-v4.0"
62 Definition: A standard property. Define the 'ERA' of the SEC
68 Definition: A standard property. Defines the number of cells
69 for representing physical addresses in child nodes.
74 Definition: A standard property. Defines the number of cells
75 for representing the size of physical addresses in
80 Value type: <prop-encoded-array>
81 Definition: A standard property. Specifies the physical
82 address and length of the SEC4 configuration registers.
87 Value type: <prop-encoded-array>
88 Definition: A standard property. Specifies the physical address
89 range of the SEC 4.0 register space (-SNVS not included). A
90 triplet that includes the child address, parent address, &
95 Value type: <prop_encoded-array>
96 Definition: Specifies the interrupts generated by this
97 device. The value of the interrupts property
98 consists of one interrupt specifier. The format
99 of the specifier is defined by the binding document
100 describing the node's interrupt parent.
103 Usage: (required if interrupt property is defined)
104 Value type: <phandle>
105 Definition: A single <phandle> value that points
106 to the interrupt parent to which the child domain
110 Usage: required if SEC 4.0 requires explicit enablement of clocks
111 Value type: <prop_encoded-array>
112 Definition: A list of phandle and clock specifier pairs describing
113 the clocks required for enabling and disabling SEC 4.0.
116 Usage: required if SEC 4.0 requires explicit enablement of clocks
118 Definition: A list of clock name strings in the same order as the
121 Note: All other standard properties (see the ePAPR) are allowed
127 compatible = "fsl,sec-v4.0";
129 #address-cells = <1>;
131 reg = <0x300000 0x10000>;
132 ranges = <0 0x300000 0x10000>;
133 interrupt-parent = <&mpic>;
135 clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
136 <&clks IMX6QDL_CLK_CAAM_ACLK>,
137 <&clks IMX6QDL_CLK_CAAM_IPG>,
138 <&clks IMX6QDL_CLK_EIM_SLOW>;
139 clock-names = "mem", "aclk", "ipg", "emi_slow";
142 =====================================================================
145 Child of the crypto node defines data processing interface to SEC 4
146 across the peripheral bus for purposes of processing
147 cryptographic descriptors. The specified address
148 range can be made visible to one (or more) cores.
149 The interrupt defined for this node is controlled within
150 the address range of this node.
155 Definition: Must include "fsl,sec-v4.0-job-ring"
159 Value type: <prop-encoded-array>
160 Definition: Specifies a two JR parameters: an offset from
161 the parent physical address and the length the JR registers.
164 Usage: optional-but-recommended
165 Value type: <prop-encoded-array>
167 Specifies the LIODN to be used in conjunction with
168 the ppid-to-liodn table that specifies the PPID to LIODN mapping.
169 Needed if the PAMU is used. Value is a 12 bit value
170 where value is a LIODN ID for this JR. This property is
171 normally set by boot firmware.
175 Value type: <prop_encoded-array>
176 Definition: Specifies the interrupts generated by this
177 device. The value of the interrupts property
178 consists of one interrupt specifier. The format
179 of the specifier is defined by the binding document
180 describing the node's interrupt parent.
183 Usage: (required if interrupt property is defined)
184 Value type: <phandle>
185 Definition: A single <phandle> value that points
186 to the interrupt parent to which the child domain
191 compatible = "fsl,sec-v4.0-job-ring";
192 reg = <0x1000 0x1000>;
194 interrupt-parent = <&mpic>;
199 =====================================================================
200 Run Time Integrity Check (RTIC) Node
202 Child node of the crypto node. Defines a register space that
203 contains up to 5 sets of addresses and their lengths (sizes) that
204 will be checked at run time. After an initial hash result is
205 calculated, these addresses are checked by HW to monitor any
206 change. If any memory is modified, a Security Violation is
207 triggered (see SNVS definition).
213 Definition: Must include "fsl,sec-v4.0-rtic".
218 Definition: A standard property. Defines the number of cells
219 for representing physical addresses in child nodes. Must
225 Definition: A standard property. Defines the number of cells
226 for representing the size of physical addresses in
227 child nodes. Must have a value of 1.
231 Value type: <prop-encoded-array>
232 Definition: A standard property. Specifies a two parameters:
233 an offset from the parent physical address and the length
238 Value type: <prop-encoded-array>
239 Definition: A standard property. Specifies the physical address
240 range of the SEC 4 register space (-SNVS not included). A
241 triplet that includes the child address, parent address, &
246 compatible = "fsl,sec-v4.0-rtic";
247 #address-cells = <1>;
249 reg = <0x6000 0x100>;
250 ranges = <0x0 0x6100 0xe00>;
253 =====================================================================
254 Run Time Integrity Check (RTIC) Memory Node
255 A child node that defines individual RTIC memory regions that are used to
256 perform run-time integrity check of memory areas that should not modified.
257 The node defines a register that contains the memory address &
258 length (combined) and a second register that contains the hash result
259 in big endian format.
264 Definition: Must include "fsl,sec-v4.0-rtic-memory".
268 Value type: <prop-encoded-array>
269 Definition: A standard property. Specifies two parameters:
270 an offset from the parent physical address and the length:
272 1. The location of the RTIC memory address & length registers.
273 2. The location RTIC hash result.
276 Usage: optional-but-recommended
277 Value type: <prop-encoded-array>
279 Specifies the HW address (36 bit address) for this region
280 followed by the length of the HW partition to be checked;
281 the address is represented as a 64 bit quantity followed
285 Usage: optional-but-recommended
286 Value type: <prop-encoded-array>
288 Specifies the LIODN to be used in conjunction with
289 the ppid-to-liodn table that specifies the PPID to LIODN
290 mapping. Needed if the PAMU is used. Value is a 12 bit value
291 where value is a LIODN ID for this RTIC memory region. This
292 property is normally set by boot firmware.
296 compatible = "fsl,sec-v4.0-rtic-memory";
297 reg = <0x00 0x20 0x100 0x80>;
299 fsl,rtic-region = <0x12345678 0x12345678 0x12345678>;
302 =====================================================================
303 Secure Non-Volatile Storage (SNVS) Node
305 Node defines address range and the associated
306 interrupt for the SNVS function. This function
307 monitors security state information & reports
313 Definition: Must include "fsl,sec-v4.0-mon".
317 Value type: <prop-encoded-array>
318 Definition: A standard property. Specifies the physical
319 address and length of the SEC4 configuration
325 Definition: A standard property. Defines the number of cells
326 for representing physical addresses in child nodes. Must
332 Definition: A standard property. Defines the number of cells
333 for representing the size of physical addresses in
334 child nodes. Must have a value of 1.
338 Value type: <prop-encoded-array>
339 Definition: A standard property. Specifies the physical address
340 range of the SNVS register space. A triplet that includes
341 the child address, parent address, & length.
345 Value type: <prop_encoded-array>
346 Definition: Specifies the interrupts generated by this
347 device. The value of the interrupts property
348 consists of one interrupt specifier. The format
349 of the specifier is defined by the binding document
350 describing the node's interrupt parent.
353 Usage: (required if interrupt property is defined)
354 Value type: <phandle>
355 Definition: A single <phandle> value that points
356 to the interrupt parent to which the child domain
361 compatible = "fsl,sec-v4.0-mon";
362 reg = <0x314000 0x1000>;
363 ranges = <0 0x314000 0x1000>;
364 interrupt-parent = <&mpic>;
368 =====================================================================
369 Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
371 A SNVS child node that defines SNVS LP RTC.
376 Definition: Must include "fsl,sec-v4.0-mon-rtc-lp".
380 Value type: <prop-encoded-array>
381 Definition: A standard property. Specifies the physical
382 address and length of the SNVS LP configuration registers.
385 sec_mon_rtc_lp@314000 {
386 compatible = "fsl,sec-v4.0-mon-rtc-lp";
390 =====================================================================
393 crypto: crypto@300000 {
394 compatible = "fsl,sec-v4.0";
395 #address-cells = <1>;
397 reg = <0x300000 0x10000>;
398 ranges = <0 0x300000 0x10000>;
399 interrupt-parent = <&mpic>;
403 compatible = "fsl,sec-v4.0-job-ring";
404 reg = <0x1000 0x1000>;
405 interrupt-parent = <&mpic>;
410 compatible = "fsl,sec-v4.0-job-ring";
411 reg = <0x2000 0x1000>;
412 interrupt-parent = <&mpic>;
417 compatible = "fsl,sec-v4.0-job-ring";
418 reg = <0x3000 0x1000>;
419 interrupt-parent = <&mpic>;
424 compatible = "fsl,sec-v4.0-job-ring";
425 reg = <0x4000 0x1000>;
426 interrupt-parent = <&mpic>;
431 compatible = "fsl,sec-v4.0-rtic";
432 #address-cells = <1>;
434 reg = <0x6000 0x100>;
435 ranges = <0x0 0x6100 0xe00>;
438 compatible = "fsl,sec-v4.0-rtic-memory";
439 reg = <0x00 0x20 0x100 0x80>;
443 compatible = "fsl,sec-v4.0-rtic-memory";
444 reg = <0x20 0x20 0x200 0x80>;
448 compatible = "fsl,sec-v4.0-rtic-memory";
449 reg = <0x40 0x20 0x300 0x80>;
453 compatible = "fsl,sec-v4.0-rtic-memory";
454 reg = <0x60 0x20 0x500 0x80>;
459 sec_mon: sec_mon@314000 {
460 compatible = "fsl,sec-v4.0-mon";
461 reg = <0x314000 0x1000>;
462 ranges = <0 0x314000 0x1000>;
463 interrupt-parent = <&mpic>;
467 compatible = "fsl,sec-v4.0-mon-rtc-lp";
472 =====================================================================