1 * Rockchip RK3399 Clock and Reset Unit
3 The RK3399 clock controller generates and supplies clock to various
4 controllers within the SoC and also implements a reset controller for SoC
9 - compatible: PMU for CRU should be "rockchip,rk3399-pmu-cru"
10 - compatible: CRU should be "rockchip,rk3399-cru"
11 - reg: physical base address of the controller and length of memory mapped
13 - #clock-cells: should be 1.
14 - #reset-cells: should be 1.
18 - rockchip,grf: phandle to the syscon managing the "general register files"
19 If missing, pll rates are not changeable, due to the missing pll lock status.
21 Each clock is assigned an identifier and client nodes can use this identifier
22 to specify the clock which they consume. All available clocks are defined as
23 preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be
24 used in device tree sources. Similar macros exist for the reset sources in
29 There are several clocks that are generated outside the SoC. It is expected
30 that they are defined using standard clock bindings with following
32 - "xin24m" - crystal input - required,
33 - "xin32k" - rtc clock - optional,
34 - "ext_i2s" - external I2S clock - optional,
35 - "ext_gmac" - external GMAC clock - optional
36 - "ext_hsadc" - external HSADC clock - optional,
37 - "ext_isp" - external ISP clock - optional,
38 - "ext_jtag" - external JTAG clock - optional
39 - "ext_vip" - external VIP clock - optional,
40 - "usbotg_out" - output clock of the pll in the otg phy
42 Example: Clock controller node:
44 pmu_cru: pmu-clock-controller@ff750000 {
45 compatible = "rockchip,rk3399-pmu-cru";
46 reg = <0x0 0xff750000 0x0 0x1000>;
51 cru: clock-controller@ff760000 {
52 compatible = "rockchip,rk3399-cru";
53 reg = <0x0 0xff760000 0x0 0x1000>;
54 rockchip,grf = <&grf>;
59 Example: UART controller node that consumes the clock generated by the clock
62 uart0: serial@ff1a0000 {
63 compatible = "snps,dw-apb-uart";
64 reg = <0xff1a0000 0x1000>;
65 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
68 clocks = <&cru SCLK_UART0>, <&cru_pmu PMU_SCLK_UART>;