1 * ARM Generic Interrupt Controller, version 3
3 AArch64 SMP cores are often associated with a GICv3, providing Private
4 Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI),
5 Software Generated Interrupts (SGI), and Locality-specific Peripheral
8 Main node required properties:
10 - compatible : should at least contain "arm,gic-v3".
11 - interrupt-controller : Identifies the node as an interrupt controller
12 - #interrupt-cells : Specifies the number of cells needed to encode an
13 interrupt source. Must be a single cell with a value of at least 3.
15 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
16 interrupts. Other values are reserved for future use.
18 The 2nd cell contains the interrupt number for the interrupt type.
19 SPI interrupts are in the range [0-987]. PPI interrupts are in the
22 The 3rd cell is the flags, encoded as follows:
23 bits[3:0] trigger type and level flags.
27 Cells 4 and beyond are reserved for future use. When the 1st cell
28 has a value of 0 or 1, cells 4 and beyond act as padding, and may be
29 ignored. It is recommended that padding cells have a value of 0.
31 - reg : Specifies base physical address(s) and size of the GIC
32 registers, in the following order:
33 - GIC Distributor interface (GICD)
34 - GIC Redistributors (GICR), one range per redistributor region
35 - GIC CPU interface (GICC)
36 - GIC Hypervisor interface (GICH)
37 - GIC Virtual CPU interface (GICV)
39 GICC, GICH and GICV are optional.
41 - interrupts : Interrupt source of the VGIC maintenance interrupt.
45 - redistributor-stride : If using padding pages, specifies the stride
46 of consecutive redistributors. Must be a multiple of 64kB.
48 - #redistributor-regions: The number of independent contiguous regions
49 occupied by the redistributors. Required if more than one such
54 gic: interrupt-controller@2cf00000 {
55 compatible = "arm,gic-v3";
56 #interrupt-cells = <3>;
58 reg = <0x0 0x2f000000 0 0x10000>, // GICD
59 <0x0 0x2f100000 0 0x200000>, // GICR
60 <0x0 0x2c000000 0 0x2000>, // GICC
61 <0x0 0x2c010000 0 0x2000>, // GICH
62 <0x0 0x2c020000 0 0x2000>; // GICV
66 gic: interrupt-controller@2c010000 {
67 compatible = "arm,gic-v3";
68 #interrupt-cells = <3>;
70 redistributor-stride = <0x0 0x40000>; // 256kB stride
71 #redistributor-regions = <2>;
72 reg = <0x0 0x2c010000 0 0x10000>, // GICD
73 <0x0 0x2d000000 0 0x800000>, // GICR 1: CPUs 0-31
74 <0x0 0x2e000000 0 0x800000>; // GICR 2: CPUs 32-63
75 <0x0 0x2c040000 0 0x2000>, // GICC
76 <0x0 0x2c060000 0 0x2000>, // GICH
77 <0x0 0x2c080000 0 0x2000>; // GICV