5 The device tree allows to describe the layout of CPUs in a system through
6 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
7 defining properties for every cpu.
9 Bindings for CPU nodes follow the ePAPR v1.1 standard, available from:
11 https://www.power.org/documentation/epapr-version-1-1/
13 with updates for 32-bit and 64-bit ARM systems provided in this document.
15 ================================
16 Convention used in this document
17 ================================
19 This document follows the conventions described in the ePAPR v1.1, with
22 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
23 the reg property contained in bits 7 down to 0
25 =====================================
26 cpus and cpu node bindings definition
27 =====================================
29 The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu
30 nodes to be present and contain the properties described below.
34 Description: Container of cpu nodes
36 The node name must be "cpus".
38 A cpus node must define the following properties:
44 Definition depends on ARM architecture version and
47 # On uniprocessor ARM architectures previous to v7
48 value must be 1, to enable a simple enumeration
49 scheme for processors that do not have a HW CPU
50 identification register.
51 # On 32-bit ARM 11 MPcore, ARM v7 or later systems
52 value must be 1, that corresponds to CPUID/MPIDR
54 # On ARM v8 64-bit systems value should be set to 2,
55 that corresponds to the MPIDR_EL1 register size.
56 If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
57 in the system, #address-cells can be set to 1, since
58 MPIDR_EL1[63:32] bits are not used for CPUs
63 Definition: must be set to 0
67 Description: Describes a CPU in an ARM based system
74 Definition: must be "cpu"
76 Usage and definition depend on ARM architecture version and
79 # On uniprocessor ARM architectures previous to v7
80 this property is required and must be set to 0.
82 # On ARM 11 MPcore based systems this property is
83 required and matches the CPUID[11:0] register bits.
85 Bits [11:0] in the reg cell must be set to
86 bits [11:0] in CPU ID register.
88 All other bits in the reg cell must be set to 0.
90 # On 32-bit ARM v7 or later systems this property is
91 required and matches the CPU MPIDR[23:0] register
94 Bits [23:0] in the reg cell must be set to
97 All other bits in the reg cell must be set to 0.
99 # On ARM v8 64-bit systems this property is required
100 and matches the MPIDR_EL1 register affinity bits.
102 * If cpus node's #address-cells property is set to 2
104 The first reg cell bits [7:0] must be set to
105 bits [39:32] of MPIDR_EL1.
107 The second reg cell bits [23:0] must be set to
108 bits [23:0] of MPIDR_EL1.
110 * If cpus node's #address-cells property is set to 1
112 The reg cell bits [23:0] must be set to bits [23:0]
115 All other bits in the reg cells must be set to 0.
120 Definition: should be one of:
181 Value type: <stringlist>
182 Usage and definition depend on ARM architecture version.
183 # On ARM v8 64-bit this property is required and must
187 # On ARM 32-bit systems this property is optional and
189 "allwinner,sun6i-a31"
192 "marvell,armada-375-smp"
193 "marvell,armada-380-smp"
194 "marvell,armada-xp-smp"
198 "rockchip,rk3066-smp"
201 Usage: required for systems that have an "enable-method"
202 property value of "spin-table".
203 Value type: <prop-encoded-array>
205 # On ARM v8 64-bit systems must be a two cell
206 property identifying a 64-bit zero-initialised
210 Usage: required for systems that have an "enable-method"
211 property value of "qcom,kpss-acc-v1" or
213 Value type: <phandle>
214 Definition: Specifies the SAW[1] node associated with this CPU.
217 Usage: required for systems that have an "enable-method"
218 property value of "qcom,kpss-acc-v1" or
220 Value type: <phandle>
221 Definition: Specifies the ACC[2] node associated with this CPU.
225 Value type: <prop-encoded-array>
227 # List of phandles to idle state nodes supported
230 Example 1 (dual-cluster big.LITTLE system 32-bit):
234 #address-cells = <1>;
238 compatible = "arm,cortex-a15";
244 compatible = "arm,cortex-a15";
250 compatible = "arm,cortex-a7";
256 compatible = "arm,cortex-a7";
261 Example 2 (Cortex-A8 uniprocessor 32-bit system):
265 #address-cells = <1>;
269 compatible = "arm,cortex-a8";
274 Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
278 #address-cells = <1>;
282 compatible = "arm,arm926ej-s";
287 Example 4 (ARM Cortex-A57 64-bit system):
291 #address-cells = <2>;
295 compatible = "arm,cortex-a57";
297 enable-method = "spin-table";
298 cpu-release-addr = <0 0x20000000>;
303 compatible = "arm,cortex-a57";
305 enable-method = "spin-table";
306 cpu-release-addr = <0 0x20000000>;
311 compatible = "arm,cortex-a57";
313 enable-method = "spin-table";
314 cpu-release-addr = <0 0x20000000>;
319 compatible = "arm,cortex-a57";
321 enable-method = "spin-table";
322 cpu-release-addr = <0 0x20000000>;
327 compatible = "arm,cortex-a57";
329 enable-method = "spin-table";
330 cpu-release-addr = <0 0x20000000>;
335 compatible = "arm,cortex-a57";
337 enable-method = "spin-table";
338 cpu-release-addr = <0 0x20000000>;
343 compatible = "arm,cortex-a57";
345 enable-method = "spin-table";
346 cpu-release-addr = <0 0x20000000>;
351 compatible = "arm,cortex-a57";
353 enable-method = "spin-table";
354 cpu-release-addr = <0 0x20000000>;
359 compatible = "arm,cortex-a57";
361 enable-method = "spin-table";
362 cpu-release-addr = <0 0x20000000>;
367 compatible = "arm,cortex-a57";
369 enable-method = "spin-table";
370 cpu-release-addr = <0 0x20000000>;
375 compatible = "arm,cortex-a57";
377 enable-method = "spin-table";
378 cpu-release-addr = <0 0x20000000>;
383 compatible = "arm,cortex-a57";
385 enable-method = "spin-table";
386 cpu-release-addr = <0 0x20000000>;
391 compatible = "arm,cortex-a57";
393 enable-method = "spin-table";
394 cpu-release-addr = <0 0x20000000>;
399 compatible = "arm,cortex-a57";
401 enable-method = "spin-table";
402 cpu-release-addr = <0 0x20000000>;
407 compatible = "arm,cortex-a57";
409 enable-method = "spin-table";
410 cpu-release-addr = <0 0x20000000>;
415 compatible = "arm,cortex-a57";
417 enable-method = "spin-table";
418 cpu-release-addr = <0 0x20000000>;
423 [1] arm/msm/qcom,saw2.txt
424 [2] arm/msm/qcom,kpss-acc.txt
425 [3] ARM Linux kernel documentation - idle states bindings
426 Documentation/devicetree/bindings/arm/idle-states.txt